JP2954988B2 - Information processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus such as a personal computer, and particularly to an Industry Standard Archit.
It relates to an information processing device conforming to ecture.

2. Description of the Related Art Conventionally, as an architecture of a small information processing apparatus such as a personal computer, an industry standard architecture (hereinafter, abbreviated as ISA) has been widely used.

FIG. 8 is a diagram showing a basic configuration of a circuit board constituting a personal computer conforming to the ISA, and FIG. 9 is a basic memory map defined in the ISA.

In FIG. 8, 1 is a main board, 2 is a slot which is mounted on the main board and is a connector for connecting various adapters, 3 is an adapter board, 4 is mounted on the main board 1, and A basic ROM (read only memory) 5 for storing a basic input / output control program of the computer, an adapter ROM 5 mounted on the adapter board 3 and storing programs and data necessary for making the adapter board 3 function. ing.

In the ISA, various adapter boards are inserted into one or a plurality of slots 2 mounted on the main board 1 so that
An important feature is the ability to extend the functionality of personal computers.

Since it is impossible to store a control program for an unspecified adapter in the basic ROM 4 in advance, each adapter board inserted into the ISA stores its own control program in the adapter ROM 5.

The address space allocated to the adapter ROM is ninth.
As shown in the figure, OCOOOOH (the letter "H" at the end indicates hexadecimal notation) is set to 128 kByte of ODFFFFH, and this space is allocated to the adapter ROMs provided on each of a plurality of adapter boards. use.

The ISA supports data transfer with the adapter board in units of 16 bits and data transfer in units of 8 bits. The data transfer in units of 16 bits and the data transfer in units of 8 bits are supported. Switching is 128k
It can be performed only for each address space divided in Byte units.

On the other hand, since the adapter ROM normally uses an address space divided into units of 8 kBytes, data transfer in units of 16 bits cannot be used. Bit-wise data transfer must be used.

Moreover, the transfer speed of the data transfer in units of 8 bits is half the transfer speed of the data transfer in units of 16 bits. Therefore, the number of times of reading is double as compared with the case where reading can be performed in units of 16 bits, and the time required for one transfer is also doubled.

For this reason, there is a limitation that the time required for reading from the adapter ROM is four times the time required for reading from the basic ROM that can be accessed in 16-bit units, which is a problem in improving performance. Had become.

Conventionally, to address this issue, No. 10, 11, 12, 13
The technology shown in the figure was employed.

10 and 11 show a first conventional example, FIG. 10 shows a basic configuration of a circuit board of a personal computer in the first conventional example, and FIG. 11 shows a first conventional example. It is a memory map.

12 and 13 show a second conventional example, FIG. 12 shows a basic configuration of a circuit board of a personal computer in the second conventional example, and FIG. 13 shows a second conventional example. It is a memory map.

In FIGS. 8 to 13, the same components are denoted by the same reference numerals.

First, a first conventional example will be described with reference to FIGS. 10 and 11. FIG.

In FIG. 10, reference numeral 6 denotes a circuit portion for realizing the functions realized by the conventional adapter substrate by incorporating them on the main substrate 1.

In recent years, with the development of semiconductor technology, it has become possible to integrate more functions than ever before on a substrate of the same size.

In the first conventional example, in accordance with such a background, a function previously realized by inserting the adapter board 3 into the slot 2 is built in the main board 1 as a circuit portion 6,
It can be used as a standard function.

In the configuration of the first conventional example, a control program corresponding to this is required to make the circuit portion 6 function effectively.

For this purpose, as shown in the memory map of FIG. 11, the capacity of the basic ROM 4 is doubled, the increase is allocated to the addresses OEOOOOH to OEFFFFH, which are spare areas for expansion, and the control program is stored here.

However, in this case, since the spare area is occupied by a specific application, there is a fear that inconvenience may occur for an application that uses this area for some purpose.

Next, a second conventional example will be described with reference to FIGS. 12 and 13. FIG.

In this conventional example, the configuration of the circuit board is the same as that of the first conventional example. However, as shown in the memory map of FIG.
ROM for each unit with a certain capacity as a unit for OFFFFFH
And a bank-switchable RAM (random access memory) which can be switched to a corresponding address.

Then, the storage contents of the basic ROM 4 and the storage contents of the adapter ROM 5 are all read, written on this RAM, a copy is made, the bank is switched, and the RAM is switched to the ROM. The program of the adapter ROM5 that could only be read is read and executed faster than the copy on the RAM.

Since the RAM is placed on the main substrate 1, 16-bit reading (or, for example, a 32-bit reading in a device having a larger data bit width) becomes possible as necessary.

As a result, by executing the program stored in the adapter ROM 5 on the bank-switchable RAM, the time required for executing the program can be reduced.

However, in this case, there is a problem that several hundred kilobytes of RAM are required in addition to the RAM adapter ROM.

As this type of technology, a technology described in Japanese Patent Application Laid-Open No. 64-8214 is known.

[Problems to be Solved by the Invention] As described above, in an apparatus conforming to ISA, there is a limitation that reading of an adapter ROM provided on an adapter board on a slot can be basically performed only in units of 8 bits. In contrast to the conventional technology, both the adapter board and the adapter ROM are realized as a circuit on the main board, the contents of the adapter ROM are copied to the RAM on the main board, and the program data on the RAM is used instead of the adapter ROM Technology was sometimes adopted.

However, these methods have a problem that, as described above, there is a case where the compatibility is not sufficiently guaranteed, or an extra RAM is required.

Therefore, the present invention can improve the execution speed of a program conventionally incorporated in ROM on an adapter board without occupying an extension area of a system ROM and without increasing ROM or RAM so much. And an information processing apparatus such as a personal computer compatible with ISA.

Means for Solving the Problems To achieve the above object, the present invention provides a central processing unit, a basic ROM for storing a basic input / output control program read by the central processing unit and other programs, on a main board. Relocating the basic input / output program to a system ROM area,
Further, the present invention provides an information processing apparatus comprising a relocation circuit capable of relocating the another program in a predetermined adapter ROM area.

Further, in the present information processing apparatus, when two or more of the other programs are stored in the basic ROM, the relocation circuit selectively selects one of the two or more other programs in a predetermined manner. Can be relocated to the adapter ROM area.

Also, an extension ROM for storing a program or data different from the basic ROM read by the central processing unit is provided on the main board, and the relocation circuit stores the program or data stored in the extension ROM in a system ROM extension area. It is desirable to be able to rearrange.

Further, in this case, if the capacity of the program or data stored in the extension ROM is larger than the area of the relocation destination, the relocation circuit stores the program or data stored in the extension ROM for each predetermined capacity. In this case, the plurality of banks may be divided into a plurality of banks, and one of the plurality of banks may be selectively rearranged in the system ROM extension area.

Further, it is preferable that the central processing unit includes a register for instructing the relocation circuit to perform relocation or prohibit relocation, so that the relocation can be controlled according to a process to be performed.

[Operation] According to the information processing apparatus of the present invention, the central processing unit can read the basic ROM on the main board, which is readable in units of 16-bit (or more) bits, or the adapter board or A program, data, and the like for controlling a circuit portion on the main board that realizes a function equivalent to that of the adapter board are stored, so that these functions can be realized at high speed. Adapter RO
By relocating to the M area, it is possible to read from the address defined as the read address of the adapter ROM, while making the area for expanding the system ROM available for other uses.

Further, two or more programs are stored in the basic ROM,
If the relocation circuit enables one of the two or more other programs to be selectively relocated to a predetermined adapter ROM area, the relocation circuit performs a function equivalent to two or more adapter boards or an adapter board. And can be similarly realized.

Further, the extension ROM is not necessarily required in all devices. However, when the extension ROM is provided on the main board, the extension ROM includes, for example, kanji processing, for example, a kanji character indicating a shape of a kanji character. A font, a conversion dictionary for kana-kanji conversion, and the like are stored.
Program or data stored in the system RO
By rearranging them in the M extension area, these functions can also be used in the system ROM extension area.

If the capacity of a kanji font or a conversion dictionary for kana-kanji conversion is larger than the system ROM extension area, the relocation circuit replaces the program or data stored in the extension ROM with a predetermined value. It is divided into a plurality of banks for each capacity, and one of the plurality of banks is selectively rearranged in the system ROM extension area, and all of them are made available in the system ROM extension area.

[Embodiment] An embodiment of an information processing apparatus according to the present invention will be described below using a personal computer as an example.

Here, FIG. 1 is a block diagram showing a configuration of a main part of the personal computer according to the present embodiment, FIG. 2 is a block diagram showing a basic configuration of a circuit board of the personal computer, and FIG.
FIG. 2 shows a part of the memory map of the personal computer which is particularly characteristic in this embodiment.

In FIGS. 1 and 2, FIG. 8 to FIG.
The same components as those in FIG. 12 are denoted by the same reference numerals.

FIG. 1 shows the configuration of the main substrate 1, in which FIG.
2 is a slot, 10 is an address latch that holds a ROM address to be provided to the basic ROM 4 and the extended ROM 7, and 11 is an address and bus control signal to control access by performing ROM address decoding and decoding for the control register. The decoder 12 converts the address based on the ROM address decode signal output from the decoder 11 and the mapper control signal for specifying the arrangement of the ROM, generates a ROM address, and supplies the ROM address to the basic ROM 4 and the extended ROM 7. ,13
Is a mapper control register that supplies mapper control information for specifying whether or not to perform address conversion on the mapper 12, and for specifying a conversion operation when performing the conversion, and 14 is divided for each unit capacity of the extended ROM 7. An extended ROM bank register, which stores a bank number designating which delimiter content can be arranged on the memory map from the stored content and supplies it as a part of a ROM address signal of the extended ROM 7;
5 is a buffer for sending data read from the basic ROM 4 or the extended ROM 7 onto the data bus, 16 is a CPU, 1
7 is a main memory, 18 is a control bus, 19 is an address bus, and 20 is a data bus.

In FIG. 2, 1 is a main board, 2 is a slot mounted on the main board, and a connector is a connector for connecting various adapters, 4 is mounted on the main board 1, and a basic input / output control of a personal computer is performed. Basics of storing programs
ROM 6 is a circuit portion for realizing the functions realized by the conventional adapter board by being built in the main board 1, and FIG. 7 is an expansion ROM.

FIG. 3 is a memory map showing a mapping relationship from a physical ROM address to a memory map.

In FIG. 3, the left side shows a memory map portion where a ROM can be arranged in an apparatus conforming to ISA, and the right side in FIG. 3 shows the storage contents of the basic ROM 4 and the expansion ROM 7, respectively.

As shown in FIG. 3, in this embodiment, the basic ROM
The ROM address area for storing the basic input / output program is fixedly allocated to the area of OFOOOOH to OFFFFFH in the memory map, and the remaining ROM address area is allocated to OEOOOOH to OEFFFFH, or this area is further divided into two. Then, one of the two ROM address areas is divided into the memory map OCOOOOH
It is shown that it is possible to switch between placing in the region of ~ OC7FFFFH.

In addition, the contents written in units of unit capacity of the expansion ROM are selected by specifying the bank number, and the OEOO of the memory map is selected.
This indicates that the device can be arranged in the region from OOH to OEFFFFH.

 Hereinafter, the operation of the present embodiment will be described.

In FIG. 1, before reading from the basic ROM 4 and the extended ROM 7, the CPU 16 stores in the mapper control register 13 and the extended ROM bank register 14 how the mapping of the ROM address to the memory map is performed on the mapper 12 respectively. It is necessary to set mapper control information for specifying whether to perform the operation, and an extended ROM bank number for specifying which part of the contents stored in the extended ROM can be read.

For this purpose, the decoder 11 generates a write signal for each of the mapper control register 13 and the extension bank register 14 from the address and the bus control signal, while the mapper control register 13 and the extension bank register 14 generate a write signal supplied from the decoder 11. Stores new information.

When reading the ROM, the decoder 11 decodes the upper bits of the address and reads the basic ROM 4 or the extended RO.
When an address from which M can be accessed is given, it informs mapper 12 that a ROM can be selected.

The address latch 10 latches the lower bits of the address and supplies a ROM address necessary for determining a read location of the basic ROM 4 and the extended ROM 7.

When the decoder 11 instructs access to the ROM, the mapper 12 converts the read address according to the upper bits of the address and the mapper control information given from the mapper control register 13 to determine whether to read the basic ROM 4 or the extended ROM 7. It is determined whether or not to perform the conversion and what kind of mapping relationship to follow when performing the conversion.

When instructing the mapper 12 to read the basic ROM 4, the read addresses of the basic ROM 4 are OCOOOOH to OC7FFFH, OEOOOOH to OEFFFFH, OFOOOOH to OFF as shown in FIG.
This is one of the three regions of FFFH.

When allocating the area of OEOOOOH to OEFFFFH and the area of OFOOOOOH to OFFFFFH to the basic ROM, the mapper 12 provides an output enable signal (BIOSOE # in FIG. 1) for the basic ROM 4 and sets the read address bits RA16 to RA16 to the basic ROM. It is realized by giving.

If the area from OEOOOO to OEFFFFH is not allocated to the basic ROM 4, the mapper 12
Reading is prohibited by not giving an output enable signal (BIOSOE #) to ROM4.

When allocating the address area of OCOOOO to OC7FFFH to the basic ROM 4, the ROM capacity that can be arranged in the address area of OCOOOOH to OC7FFFH is one half of the lower half of the stored content of the basic ROM 4, that is, the ROM 4 1/4, so mapper 12
Fix the ROM address bit RA15 to “0” or “1” according to the mapper control information, and
When the area of OEOOOOH to OEFFFFH, which controls to perform upper or lower reading in 2, is assigned to the extended ROM 7, the mapper 12 decodes the upper bits of the address and points to the area of OEOOOOH to OEFFFFH. Output enable signal to the expansion ROM 7 (DICOE in FIG. 1).
#)give.

Then, a bank number given from the extended ROM bank register 14 and a ROM address given from the address latch 10 are supplied, and stored contents are read from the extended ROM 7.

The mapper 12 can inhibit or permit the data output of the buffer 15 according to the contents of the mapper control register 13, so that the reading of the basic ROM 4 and the extended ROM 7 is prohibited and the mapper 12 is used for reading these ROMs. Address areas can be released for entirely different uses. That is, even when an adapter board designed to occupy these address areas is inserted into the slot, the corresponding address area can be used by the adapter board, and the existing adapter can be used.

As described above, according to the present embodiment, when functions that are conventionally connected to the adapter board are integrated on the main board, control programs and data can be stored in the basic ROM without loss of compatibility. .

In addition, as a result, it is possible to avoid the restriction that the ROM access is limited to the unit of 8 bits, so that it is possible to shorten the time required for the execution process of the program and to improve the performance of the apparatus. Further, in this embodiment, no extra RAM is required, so that an increase in cost can be prevented.

 Hereinafter, details of the present embodiment will be described.

FIGS. 4 and 5 show the correspondence between the mapper control information and the ROM content mapped to each address area when finer relocation control is performed in the address relocation mechanism of the ROM memory according to the present embodiment. FIGS. 6 and 7 show examples of logical expressions when the decoder and the mapper for performing the relocation control are realized by a PLD (Programmable Logic Device).

In the memory maps shown in FIGS. 4 and 5, basic ROOs are assigned to FEOOOOH to FFFFFFH, which is the highest address area.
The difference from the memory map shown in FIG. 3 is that the arrangement of M can be controlled.

In the memory maps of FIGS. 4 and 5, DICE
N, BIOSEN, CXEN, CXPG, and KILLBIOS are signals constituting the mapper control information set in the mapper control register 13, respectively.

When DICEN is “1”, the extension ROM is arranged in the area of addresses OEOOOOH to OEFFFFH.

When BIOSEN is “1” and KILLBIOS is “0”, the address FE
The basic ROM can be allocated to OOOOH to FFFFFFH. At this time, if CXEN is “0” and CXPG is “1”, the address FEOOOO
The lower order address half of the basic ROM is arranged in H to FEFFFFH.

When CXEN is "1", the basic RO address OCOOOOH to OC7FFFH
Either the upper or lower specified by CXPG in the lower address side 1/2 of M is arranged.

When KILLBIOS is “1”, the basic ROM does not appear on the memory map.

As described above, in the memory map shown in FIG. 4, control can be performed so that the basic ROM does not appear on the memory map, so that another memory can be arranged in the address area where the basic ROM is normally arranged.

In other words, if necessary, RAM
In this case, the available RAM area can be increased, or the adapter board can replace the basic input / output control program stored in the basic ROM by arranging which ROM. Further, there is no problem for applications in which the contents of the ROM are copied to the RAM and used as in the second conventional example described above.

As described above, according to the present embodiment, the basic ROM can be used without inconsistency in the basic memory map of the ROM memory that is conventionally standardly used in personal computers.
, And new programs and data can be stored. As a result, the ROM on the adapter board is
Since the program stored in the ROM can be read in a shorter time as compared with the case where the program is provided, it is useful to shorten the processing time. Further, in implementing this embodiment, extra RA
Since no M or the like is required, it is possible to reduce the cost, or it is possible to prevent a reduction in the available RAM capacity by not consuming extra RAM mounted on the device.

[Effects of the Invention] As described above, according to the present invention, the ROM on the conventional adapter board is built in the ROM on the conventional adapter board without occupying the extended area of the system ROM and without increasing the ROM or RAM so much. It is possible to provide an information processing apparatus such as a personal computer or the like, which is capable of improving the execution speed of a program that has been used, and is compatible with ISA.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a personal computer according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a substrate configuration of the personal computer, FIG.
FIG. 5 and FIG. 5 are explanatory diagrams showing a memory map of the personal computer. FIG. 6 and FIG.
FIG. 8 is an explanatory view showing a substrate configuration adapted to a conventional ISA,
FIG. 9 is an explanatory view showing a conventional memory map adapted to ISA, FIG. 10 is an explanatory view showing a substrate configuration according to a first conventional example, and FIG. 11 is an explanatory view showing a memory map according to the first conventional example. FIG. 12 is an explanatory diagram showing a substrate configuration according to a second conventional example, and FIG. 13 is an explanatory diagram showing a memory map according to the second conventional example. 4 Basic ROM, 7 Extended ROM, 10 Address latch, 11 Decoder, 12 Mapper, 13 Mapper control register, 14 Extended ROM bank register, 15 Buffer, 16 ... CPU, 17 ... main memory, 18 ... control bus, 19 ... address bus, 20 ... data bus.

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-1-114950 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 12/06

Claims (4)

(57) [Claims] 1. A central processing unit, a basic ROM for storing a basic input / output control program read by the central processing unit and other programs, and a program different from the basic ROM read by the central processing unit. Alternatively, an expansion ROM for storing data, the basic input / output control program is rearranged in a system ROM area, the other program is rearranged in a predetermined adapter ROM area, and further, a program stored in the expansion ROM or An information processing apparatus, comprising: a relocation circuit capable of relocating data to a system ROM extension area. 2. The information processing apparatus according to claim 1, wherein the basic ROM stores two or more of the other programs, and wherein the relocation circuit stores one of the two or more other programs. An information processing apparatus, wherein a program can be selectively rearranged in a predetermined adapter ROM area. 3. The information processing apparatus according to claim 1, wherein the relocation circuit divides a program or data stored in the extension ROM into a plurality of banks for each predetermined capacity. An information processing apparatus, wherein one of the banks can be selectively rearranged in a system ROM extension area. 4. The information processing apparatus according to claim 1, wherein the central processing unit includes a register for instructing the relocation circuit to perform relocation or prohibit relocation. Characteristic information processing device.