JP3449749B2 - Information processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a microprocessor unit.

[0002]

2. Description of the Related Art FIG. 5 shows an M including a ROM and a RAM.
The memory map of PU is shown. When & H is added to the head and a hexadecimal number is written, the address ranges of the internal ROM and internal RAM are & HFF8000 to & HFFFFFF and & H000100 to & H000FFF , respectively.
Programs and constant data are stored in the internal ROM, while the internal RAM is used as a work area for accessing data.

In order to reduce the number of bits of the address designation section in the instruction word and shorten the instruction word length, the entire memory space is
It is divided into banks that are distinguished by the upper 8 bits. The bank address for reading the instruction word in the program is held in the instruction word access bank register R1, and the bank address for data access is the data access bank register R2.
Held in. When accessing the data in the internal RAM, the data access bank register R2 is & H0.
When writing 0 and accessing constant data in the internal ROM, & HFF must be written. Therefore, it is necessary to rewrite the contents of the data access bank register R2 according to the internal RAM and the internal ROM to be accessed, which causes a long program and a long program execution time.

In order to solve this problem, conventionally, in an initialization routine executed immediately after power-on,
All constant data in the internal ROM has been transferred to the internal RAM, and the constant data has been read from the internal RAM.

[0005]

However, extra time is required to transfer the constant data in the internal ROM to the internal RAM, and the available capacity of the internal RAM is reduced. In view of such problems, the object of the present invention is to
Since the constant data stored in the OM is transferred to the RAM in advance, it is possible to eliminate waste of the storage capacity of the RAM.
An object of the present invention is to provide an information processing device that can shorten the program stored in the OM and can shorten the program execution time.

[0006]

An information processing apparatus according to the present invention will be described with reference to the reference numerals of corresponding constituent elements in the embodiments. The present invention is, for example, as shown in FIGS. 1-3, the banks are distinguished by the upper address, the first selector
The first memory (12) selected by the control signal (CS1)
It is assigned to one bank and the second select signal (CS2)
The selected second memory (13) is assigned to the second bank.
Information processing device based on the upper address
When the bank is determined and it is determined that the bank is the first bank
Activates the first select signal to activate the second bank
When it is determined that the first select signal and the second select signal
Bank decode times that activate both select signals
Path (16), the area of the lower address is the first memory
And the second memory is different.
It

With the above structure, the second bank is designated.
If the bank decode circuit (16) determines that
1 select signal CS1 and second select signal CS2
Become active. However, the lower address of the second bank
The memory range is between the first memory (12) and the second memory (13).
Since it is different, the first memory (12) or the second memory (1
Only one of 3) is accessed and no data collision occurs.

The data stored in the second bank is accessed.
When accessing the data, the data is stored in the first memory (12) and the second memory (12).
Even if it is stored in both memory (13),
Can be accessed without modification.

Therefore, avoiding this upper address change
Therefore, the initialization routine that is executed immediately after the power is turned on
And transfer the data in the first memory to the second memory in advance.
There is no need to keep it, and the second memory of this transfer
It is possible to reduce waste of storage capacity. Also as above
Since it is not necessary to change the upper address to
The stored program can be shorter,
Second, the program execution time can be shortened. In the first aspect of the present invention, as shown in FIG.
The value of the upper address that specifies a bank has the same value for each bit, and the upper address that specifies the second bank
Values are values that each bit is inverted one value of identity, bank decode circuit (16), for example as shown in FIG. 1 (B), AND gate upper address is supplied (21
A) or the output of the NOR gate (22A) determines that the bank is the first bank or the second bank.

In this case, the structure is particularly simple. In the second aspect of the present invention, in the above-mentioned configuration, as shown in FIG. 4, for example, the upper address designates the second bank, and the lower address indicates the area of the second bank allocated to the second memory. An address discrimination circuit (33 to 35) for discriminating that it is outside the lower address range, and an address conversion circuit (32) for translating the lower address into the lower address of the first memory outside the lower address range of the second memory, A selector (31) for selecting the output of the address conversion circuit when the determination is made , and selecting the lower address before the conversion when the determination is not made, and is selected by the selector. The output is used to specify a lower address of the first memory and the second memory.

In the case of this configuration, the first with two banks
The lower addresses in both banks of memory can be different. A third aspect of the present invention is a microprocessor unit in which the information processing apparatus having the above configuration is integrated into a single chip. The effect of the present invention is that the first memory has a relatively small storage capacity.
This is remarkable when applied to a microprocessor unit having a memory and a second memory .

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a schematic configuration of the one-chip MPU 10. The MPU 10 includes a CPU 11, ROM 12, RA
An M13, a peripheral circuit 14, an I / O port 15, a bank decode circuit 16, an address bus 17 and a data bus 18 are provided, and the address bus 1 is provided between the constituent elements 11 to 16.
7 and the data bus 1 is connected between the constituent elements 11 to 15.
8 are connected.

The peripheral circuit 14 includes, for example, a timer, a serial / parallel conversion circuit, a parallel / serial conversion circuit, an A / D converter and the like. Address bus 17 is 2
It has 4 bits, and its memory space is divided into banks represented by the upper 8 bits. Bank for reading command words
The address and the bank address for data access are respectively the instruction word access bank register R in the CPU 11.
1 and the data access bank register R2. The upper 8 bits of the program counter in the CPU 11 are determined by the content of the instruction word access bank register R1, while the upper 8 bits of the data access address are determined by the content of the data access bank register R2 and the lower 16 bits are the instruction word. Determined by the addressing section inside. With such a configuration, an address in a large-capacity memory space can be designated with a short instruction word length.

The bank decoding circuit 16 activates the select signals CS1 to CS4 in accordance with the values of the upper 8 bits A23 to A16 (upper address) of the address,
ROM 12, RAM 13, peripheral circuit 14 and I respectively
One of the / O ports 15 is enabled, and data can be exchanged with the CPU 11 via the data bus 18. In the activated ROM 12 or RAM 13, the storage address is designated by the lower 16 bits of the address.

The ROM 12 has two first and second address ranges for the same storage area. For example, FIG.
As shown in (A), the first address range is & HFF800.
0 to & HFFFFFF, the second address range is & H008
000- & H00FFFF. This second address range is the address range & H00010 of RAM13.
0 && H000FFF, the same bank & H00.

In order to give two address ranges to the same storage area of the ROM 12, the bank decoding circuit 16
As a component thereof, is generally provided with a select signal CS1 & CS2 generating circuit 20 as shown in FIG. 1 (A) to create the select signal CS1. Both the first bank determination circuit 21 and the second bank determination circuit 22 are supplied with the upper 8 bits A23 to A16 of the address, and when the first bank determination circuit 21 determines that this address is the first bank address. Only when it is determined that this address is the second bank address , the second bank determination circuit 22 outputs the high level as the select signal CS2. The outputs of the first bank determination circuit 21 and the second bank determination circuit 22 are supplied to the OR gate 23, and the logical sum of them is output as the select signal CS1.

In the case of FIG. 3A, since the first bank is the bank & HFF and the second bank is the bank & H00, the select signal CS1 & CS2 generating circuit 20 is shown in FIG.
A circuit 20A as shown in (B) can be used. That is, the AND gate 2 is used as the first bank determination circuit 21.
1A and the NOR gate 22A can be used as the second bank determination circuit 22, which simplifies the configuration.

Next, the operation of the first embodiment constructed as described above will be explained. When the content of the data access bank register R2 is & HFF, only CS1 of the select signals CS1 to CS4 becomes high level, and when the content of the data access bank register R2 is & H00, the select signal C
Both S1 and CS2 go high. But ROM
Since the lower 16 bits (lower address) of the addresses of 12 and RAM 13 are different from each other, only one of them can be accessed and data collision does not occur.

The reset signal RST is supplied to the CPU 11 by the reset operation immediately after the power is turned on or thereafter,
The content of the instruction word access bank register R1 is set to & HFF, and the program stored in the ROM 12 is stored in the CPU 11
Executed by. When accessing the RAM 13, the CPU 11 first sets the data access bank register R2.
The content of is & H00. In the case of accessing the constant data stored in the ROM 12, the CPU 11 conventionally needs to set the content of the data access bank register R2 to & HFF as a preprocessing, but in the first embodiment, the first data assigned to the ROM 12 is used. 2 address range & H0080
Since it is possible to access 00 to & H00FFFF, the contents of the data access bank register R2 are set to & H0
There is no need to rewrite as 0.

Therefore, the RAM 1 is obtained by transferring the constant data stored in the ROM 12 to the RAM 13 in advance.
It is possible to eliminate the waste of the storage capacity of 3, and to shorten the program stored in the ROM 12 as compared with the conventional one.
Moreover, the program execution time can be shortened. [Second Embodiment] In the first embodiment, as shown in FIG. 3A, the ROM 12 includes a bank & HFF and a bank & H00.
Although the lower 16 bits of are the same, the lower 16 bits can have different values as shown in FIG.

In this case, the address of the bank & HFF & H
8000 && HFFFF and bank & H00 address &
One ROM in correspondence with H1000 to & H8FFF
12 are assigned. ROM 12 is associated with bank & HFF and bank & H00, and RAM 13 is associated with bank & H
Since it is the same as the first embodiment in that it corresponds to 00, the select signal CS1 & CS2 generation circuit 20A shown in FIG. 1B can be used.

However, the lower address of the ROM 12 & H8
000- & HFFFF and lower address & H1000- &
Since the H8FFF and the H8FFF correspond to each other, the address discrimination / conversion circuit 30 as shown in FIG.
Prepare for 11. For the addresses A23 to A00 output from the CPU 11, the addresses generated by decoding the address part of the instruction word in the CPU 11 are A15 'to
Notated as A00 '. Addresses A15'-A12 'are
It is commonly supplied to one input terminal of the selector 31, the address conversion circuit 32, and the OR gate 33. On the other hand, the upper address A held in the data access bank register R2
23 to A16 are supplied to the NOR gate 34. The output of the address conversion circuit 32 is supplied to the other input end of the selector 31. The outputs of the OR gate 33 and the NOR gate 34 are both supplied to the AND gate 35, and the output thereof is supplied to the control input terminal of the selector 31. Address conversion circuit 3
2 shifts up & H1 to & H9 to & H8 to & HF.

The other points are the same as those of the first embodiment. In the above configuration, when the value of the upper address A23 to A16 is 0 and the value of the address A15 'to A12' is not 0, that is, the lower address is in & H1000 to & HFFFF in the bank & H00 (second bank) (outside the address range of the RAM13). ), The output of the AND gate 35 becomes high level, the output of the address conversion circuit 32 is selected by the selector 31, and the selector 31 selects & H1.
Addresses A15 to A12 obtained by converting the values in & H9 to & H8 to & HF are output. Meanwhile, the bank is & H
00, the select signal C in FIG.
S1 and CS2 go high. Therefore, the RAM 13 and the ROM 12 can be data-accessed without changing the bank & H00.

According to the second embodiment, the lower addresses of both banks of the ROM 12 having two banks can be made different, but the configuration becomes complicated as compared with the first embodiment. In addition, the present invention includes various modifications. For example, in FIG. 2, the second address of the ROM 12
Range, (not shown) connected to an external MPU 10 RAM
The same bank may be used.

[0025]

[0026]

[Brief description of drawings]

FIG. 1 is a select signal C constituting a bank decode circuit.
It is a S1 & CS2 generation circuit diagram.

FIG. 2 is a block diagram showing a schematic configuration of a microprocessor unit.

FIG. 3 is a memory map inside a microprocessor unit.

FIG. 4 is an address discrimination / translation circuit diagram.

FIG. 5 is a memory map of a conventional microprocessor unit.

[Explanation of symbols]

10 MPU 11 CPU 12 ROM 13 RAM 16 bank decode circuit 20, 20A select signal CS1 & CS2 generation circuit 21 First Bank Determination Circuit 22 Second Bank Determination Circuit 30 Address discrimination / conversion circuit 31 selector 32 address conversion circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-63-211447 (JP, A) JP-A-61-168436 (JP, A) JP-A-60-29854 (JP, A) JP-A-63- 75852 (JP, A) JP 57-203154 (JP, A) JP 59-41069 (JP, A) JP 5-233439 (JP, A) JP 1-222453 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 12 / 04,12 / 06 G06F 15/78 G06F 9 / 32,9 / 34

Claims (5)

(57) [Claims] 1.The bank is distinguished by the high-order address, and the first
The first memory (1 selected by the select signal (CS1)
2) is assigned to the first bank, and the second select signal (C
The second memory (13) selected in S2) is in the second bank
In the assigned information processing device, The bank is determined based on the upper address and the first bank is determined.
If it is determined that the first selection signal is
When it is determined to be the second bank, the
Activating both the 1 select signal and the second select signal
A bank decoding circuit (16) for
The memory area is different between the first memory and the second memory.
An information processing device characterized by the above. 2. The first memory is a ROM, the second memory is a RAM, and a register (R1) holding an instruction word access bank address and a register (R2) holding a data access bank address. The information processing apparatus according to claim 1, further comprising: 3. The value of the high-order address designating the first bank has the same value in each bit, and the value of the high-order address designating the second bank inverts the same value in each bit. The bank decode circuit (16) is provided with an AND gate (21A) or a NOR gate (2) to which the higher address is supplied.
The information processing apparatus according to claim 2, wherein the information processing apparatus determines that the bank is the first bank or the second bank based on the output of 2A). 4. The second address according to claim 2 or 3, wherein the upper address designates the second bank, and the lower address is assigned to the second memory.
An address discriminating circuit (33 to 35) for discriminating that it is outside the lower address range indicating a bank area, and converting the lower address into a lower address of the first memory outside the lower address range of the second memory. And an selector (31) for selecting the output of the address conversion circuit when the determination is made and selecting the lower address before the conversion when the determination is not made. And an output selected by the selector is used for designating the lower address of the first memory and the second memory. 5. A microprocessor unit comprising the information processing apparatus according to claim 1 integrated into one chip.