JPH03211641A - Address designation method for memory device - Google Patents

Abstract

PURPOSE:To expand the capacity of a memory without the necessity of changing the design of hardware by using an access operation for plural specified addresses for the designation of the selection of a memory cell connected at the time of access with the other respective memory addresses. CONSTITUTION:A latch circuit 160 is connected to the lower four bits of an address bus 14 and higher 12 bits are decoded. When they are equivalent to 3FF, the latch circuit 160 is caused to fetch data. A decoding circuit 200 decodes a value written in it (four bits in this case) and generates a bank selection signal. The access of an address 3FF0 causes the selection of a bank number '0', and the access of an address 3FF1 does the selection of a bank number '1'. Namely, addresses 3FF0-3FFF being the specified addresses are used for the switching of a memory bank. Thus, the capacity of the memory is increased without changing the design of hardware in a computer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of addressing a memory device, and particularly to a method of addressing a memory device having a configuration in which a plurality of memory cells are mapped to the same memory address.

[Conventional technology]

In recent years, the functionality of electronic computers has increased significantly, and it is often necessary to improve the functionality of basic programs such as the basic attendance system (BIO8) program. Normally, these basic programs are often implemented as ROM (read-only memory) in the computer hardware, and when these basic programs become long to increase functionality, they must be implemented in the computer. It will also be necessary to increase the capacity of the ROM.

However, in actual computer systems, in order to maintain compatibility with previous models in terms of software and hardware, it is not possible to make major changes to the type of CPU used or the bus configuration of devices, so the ROM program Even if the capacity of the computer increases, it is not possible to immediately expand the computer's memory space.

In such a case, the number of memories that can be connected to the bus is often increased by mapping a plurality of ROMs to the same memory address using a method called bank memory. For example, in order to expand the capacity of the ROM 10 connected to the computer bus as shown in Figure 2(a),
As shown in FIG. 2(b), a first ROM 20 as bank O and a second ROM 2 as bank 1 are connected to a computer bus consisting of a data bus 12 and an address bus 14.
2 are provided.

The conventional addressing method for this type of memory device requires a new specific input/output address (FOO in the example shown in Figure 2).
When the latch circuit 16 and decode circuit 18 of O) are installed and specific data is output to that address, that data is decoded by the decoder 18 and a selection signal is output, and the selection signal causes multiple maps mapped to the same address to be output. memory (bank), in the illustrated example the first ROM 20
and the second ROM 22.

[Problem to be solved by the invention]

In order to increase the memory capacity using the conventional memory device addressing method described above, it is necessary to add a latch and decode circuit to the computer bus, and then connect the selection signal from that circuit to the memory. , which required considerable changes to the computer hardware design.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for addressing a memory device that can expand memory capacity without requiring changes to hardware design.

[Means to solve the problem]

The method of the present invention provides an addressing method for a memory device having a configuration in which a plurality of memory cells are mapped to the same memory address. It is characterized in that it is used to specify the selection of memory cells to be connected when accessed using individual memory addresses.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the memory device of the present invention.

This corresponds to the first ROM 20 and second ROM 22 mapped to the same address in the configuration shown in FIG.
Latch circuit 16 and decode circuit 1 for memory selection
8 are grouped together as one memory device 100. However, in FIG. 1, the lucky circuit 200 and the decode circuit 160 are incorporated into the memory device. Therefore, this circuit is not an input/output address, but a part of the memory address included in the memory device 100 (the first address).
In the figure, it is assigned to addresses 3FFO to 3FFF).

The latch circuit 160 is connected not to the data bus 12 but to the lower four bits of the address bus 14.

The upper 12 bits are decoded, and if it corresponds to 3FF, the latch circuit 160 is caused to take in the data.

Decode circuit 200 decodes the value written therein (4 bits in this case) and generates a bank selection signal. In this example, for example, access to address 3FFO causes selection of bank number O, and access to address 3FF1 causes selection of bank number 1.

Such a memory device can first be configured and used as a ROM as shown in FIG. Then, specific addresses 3FFO to 3FFF are used for switching memory banks. Therefore, although the memory space is not completely contiguous, there is no particular problem when using it as a ROM for a fixed program.

FIG. 3 conceptually shows the structure of the program written as contents in this ROM. Originally Figure 3(a)
When replacing a ROM program with contents like this with a bank-type ROM to expand its capacity, the conventional configuration shown in Figure 2(b) requires switching of memory banks as shown in Figure 3(b). An OUT command is required for the input/output board, indicating that an external circuit other than the ROM is required.

On the other hand, the configuration according to the method of the present invention shown in FIG.
RITE command may be used, and the data to be read and written is also arbitrary)
If this is for an address included in the ROM itself, it can be seen that there is no need to change anything externally attached other than the ROM.

That is, if a bank type ROM is made using the method of the present invention,
It can be simply replaced with an old small-capacity ROM, and there is no need to change the computer bus connection. This is a great advantage when designing a new model of computer. In addition, it is possible to easily improve the functionality of a computer already in use by a customer by replacing the ROM, which is also a great advantage. Since the ROM configured according to the present invention can switch banks only with a READ command,
An RO where the WRITE signal is not originally connected.
You can use the M-dedicated socket without any problems.

In addition to the above-mentioned ROM, the memory device of the present invention includes:
It is also possible to configure and use it as a RAM. however,
Since specific addresses are used to specify banks, the memory space is not completely contiguous, and care must be taken when using RAM, which is used for general purposes.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to increase the memory capacity without changing the hardware design of the computer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a memory device of the present invention, and FIG. 2 is a block diagram showing a conventional method for expanding ROM memory capacity, in which (a) is before expansion, (b)
) is a diagram showing the state after expansion, and FIG. 3 is a configuration diagram of the program written in the ROM, where (a) is before the ROM capacity is expanded, (b) is the state when expanded using the conventional method, (C
) is expanded using the method of the present invention. 10... ROM120... first ROM, 22...
・Second ROM, 12...Data bus, 14...Address bus, ie, ieo...Latch circuit, 18.2
00...Decode circuit, 150...Address decode circuit, 00...Memory device.

Claims (1)

[Claims] In an addressing method for a memory device having a configuration in which a plurality of memory cells are mapped to the same memory address, an access operation to a specific plurality of addresses among the memory addresses included in the memory device is performed using other individual memory addresses. 1. A method of addressing a memory device, the method being used to specify selection of a memory cell to be connected when accessed.