JPH08221322A - Device and method for controlling memory - Google Patents

Abstract

PURPOSE: To provide a device and a method for controlling memory capable of easily performing programming. CONSTITUTION: The logical address of a memory space accessible from a central processing unit 16 is supplied to bank control registers CR1, CR2, and its content is constituted so as to be rewritten and reread. A bank switching control means 14, when the central processing unit 16 accesses a window WD1, performs switching to which bank memory BK0-BKF access is performed according to the content of the bank control register CR1, and also, when the central processing unit 16 accesses a window WD2, performs the switching to which bank memory BK0-BKF the access is performed according to the content of the bank control register CR2. The contents of the bank control registers CR1, CR2 are read in a program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device and a memory control method, and more particularly to switching of bank memories.

[0002]

2. Description of the Related Art In a computer game machine or the like, C
In order to expand the memory capacity that PU can access,
Bank memory is used. A bank memory controller is used to switch the bank memories. FIG.
The configuration of the conventional bank memory control device 2 is shown in FIG.

The ROM 4 constitutes a bank memory,
The program is stored. In addition, ROM4 is D0
To D7 8-bit data terminals and A0 to A16
17-bit address terminal.

The data terminals D0 to D7 of the ROM 4 are connected to the CPU (not shown) by the signal lines LND0 to LND7, and the address terminals A0 to A13 are connected to the CPU (not shown) by the signal lines LNA0 to LNA13. Also,
Of the data terminals, D0 to D2 (corresponding to the lower 3 bits of data) are connected to the input end 6a of the latch circuit 6, and the output end 6b of the latch circuit 6 is connected to the upper three address terminals A14 to A16. It is connected.

The storage area of the ROM 4 is, as shown in FIG.
It is composed of eight bank memories BKM0 to BKM7. The eight bank memories BKM0 to BKM7 are configured to be specified corresponding to eight combinations of inputs to the address terminals A14 to A16. Therefore, which bank memory can be accessed by the CPU is determined by the combination of the inputs to the address terminals A14 to A16.

First, when the power is turned on, the content of the latch circuit 6 becomes "000", so that the address terminals A14 to A1.
The input to 6 is "000". Therefore, as shown in FIG. 9, the bank memory BKM7 can be accessed.
That is, of the logical addresses accessible from the CPU, for the window WD given to the ROM 4,
This means that the bank memory BKM7 has been applied.

The CPU proceeds with the processing according to the program contents stored in the bank memory BKM7. At a specific address of the bank memory BKM7, data having a code designating a bank memory to be accessed next is stored in the lower 3 bits. The CPU outputs the data stored at this specific address, and at the same time, outputs the latch signal terminal LOAD of the latch circuit 6 shown in FIG.
Send a latch signal to.

The latch circuit 6 receives this latch signal,
The lower 3 bits of the data being output are fetched and output to the upper 3 address terminals A14 to A16 of the ROM 4.
Therefore, the next accessible bank memory is determined by the contents of the lower 3 bits of the data stored at the specific address described above.

For example, when the lower 3 bits of the data stored at this specific address is "101", the contents of the window WD are subsequently switched and the bank memory BKM2 is accessed, as shown in FIG. It will be possible. In this way, the contents of the window can be switched appropriately. Therefore, even when the range of logical addresses accessible by the CPU is small, it is possible to access a ROM having a physical address exceeding the range of logical addresses.

[0010]

However, the conventional bank memory control device 2 has the following problems. In the conventional bank memory control device 2, the latch circuit 6 is used for switching the bank memories. Therefore, it was not possible to know on a program what the bank memory that is currently accessible is.

Therefore, the programmer must always know which bank memory is currently accessible when creating a program. Therefore, in a complicated program having many jumps, for example, when the jump destination must be determined by the currently accessible bank memory, the programmer traces the program in the backward direction and It was necessary to know which bank memory was accessible.

Therefore, it is difficult to create a program, and errors in the program are likely to occur. Especially when checking, modifying, changing or adding the program contents,
There was a disadvantage that it was easy to make an error.

The present invention solves the problems of the conventional memory control device such as the bank memory control device and the conventional memory control method, and facilitates programming. The purpose is to provide a method.

[0014]

According to another aspect of the present invention, there is provided a memory control device, wherein a logical address of a memory space accessible from a central processing unit is given, and the contents are rewritable and readable. When accessing the window from the control register or central processing unit,
A bank switching control means for switching which bank memory to access according to the contents of the bank control register is provided.

According to another aspect of the present invention, there is provided a memory control device.
In the control device of the memory of,
A feature is that a bank control register corresponding to each window portion is provided.

According to another aspect of the memory control method of the present invention, the contents of the bank control register to which the logical address of the memory space accessible from the central processing unit is given are rewritable and readable. When the window part is accessed, which bank memory is accessed is switched according to the contents of the bank control register.

[0017]

According to another aspect of the present invention, there is provided a memory control device and a memory control method according to claim 3, wherein the contents of a bank control register given a logical address of a memory space accessible from the central processing unit are rewritable and readable. If it is possible to access the window from the central processing unit,
It is characterized in that which bank memory is accessed is switched.

Therefore, the contents of the bank control register can be programmed to be read. Therefore, it is possible to easily know which bank memory is currently being accessed.

According to another aspect of the present invention, there is provided a memory control device.
In the control device of the memory of,
A feature is that a bank control register corresponding to each window portion is provided.

Therefore, it is possible to program the contents of the bank control register corresponding to each window to be read. Therefore, it is possible to easily know which bank memory is currently being accessed for each window.

[0021]

1 shows the structure of a bank memory controller 12 which is a memory controller according to an embodiment of the present invention. The bank memory control device 12 has two bank control registers CR1 and CR2 and a bank switching control means 14.

Bank control registers CR1 and CR
2 is given a logical address of a memory space accessible from the central processing unit 16, and its contents are rewritable and readable. The bank control registers CR1 and CR2 correspond to the windows WD1 and WD2, respectively.

When the window WD1 is accessed from the central processing unit 16, the bank switching control means 14 switches which bank memory BK0 to BKF is to be accessed according to the contents of the bank control register CR1 and the central processing unit 16 controls the bank memory. When the window WD2 is accessed, which bank memory BK0 to BKF is to be accessed is switched according to the contents of the bank control register CR2.

FIG. 2 shows the bank memory controller 12 described above.
2 shows a hardware configuration in the case where is realized by using a CPU. The main memory 22 is a writable storage element (RAM)
It is composed of The storage unit 24 includes 16 bank memories BK configured by read-only storage elements (ROM).
It has 0 to BKF.

The central processing unit 16 is a window WD.
1, the memory space including WD2 is accessible. That is, the main memory 22, the windows WD1 and WD2 (that is, the bank memories BK0 to BK0).
A logical address accessible from the central processing unit 16 is attached to the bank control registers CR1 and CR2 (part of BKF) (see FIG. 7).

FIG. 3 shows a flow of bank memory processing by the bank memory controller 12. First, the CPU 20
According to the procedure of the initialization process or the description of the program being executed, it is determined whether the bank memory needs to be switched (see step ST2 in FIG. 3).

When it is determined that the bank memory needs to be switched, the CPU 20 determines the bank control register CR.
The bank number of the bank memory to be used next is set in 1 and CR2 (see step ST4 in FIG. 3). in this case,
The bank number of the bank memory is set in either or both of the bank control registers CR1 and CR2 according to the bank memory requiring switching.

FIG. 4 shows the specifications of the bank control registers CR1 and CR2 used in this embodiment. The bank control registers CR1 and CR2 are both rewritable and readable.

The bank control register CR1 contains
Logical address "2FF00" accessible by the CPU 20
0 "H (H represents a hexadecimal number) is given.
The window WD is stored in the bank control register CR1.
For 1, the bank number of the bank memory to be used next is set. Similarly, the bank control register CR
The logical address "2FF002" H is given to 2, and the bank number of the bank memory to be used next is set for the window WD2 (see FIG. 7).

FIG. 5 shows the correspondence between the bank numbers of the bank memories BK0 to BKF and the physical addresses of the ROM. Bank numbers “00” H are stored in the bank memories BK0 to BKF.
~ "0F" H is attached. In this embodiment, it is configured to have a maximum of 16 bank memories.

Therefore, the CPU 20 can access accessible logical addresses "2FF000" H, "2FF002".
By writing "00" H to "0F" H in H, the bank number of the bank memory to be used next is set.

Bank numbers "00" H to "07" H
Is the physical address "0" of the mask ROM of 32 Mbits.
0000000 "H to" 1FFFFF "H correspond to the bank numbers" 08 "H to" 0F "H.
Physical address of 2M bit mask ROM "00000
0 "H to" 1FFFFF "H correspond, that is, the maximum mounted ROM capacity is set to 64M bits (32M bits X2) in this embodiment.

Further, as shown in FIG.
In the case of 2M bits (16M bits X2), the bank registers BK8 to BKF are inaccessible, so the bank numbers set in the bank control registers CR1 and CR2 are limited to "00" H to "07" H. It

Bank control registers CR1 and CR
When the bank number of the bank memory to be used next is set to 2, the CPU 20 next switches the bank memory according to the contents of the set bank control registers CR1 and CR2 (see step ST6 in FIG. 3). This step ST6 corresponds to the bank switching means 14 of FIG.

For example, the bank control register C
The bank numbers set in R1 and CR2 are "
In case of “00” H and “01” H, as shown in FIG.
Bank memories BK0 and BK1 are applied to the windows WD1 and WD2, respectively. This allows the CPU
From 20, the bank memories BK0 and BK1 can be accessed. In this case, the contents of the bank control registers CR1 and CR2 may be the same. In this case, the same bank memory is applied to the windows WD1 and WD2.

Further, as shown in FIG. 7, in this embodiment, the windows WD1 and WD2 respectively have CPs.
Logical address "200000" accessible by U20
H ~ "27FFFF" H, "2800000" H ~ "2F
EFFF ”is given. Therefore, the window W
D2 is smaller than window WD1 by "1000" H. This is because of the above-mentioned bank control registers CR1 and CR2 due to the hardware limitation.
The logical address accessible by 20 is "1000" H
This is because the amount must be secured. In this embodiment, the logical address (see FIG. 7) is assigned to each byte of the storage element, and the physical address (see FIGS. 5 and 6).
Is attached to every 2 bytes (1 word) of the storage element.

Next, the CPU 20 executes the contents of the program written in the bank memory switched in step ST6 (see step ST8 in FIG. 3). When it is determined in step ST2 that the bank memory does not need to be switched, the CPU 20 does not switch the bank memory and the contents of the program currently stored in the bank memory currently applied to the windows WD1 and WD2 are stored. Continue execution.

During execution of the program, the CPU 20 determines whether or not it is necessary to refer to the bank numbers (“00” H and “01” H in the above example) of the bank memory that is currently accessible. (FIG. 3, step ST1
0).

When it is determined that the reference is necessary, the CPU
20 refers to the contents of one or both of the bank control registers CR1 and CR2 according to the program (see step ST12 in FIG. 3) and executes the program based on the referred bank number. On the other hand, CPU2
0 determines that it is not necessary to refer to the bank number,
The control is returned to step S2, and the same processing is repeated thereafter.

In this way, the CPU 20 can access accessible logical addresses "2FF000" H, "2FF00".
By reading the contents stored in 2 "H, the bank number of the currently accessible bank memory can be known on the program at any time.

In this embodiment, the maximum mounting R
Although the OM capacity is set to 64 Mbits, the maximum mounted ROM capacity is not limited to this. Further, the number of bank memories may be other than 8, 16. In addition, the wind department,
Not limited to two. It may be 1 or 3 or more. The number of bank control registers can be provided correspondingly.

Further, in the above embodiment, the CPU 2
The case where the hardware configuration is realized by using 0 has been described as an example, but a part or the whole of the hardware configuration can be realized by the hardware logic.

[0043]

According to the memory control device of the first aspect and the memory control method of the third aspect, the contents of the bank control register to which the logical address of the memory space accessible from the central processing unit is given can be rewritten. In addition, when the window is accessed from the central processing unit, which bank memory is accessed is switched according to the contents of the bank control register.

Therefore, it can be programmed to read the contents of the bank control register. Therefore, it is possible to easily know which bank memory is currently being accessed. That is, even a program having a complicated structure can be easily programmed.

According to a second aspect of the present invention, there is provided a memory control device according to the first aspect.
In the control device of the memory of,
A feature is that a bank control register corresponding to each window portion is provided.

Therefore, it can be programmed to read the contents of the bank control register corresponding to each window. Therefore, it is possible to easily know which bank memory is currently being accessed for each window. That is, programming can be easily performed even in a program having a more complicated structure.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a bank memory control device according to an embodiment of the present invention.

FIG. 2 is a drawing showing a hardware configuration when a bank memory control device according to an embodiment of the present invention is implemented using a CPU.

FIG. 3 is a drawing showing the flow of bank memory control processing by the bank memory control device according to one embodiment of the present invention.

FIG. 4 is a diagram showing specifications of a bank control register.

FIG. 5 is a diagram showing correspondence between bank numbers and physical addresses.

FIG. 6 is a diagram showing correspondence between bank numbers and physical addresses.

FIG. 7 is a diagram showing correspondence between windows and bank memories.

FIG. 8 is a diagram showing a configuration of a conventional bank memory control device.

FIG. 9 is a diagram showing a relationship between banks and bank selection data in a conventional bank memory control device.

[Explanation of symbols]

 14 ... Bank switching control means 16 ... Central processing unit CR1 ... Bank control register CR2 ... Bank control register WD1 ...・ ・ ・ Window WD2 ・ ・ ・ Window BK0 to BKF ・ ・ ・ Bank memory

Claims (3)

[Claims] 1. A central processing unit capable of accessing a memory space including a window section, wherein the central processing unit is accessible in a controller of a memory for accessing a plurality of bank memories corresponding to the window section. When the window is accessed from the central control unit, the bank control register that is configured to be rewritable and readable, and the logical address of the memory space is given, which bank memory is stored according to the content of the bank control register. A memory control device comprising: bank switching control means for switching access. 2. The memory control device according to claim 1, wherein a plurality of window sections are provided, and a bank control register corresponding to each window section is provided. 3. The contents of a bank control register given a logical address of a memory space accessible from the central processing unit are configured to be rewritable and readable, and when the window section is accessed from the central processing unit, the bank is A method for controlling a memory, characterized in that which bank memory is to be accessed is switched according to the contents of a control register.