KR20040036477A - Integrated circuit capable of operating data read and data writing simultaneously and method thereof - Google Patents

Abstract

PURPOSE: An integrated circuit capable of performing a data read operation and a data write operation at the same time and its method are provided to increase an operating frequency of a clock signal. CONSTITUTION: According to the integrated circuit(200) where an input port and an output port are separated and a write address(WADD) and a read address(RADD) are inputted during one period of a clock signal, memory blocks(MB1,MB2,MB3,MB4) comprise a plurality of sub memory blocks respectively. Cache memory blocks(CMB1,CMB2,CMB3,CMB4) correspond to the memory blocks. And a tag memory control part(210) reads data stored in the memory blocks or the cache memory blocks or writes data to the memory blocks or the cache memory blocks in response to the write address or the read address.

Description

Integrated circuit capable of operating data read and data writing simultaneously and method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits, and more particularly, to integrated circuits and methods in which data read and write operations can be performed simultaneously in integrated circuits having separate input and output ports.

A general synchronous RAM can transmit only one of read data or write data every one clock period.

Double data rate RAM doubles the data rate by transferring data on the rising and falling edges of the clock. However, in a typical memory device, data input and data output are performed through one pin. In the method using the common I / O port, since the input and output of the data cannot be controlled independently, the input and output frequencies of the data are limited.

However, as bandwidth of a memory device becomes important, products using separate input / output ports (separate I / O) are being manufactured. In other words, the input and output pins are separated so that data input and output can be controlled independently. A memory device with separate input pins and output pins has a read command, a read address, a write command, a write address, and write data within a period of a clock. ) Can be received, increasing the operating frequency.

However, even in a memory device having a separate input / output port, a read command, a read address, a write command, a write address, and write data within one clock period ), Two memory cell accesses must be performed in order for the read and write operations to be performed within one clock period.

That is, since the activation of the word line for reading and writing data has to be performed twice within one period of the clock, the clock frequency is limited by the activation time of the word line.

1 is a timing diagram illustrating an operation of a memory device having separate input / output ports.

The relationship between the address and the word line, or the latency of the input data and the output data depends on the circuit configuration of the memory device and is not considered here in FIG.

Referring to FIG. 1, both the write address WADD and the read address RADD are input within one period of the clock signal CLK. Addresses A0, A2, A4 and A6 input at the rising edge of the clock signal CLK are read addresses RADD and addresses A1, A3, A5 and A7 input at the falling edge of the clock signal CLK. Is the write address WADD.

RES and WES are a read select signal and a write select signal for selecting the read address RADD and the write address WADD, respectively.

The word line AWL0 is activated by the read address RADD A0, and the data Q0 is output in response to the word line AWL0. In addition, when the word line AWL1 is activated in response to the write address WADD A1, the input data D1 is input.

Therefore, the length of one cycle of the clock signal CLK is limited due to the activation of the word line AWL0 for the read operation and the word line AWL1 for the write operation. That is, it is difficult to shorten the cycle of the clock signal CLK since the memory cells having different addresses must be sequentially accessed during one cycle of the clock signal.

An object of the present invention is to provide an integrated circuit capable of increasing an operating frequency of a clock signal by simultaneously performing a read operation and a write operation on a memory cell within one period of the clock signal.

Another object of the present invention is to provide a method of increasing the operating frequency of a clock signal by simultaneously performing a read operation and a write operation on a memory cell within one period of the clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a timing diagram illustrating an operation of a memory device having separate input / output ports.

2 is a block diagram illustrating an integrated circuit according to a first embodiment.

3 is a block diagram illustrating an integrated circuit according to a second embodiment.

4 is a flowchart illustrating a method of simultaneously performing a read operation and a write operation of data according to another exemplary embodiment.

FIG. 5 is a flowchart for describing operation 440 of FIG. 4.

6 is a flowchart for describing operation 445 of FIG. 4.

FIG. 7 is a flowchart for describing operation 455 of FIG. 4.

8 is a timing diagram illustrating the operation of the integrated circuit of the present invention.

In an integrated circuit according to a first embodiment of the present invention for achieving the above technical problem, a plurality of sub-memory blocks in an integrated circuit in which input / output ports are separated and a write address and a read address are input for one period of a clock signal. And memory blocks each having a plurality of memory blocks, cache memory blocks corresponding to the memory blocks, and a tag memory controller.

The tag memory controller reads data stored in the memory blocks and the cache memory blocks or writes the data into the memory blocks and the cache memory blocks in response to the write address or the read address.

In particular, when the write address and the read address are the same, the tag memory controller controls the data read operation and the write operation to be divided into the memory block and the cache memory block to be simultaneously performed.

When the write address and the read address are different, two different sub memory blocks corresponding to the respective write and read addresses are decoded, respectively.

The integrated circuit has a write address decoding pass and a read address decoding pass separated from each other, and the sub memory blocks are connected to the write address decoding pass and the read address decoding pass, respectively.

Memory cells having the same lower address among different sub memory blocks in the memory block correspond to one memory cell of the cache memory block. The size of the cache memory block is equal to or larger than the size of the one sub memory block.

The tag memory controller stores a cache memory address indicating an address of the sub memory block corresponding to the cache memory block and validity determination information for determining whether data stored in the cache memory block is valid.

When the upper address of the write address that selects one of the sub memory blocks and the upper address of the read address are the same as each other, neither the write address nor the read address is the same as the cache memory address. If not, the read operation is performed in the memory block corresponding to the read address, the write operation is performed in the cache memory block, and the read operation and the write operation are simultaneously performed.

When the upper address of the write address selecting the one of the sub memory blocks and the upper address of the read address are the same as each other, when the one of the write address and the read address is identical to the cache memory address The operation corresponding to the address matched with the cache memory address is performed in the cache memory block, and the operation corresponding to the address not matched is performed in the memory block.

If both the write address and the read address match the cache memory address, a read operation is performed in the cache memory block, a write operation is performed in the memory block, and the read operation and the write operation are simultaneously performed.

When the upper address of the write address selecting the one of the sub memory blocks and the upper address of the read address are different from each other, when the one of the write address and the read address matches the cache memory address The operation corresponding to the address matched with the cache memory address is performed in the cache memory block, and the operation corresponding to the address not matched is performed in the memory block.

If both the write address and the read address match the cache memory address, a read operation is performed in the cache memory block and a write operation is performed in the memory block.

If both the write address and the read address do not match the cache memory address, a write operation and a read operation are performed in different sub memory blocks corresponding to the write address and the read address of the selected memory block, and the read operation is performed. The operation and the write operation are performed at the same time.

The data is input or output at a single data rate (SDR) or a double data rate (DDR).

According to a second embodiment of the present invention for achieving the above technical problem, an integrated circuit may include a memory block, a cache memory block, a decoding unit, and a plurality of sub memory blocks, respectively, in an integrated circuit having separate input and output ports; The tag memory control unit is provided.

The cache memory blocks correspond to the respective memory blocks, and stored data is output or data is written in response to a predetermined cache control signal. The decoding units correspond to the respective memory blocks, and generate decoding signals for controlling the sub memory blocks in response to a write address or a read address and a predetermined decoding control signal.

The tag memory controller receives a write selection signal or a read selection signal, the write address or the read address, and writes and reads the data according to whether the write address and the read address inputted during one period of the clock signal are the same. It generates the cache control signal or the decoding control signal to be performed at the same time.

Each of the decoding units includes a plurality of decoding circuits corresponding to the sub memory blocks. The decoding circuits are connected to the write address decoding path and the read address decoding path which are separated from each other, and the sub memory blocks are connected to the write address decoding path and the read address decoding path, respectively.

In the method for simultaneously performing a data read operation and a write operation according to the first embodiment of the present invention for achieving the other technical problem, the input and output ports are separated and a write address and a read address are input for one period of the clock signal A method of simultaneously performing a data read operation and a write operation of an integrated circuit including a plurality of memory blocks each having a plurality of sub memory blocks and cache memory blocks corresponding to the memory blocks, the method comprising: (a) a clock; Determining whether both the write address and the read address are input or only one of the write address and the read address is input during one period of the signal; (b) if both the write address and the read address are input, the write address Of the upper address of the read address Determining whether the upper address is the same; (c) if the upper address of the write address and the upper address of the read address are the same, determining whether the write address and the read address are equal to a predetermined cache memory address; and d) if neither the write address nor the read address is the same as the cache memory address, performing a read operation on the memory block corresponding to the read address and performing a write operation on the cache memory block do.

In step (d), (d1) determining whether the data stored in the cache memory block is valid; (d2) if the data stored in the cache memory block is invalid, the memory block corresponding to the read address Performing a read operation at, and performing a write operation at the cache memory block, (d3) updating information about data written at the cache memory block, (d4) storing at the cache memory block If valid data is valid, performing a read operation on the memory block corresponding to the read address, reading valid data stored in the cache memory, and writing the read valid data into a corresponding memory block; and (d5) the cache memory block. Perform a write operation on the controller and update information about data written to the cache memory block And a step of (update).

The cache memory address indicates an address of the sub memory block corresponding to the cache memory block.

(C) (c1) if one of the write address and the read address matches the cache memory address, performing an operation corresponding to the address matched with the cache memory address in the cache memory block, and executing the cache memory. Performing an operation corresponding to an address that does not match an address in the memory block; and (c2) if both the write address and the read address match the cache memory address, perform a read operation in the cache memory block, Performing a write operation on the memory block, and updating information on data written to the memory block.

In the step (b), if the upper address of the write address and the upper address of the read address are not the same, determining whether the write address and the read address match the cache memory address, (b2) If any one of a write address and the read address matches the cache memory address, an operation corresponding to the address matched with the cache memory address is performed in the cache memory block, and the address matched with the address not matched with the cache memory address. Performing a read operation on the memory block; (b3) when both the write address and the read address match the cache memory address, a read operation is performed on the cache memory block, and a write operation is performed on the memory block. After that, the memory block (B4) if both the write address and the read address do not match the cache memory address, corresponding to the write address and the read address of the selected memory block; Performing a write operation and a read operation in different sub memory blocks.

In the step (a), if only one of the write address and the read address is input, determining whether one of the input write address and the read address matches the cache memory address, inputting (a2) If the written address or read address coincides with the cache memory address, performing an operation corresponding to the write address or read address matched with the cache memory address in the cache memory block; and (a3) inputting the write address. If the address or the read address does not match the cache memory address, performing an operation corresponding to the write address or read address that does not match the cache memory address in the memory block.

The memory cells having the same lower address among different sub memory blocks in the memory block may correspond to one memory cell of the cache memory block.

The cache memory block may have a size equal to or larger than that of the one sub memory block.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating an integrated circuit according to a first embodiment.

Referring to FIG. 2, the integrated circuit 200 may include memory blocks MB1, MB2, MB3, and MB4 and memory blocks MB1 and MB2, each of which includes a plurality of sub memory blocks SMB1, SMB2, and SMB M, respectively. And cache memory blocks CMB1, CMB2, CMB3, and CMB4 corresponding to the MB3 and the MB4, and the tag memory controller 210. In the integrated circuit 200 of FIG. 2, input / output ports are separated, and a write address WADD and a read address RADD are input for one period of a clock signal.

Since the memory blocks MB1, MB2, MB3, and MB4 have the same structure, and the cache memory blocks CMB1, CMB2, CMB3, and CMB4 have the same structure, the memory blocks MB1, MB2, and MB3 have the same structure. Will be described based on the second memory block MB2 and the second cache memory block CMB2.

The write address WADD and the read address RADD are divided into an upper address and a lower address, respectively, and the upper address is an address specifying one of the plurality of sub memory blocks.

The basic principle of the present invention is to reduce the period of the clock signal when the read address and the write address RADD are the same, and the data read operation and the write operation are respectively divided into the memory block and the cache memory block. .

That is, since the write address WADD and the read address RADD are the same, the same sub memory block (for example, SMB2) of one memory block (for example, the second memory block MB2) must be accessed at the same time. In this case, when a data read operation is performed in the sub memory block SMB2, the data write operation is performed in the cache memory block CMB2 corresponding to the sub memory block SMB2.

In contrast, when a data write operation is performed in the memory block MB2, the data read operation is performed in the cache memory block CMB2 corresponding to the memory block MB2. In this manner, data read and write operations can be performed in parallel at the same time and the period of the clock signal can be reduced.

To this end, memory cells having the same lower address among different sub memory blocks SMB1, SMB2, SMB3 to SMB M in the memory block MB2 must correspond to one memory cell of the cache memory block CMB2. . In addition, since a write operation and a read operation may be performed on the same sub memory block, the size of the cache memory block should be equal to or larger than the size of one sub memory block.

This operation is performed by the tag memory controller 210. The tag memory controller 210 stores data stored in the memory blocks MB1, MB2, MB3, and MB4 and the cache memory blocks CMB1, CMB2, CMB3, and CMB4 in response to the write address WADD or the read address RADD. Read or write data into memory blocks MB1, MB2, MB3, and MB4 and cache memory blocks CMB1, CMB2, CMB3, and CMB4.

When the write address WADD and the read address RADD are the same and a read operation is performed in one sub memory block of the memory block MB2 and a write operation is performed in the cache memory block CMB2, the cache memory block ( The address of the sub memory block of the memory block MB2 to which data written in the CMB2 is to be originally written is stored in the tag memory control unit 210 as a cache memory address.

That is, the cache memory address is an upper address that designates a sub memory block in which data stored in the cache memory block CNB2 should be originally stored.

The cache memory address stored in the tag memory controller 210 is accessed using the lower address among the input addresses, and the accessed cache memory address is compared with the upper address of the input address.

When the next write address WADD and the read address RADD are the same, and the previous write address WADD and the read address RADD are the same, there is a case where a write operation must be performed in the cache memory block CMB2 again. have. In this case, it is necessary to determine whether the data previously written to the cache memory block CMB2 is valid data.

If the data is valid, the data first written to the cache memory block CMB2 is read and written to the corresponding sub memory block of the memory block MB2, and then the data corresponding to the next write address WADD is stored in the cache memory block CMB2. This is because it is necessary to write in CMB2). The validity determination information for determining whether the data stored in the cache memory block CMB2 is valid is also stored in the tag memory controller 210.

In addition, when the write address WADD and the read address RADD are different, two different sub memory blocks corresponding to the respective write and read addresses WADD and RADD are decoded, respectively.

To this end, the integrated circuit 200 requires that the write address decoding path (not shown) and the read address decoding path (not shown) are independently separated from each other. Sub-memory blocks SMB1, SMB2, SMB3 to SMB M should be connected to the write address decoding path and the read address decoding path, respectively.

Data is input or output through the input pins and output pins at a single data rate (SDR) or double data rate (DDR).

The operation of the tag memory controller 210 to read and write data by controlling the memory block MB2 and the cache memory block CMB2 will be described later with reference to FIGS. 3 and 4.

3 is a block diagram illustrating an integrated circuit according to a second embodiment.

The integrated circuit 300 includes memory blocks, cache memory blocks, decoders, and a tag memory controller 310, each of which includes a plurality of sub memory blocks SMB1, SMB2, SMB3 to SMB M.

The cache memory blocks correspond to each memory block, and stored data is output or data is written in response to a predetermined cache control signal CCLS. The decoding units correspond to each memory block, and control the sub memory blocks SMB1, SMB2, SMB3 to SMB M in response to a write address WADD or a read address RADD and a predetermined decoding control signal DCLS. To generate a decoded signal DS.

3 illustrates one memory block MB2 of a plurality of memory blocks, one decoding unit 320 of a plurality of decoding units, and one cache memory block CMB2 of a plurality of cache memory blocks.

Therefore, a description of the operation of the integrated circuit 300 according to the second embodiment uses the memory block MB2, the cache memory block CMB2, the decoder 320, and the tag memory controller 310 illustrated in FIG. 3. Explain.

The tag memory controller 310 receives the write select signal WES or the read select signal RES, the write address WADD, or the read address RADD, and writes the input address WADD during one period of the clock signal. The cache control signal CCLS or the decoding control signal DCLS are generated to simultaneously perform the data write operation and the read operation depending on whether the read addresses RADD are the same. Although not shown, the read select signal RES and the write select signal WES may also be applied to the memory block MB2 and the cache memory block CMB2.

Like the integrated circuit 200 of FIG. 2, the decoding units include a plurality of decoding circuits (not shown) corresponding to the sub memory blocks SMB1, SMB2, SMB3 to SMB M, respectively. This is because when the input write address WADD and the read address RADD are different from each other, two different sub memory blocks corresponding to the respective write and read addresses WADD and RADD must be decoded, respectively.

To this end, the decoding circuits (not shown) are connected to a write address decoding pass (not shown) and a read address decoding pass (not shown) which are separated from each other, and the sub memory blocks SMB1, SMB2, SMB3 to SMB M. Are coupled to a write address decoding pass (not shown) and a read address decoding pass (not shown), respectively.

4 is a flowchart illustrating a method of simultaneously performing a read operation and a write operation of data according to another exemplary embodiment.

FIG. 5 is a flowchart for describing operation 440 of FIG. 4.

6 is a flowchart for describing operation 445 of FIG. 4.

FIG. 7 is a flowchart for describing operation 455 of FIG. 4.

Hereinafter, an integrated circuit and a method for simultaneously performing a data read operation and a write operation will be described with reference to FIGS. 2 to 7.

First, it is determined whether both the write address and the read address are input or only one of the write address and the read address are input during one period of the clock signal. (Step 410) The write select signal WES and the read select signal RES of FIG. Can be determined by

Here, it will be described that the write address WADD and the read address RADD are input when the write select signal WES is low level or the read select signal RES is low level. Of course, the circuit may be configured such that the write address WADD and the read address RADD are input when the levels of the write select signal WES and the read select signal RES are high.

The tag memory controller 310 receives a write select signal WES and a read select signal RES, and receives a write address WADD and a read address RADD.

When both the write address and the read address are input, it is determined whether the upper address of the write address and the upper address of the read address are the same (step 420).

The write address WADD and the read address RADD have information for specifying the sub memory block in the upper bits. Therefore, when a write address WADD or a read address RADD is input, first, an upper address of the write address WADD or the read address RADD is recognized to determine which sub memory block is designated.

If the upper address of the write address and the upper address of the read address are the same, it is determined whether the write address and the read address are the same as the predetermined cache memory address (step 430).

If the upper address of the write address WADD and the upper address of the read address RADD are the same, a sub memory block having the same write address WADD and read address RADD is designated.

The tag memory controller 310 stores a cache memory address therein. The cache memory address indicates an address of a sub memory block corresponding to the cache memory block CMB2. If the write address WADD is the same as the cache memory address, the write operation should be performed in the cache memory block CMB2.

If neither the write address nor the read address is the same as the cache memory address, a read operation is performed in the memory block corresponding to the read address, and a write operation is performed in the cache memory block (step 440).

Operation 440 will be further described with reference to FIG. 5. If neither the write address nor the read address is the same as the cache memory address, it is determined whether the data stored in the cache memory block is valid (step 510).

If neither the write address WADD nor the read address RADD is the same as the cache memory address, it means that a write operation and a read operation must be performed in the same sub memory block of the memory block MB2. However, write word lines and read word lines cannot be enabled at the same time in the same sub memory block. Therefore, the cache memory block CMB2 is used.

If the data stored in the cache memory block is invalid, a read operation is performed in the memory block corresponding to the read address, and a write operation is performed in the cache memory block (step 540).

When the write operation and the read operation are to be performed in the same sub memory block, the read operation is performed first. Therefore, a read operation is performed in the sub memory block of the memory block MB2 corresponding to the read address RADD. Since the data stored in the cache memory block CMB2 is not valid, a write operation is performed in the cache memory block CMB2.

The tag memory controller 310 applies the decoding control signal 310 to the decoder 320. Then, the decoding circuit corresponding to the read address RADD among the decoding circuits (not shown) in the decoding unit 320 generates the decoding signal DS to decode the corresponding sub memory block. The data stored in the sub memory block is then output. In FIG. 3, MDOUT is a path through which data stored in the memory block MB2 is output. Q means output pin. The output pin Q and the input pin D are separated.

In addition, the tag memory controller 310 generates a cache control signal CCLS to perform a write operation in the cache memory block MB2.

Since the data stored in the cache memory block CMB2 has been changed, information about the data written in the cache memory block is updated (step 550). The update of the information is performed by the tag memory controller 310.

If the data stored in the cache memory block is valid, a read operation is performed in the memory block corresponding to the read address, and valid data stored in the cache memory block is read and written in the corresponding memory block. 520 steps)

When the write operation and the read operation are to be performed in the same sub memory block, the read operation is performed first, and therefore, the read operation is performed in the sub memory block of the memory block MB2 corresponding to the read address RADD. The decoding control signal DCLS is generated by the tag memory controller 310.

Since the data stored in the cache memory block CMB2 is valid data, first, valid data stored in the cache memory block CMB2 must be read, and the read data must be written in the corresponding sub memory block of the memory block. In response to the cache control signal CCLS, a write operation is performed in the cache memory block CMB2, and information about data written in the cache memory block CMB2 is updated (step 530). The update is also performed in the tag memory controller 310.

Such a data write operation and a read operation are simultaneously performed. That is, since the write operation and the read operation are performed independently in the sub memory block and the cache memory block CMB2, the write word line and the read word line may be enabled at the same time. Therefore, the write word line and the read word line are sequentially enabled, thereby limiting the problem of reducing the period of the clock signal.

A write operation and a read operation are performed by determining whether one of the write address and the read address matches the cache memory address, and whether both the write address and the read address match the cache memory address (step 445).

A step 445 is further described with reference to FIG. If one of the write address and the read address matches the cache memory address, an operation corresponding to the address matched with the cache memory address is performed in the cache memory block, and the address corresponds to an address not matched with the cache memory address. The operation is performed in the memory block (step 610).

That is, if the read address RADD matches the cache memory address and the write address WADD does not match the cache memory address, the read operation is performed in the cache memory block CMB2. The tag memory controller 310 applies a cache control signal CCLS to the cache memory block CMB2 to perform a read operation. The read data is indicated as CDOUT in FIG.

In addition, the tag memory controller 310 generates a decoding control signal DCLS to perform a write operation in the memory block MB2.

On the contrary, if the write address WADD matches the cache memory address and the read address RADD does not match the cache memory address, the write operation is performed in the cache memory block CMB2 and the read operation in the memory block MB2. Do this.

If both the write address and the read address match the cache memory address, a read operation is performed in the cache memory block, a write operation is performed in the memory block, and information about data written in the memory block is updated. (update) (step 620).

If both the write address and the read address match the cache memory address, it means that both the write operation and the read operation must be performed in the cache memory block CMB2. However, this is not possible for the same reason that a write operation and a read operation cannot be performed simultaneously in the same sub memory block.

Therefore, the read operation is performed in response to the cache control signal CCLS in the cache memory block CMB2. The write operation is performed in the corresponding sub memory block of the memory block MB2 in response to the decoding control signal DCLS. Since data originally to be written to the cache memory block CMB2 is written to the sub memory block, the data currently stored in the cache memory block CMB2 becomes invalid data. Therefore, the tag memory controller 310 updates this information.

In step 420, if the upper address of the write address and the upper address of the read address are not the same, it is determined whether the write address and the read address match the cache memory address (step 450).

A write operation and a read operation are performed by determining whether one of the write address and the read address matches the cache memory address, and whether both the write address and the read address match the cache memory address (step 455).

A step 455 is further described with reference to FIG. If any one of the write address and the read address matches the cache memory address, an operation corresponding to the address matched with the cache memory address is performed in the cache memory block, and an address that does not match the cache memory address may be used. A matching operation is performed in the memory block (step 710).

That is, if the read address RADD matches the cache memory address and the write address WADD does not match the cache memory address, the read operation is performed in the cache memory block CMB2 in response to the cache control signal CCLS. . In addition, the tag memory controller 310 generates a decoding control signal DCLS to perform a write operation in the memory block MB2.

On the contrary, if the write address WADD matches the cache memory address and the read address RADD does not match the cache memory address, the write operation is performed in the cache memory block CMB2 and the read operation in the memory block MB2. Do this.

If both the write address and the read address match the cache memory address, a read operation is performed in the cache memory block, a write operation is performed in the memory block, and information about data written in the memory block is updated. (update) (step 720).

If both the write address and the read address match the cache memory address, it means that both the write operation and the read operation must be performed in the cache memory block CMB2. However, this is not possible for the same reason that a write operation and a read operation cannot be performed simultaneously in the same sub memory block.

Therefore, the read operation is performed in response to the cache control signal CCLS in the cache memory block CMB2. The write operation is performed in the corresponding sub memory block of the memory block MB2 in response to the decoding control signal DCLS. Since data originally to be written to the cache memory block CMB2 is written to the sub memory block, the data currently stored in the cache memory block CMB2 becomes invalid data. Therefore, the tag memory controller 310 updates this information.

In operation 450, if both the write address and the read address do not match the cache memory address, a write operation and a read operation are performed in different sub memory blocks corresponding to the write address and the read address among the selected memory blocks. Perform the operation (step 460).

In this case, a sub memory block in which the write address WADD and the read address RADD are different from each other is designated. Since different sub memory blocks are designated, data read and write operations are performed using a decoding circuit (not shown) corresponding to each sub memory block.

A decoding circuit capable of decoding each sub memory block is provided separately, and since the write address decoding path and the read address decoding path are independently separated, the read operation and the write operation are simultaneously performed for different sub memory blocks even with the same memory block. Can be performed.

In operation 410, when only one of the write address and the read address is input, it is determined whether any one of the input write address and the read address matches the cache memory address.

If the input write address or read address matches the cache memory address, an operation corresponding to the write address or read address matched with the cache memory address is performed in the cache memory block (step 470). Only one of the write address WADD and the read address RADD is input during one period of the clock signal.

In this case, if the input address matches the cache memory address, the corresponding operation is performed in the cache memory block. If the address does not match, the corresponding operation is performed in the memory block MB2.

That is, if only the write address WADD is input and the input write address WADD matches the cache memory address, the write operation is performed to the cache memory block CMB2. On the contrary, if only the read address RADD is input and the input read address RADD matches the cache memory address, a read operation is performed to the cache memory block CMB2. In this case, the tag memory controller 310 may generate a cache control signal CCLS to perform a write or read operation in the cache memory block CMB2.

If the input write address or read address does not match the cache memory address, an operation corresponding to a write address or read address that does not match the cache memory address is performed in the memory block (step 475).

8 is a timing diagram illustrating the operation of the integrated circuit of the present invention.

Referring to FIG. 8, it can be seen that one cycle of the clock signal CLK is reduced to half of one cycle of the clock signal CLK of FIG. 1. That is, the frequency of the clock signal CLK is doubled.

Conventionally, since the word line for the write operation and the word line for the read operation are enabled sequentially during one period of the clock signal CLK, it is difficult to shorten the period of the clock signal CLK.

However, according to the integrated circuit and method according to the present invention, as can be seen in FIG. 8, the word line WL1 for the read operation and the word line WL2 for the write operation are simultaneously operated during one period of the clock signal CLK. Since it is enabled, the period of the clock signal CLK can be shortened.

The present invention can be applied to an integrated circuit in which an input / output port is separated and can receive both a write address and a read address within one period of a clock signal. In addition, data may be input or output through an input pin or an output pin separated by a single data rate (SDR) or a double data rate (DDR).

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the integrated circuit and the method of simultaneously performing the read operation and the write operation according to the present invention include a decoding circuit capable of dividing a memory block into a plurality of sub memory blocks and decoding each sub memory block; A write address decoding path and a read address decoding path connected to all the sub memory blocks are separately provided, and the cache memory block includes read and write operations divided between the memory block and the cache memory block within one period of the clock signal. The simultaneous operation has the advantage of increasing the operating frequency of the clock signal.

Claims (30)

In an integrated circuit in which input / output ports are separated and a write address and a read address are input for one period of a clock signal, Memory blocks each having a plurality of sub memory blocks; Cache memory blocks corresponding to the memory blocks; And And a tag memory controller configured to read data stored in the memory blocks and the cache memory blocks or to write the data to the memory blocks and the cache memory blocks in response to the write address or the read address. The tag memory control unit, And when the write address and the upper address of the read address are the same, the read operation and the write operation of the data are divided into the memory block and the cache memory block, respectively, so as to be controlled at the same time. The method of claim 1, And when the write address and the read address are different, two different sub memory blocks corresponding to the respective write and read addresses are decoded, respectively. The method of claim 1, wherein the integrated circuit, A write address decoding path and a read address decoding path separated from each other, The sub memory blocks And are coupled to the write address decoding path and the read address decoding path, respectively. The method of claim 1, And memory cells having the same lower address among different sub memory blocks in the memory block correspond to one memory cell of the cache memory block. The method of claim 1, wherein the size of the cache memory block, And a size equal to or larger than a size of the one sub memory block. The method of claim 1, wherein the tag memory control unit, And a cache memory address indicating an address of the sub memory block corresponding to the cache memory block and valid determination information for determining whether data stored in the cache memory block is valid. The method of claim 6, wherein the tag memory control unit, When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are the same, If neither the write address nor the read address is the same as the cache memory address, a read operation is performed in the memory block corresponding to the read address, and a write operation is performed in the cache memory block. And said read operation and said write operation are performed simultaneously. The method of claim 6, wherein the tag memory control unit, When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are the same, If one of the write address and the read address matches the cache memory address, An operation corresponding to an address matched with the cache memory address is performed in the cache memory block, and an operation corresponding to an unmatched address is performed in the memory block, If both the write address and the read address match the cache memory address, A read operation is performed in the cache memory block and a write operation is performed in the memory block, And said read operation and said write operation are performed simultaneously. The method of claim 6, wherein the tag memory control unit, When an upper address of the write address and one of the read addresses that select one of the sub memory blocks are different from each other, If one of the write address and the read address matches the cache memory address, An operation corresponding to an address matched with the cache memory address is performed in the cache memory block, and an operation corresponding to an unmatched address is performed in the memory block, If both the write address and the read address match the cache memory address, A read operation is performed in the cache memory block and a write operation is performed in the memory block, If both the write address and the read address do not match the cache memory address, A write operation and a read operation are performed in different sub memory blocks corresponding to the write address and the read address among the selected memory blocks. And said read operation and said write operation are performed simultaneously. The method of claim 1, wherein the data, An integrated circuit, characterized in that input or output at a single data rate (SDR) or a double data rate (DDR). In an integrated circuit in which input and output ports are separated, Memory blocks each having a plurality of sub memory blocks; A plurality of cache memory blocks corresponding to the respective memory blocks, in which stored data is output or data is written in response to a predetermined cache control signal; A plurality of decoding units corresponding to each of the memory blocks and generating a decoding signal for controlling the sub memory blocks in response to a write address or a read address and a predetermined decoding control signal; Receive a write select signal or a read select signal, the write address or the read address, and perform the write operation and the read operation of the data at the same time depending on whether the write address and the read address inputted during one period of the clock signal are the same. And a tag memory controller configured to generate the cache control signal or the decoding control signal. The method of claim 11, wherein the decoding unit, And a plurality of decoding circuits corresponding to the sub memory blocks. The method of claim 12, wherein the decoding circuits, Connected to a write address decoding path and a read address decoding path that are separated from each other, The sub memory blocks, And are coupled to the write address decoding path and the read address decoding path, respectively. The method of claim 11, And when the write address and the read address are different, two different sub memory blocks corresponding to the respective write and read addresses are decoded, respectively. The method of claim 11, And memory cells having the same lower address among different sub memory blocks in the memory block correspond to one memory cell of the cache memory block. The method of claim 11, wherein the size of the cache memory block, And a size equal to or larger than a size of the one sub memory block. The method of claim 11, wherein the tag memory control unit, And a cache memory address indicating an address of the sub memory block corresponding to the cache memory block and valid determination information for determining whether data stored in the cache memory block is valid. The method of claim 17, wherein the tag memory control unit, When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are the same, If neither the write address nor the read address is the same as the cache memory address, the decoding control signal is generated to perform a read operation in the memory block corresponding to the read address, and the cache control signal is generated to generate the cache. Perform a write operation on the memory block, And said read operation and said write operation are performed simultaneously. The method of claim 17, wherein the tag memory control unit, When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are the same, If one of the write address and the read address matches the cache memory address, Generating an cache control signal to perform an operation corresponding to an address matched with the cache memory address in the cache memory block; and generating an decoding control signal to perform an operation corresponding to an address not matched with the cache memory address Perform in memory blocks, If both the write address and the read address match the cache memory address, Generating the cache control signal to perform a read operation on the cache memory block, generating the decoding control signal to perform a write operation on the memory block, And said read operation and said write operation are performed simultaneously. The method of claim 17, wherein the tag memory control unit, When an upper address of the write address and one of the read addresses that select one of the sub memory blocks are different from each other, If one of the write address and the read address matches the cache memory address, Generating an cache control signal to perform an operation corresponding to an address matched with the cache memory address in the cache memory block; and generating an decoding control signal to perform an operation corresponding to an address not matched with the cache memory address Perform in memory blocks, If both the write address and the read address match the cache memory address, Generating the cache control signal to perform a read operation on the cache memory block, generating the decoding control signal to perform a write operation on the memory block, If both the write address and the read address do not match the cache memory address, Generating the decoding control signal to perform a write operation and a read operation in different sub memory blocks corresponding to the write address and the read address of the selected memory block; And said read operation and said write operation are performed simultaneously. The method of claim 11, wherein the data, An integrated circuit, characterized in that input or output at a single data rate (SDR) or a double data rate (DDR). An input / output port is separated, a write address and a read address are input during one period of a clock signal, and a plurality of memory blocks each having a plurality of sub-memory blocks, and an integrated memory having cache memory blocks corresponding to the memory blocks. A method of simultaneously performing a data read operation and a write operation of a circuit, (a) determining whether both the write address and the read address are input or only one of the write address and the read address is input during one period of the clock signal; determining whether the upper address of the write address and the upper address of the read address are the same when both the write address and the read address are input; (c) if the upper address of the write address and the upper address of the read address are the same, determining whether the write address and the read address are equal to a predetermined cache memory address; And (d) if neither the write address nor the read address is the same as the cache memory address, performing a read operation on the memory block corresponding to the read address, and performing a write operation on the cache memory block. And reading and writing data simultaneously. The method of claim 22, wherein step (d) (d1) determining whether data stored in the cache memory block is valid; (d2) performing a read operation on the memory block corresponding to the read address and performing a write operation on the cache memory block if data stored in the cache memory block is invalid; (d3) updating information on data written in the cache memory block; (d4) If data stored in the cache memory block is valid, a read operation is performed in the memory block corresponding to the read address, and valid data stored in the cache memory block is read and written to the corresponding memory block. Doing; And (d5) performing a read operation on the cache memory block, and updating information on data written on the cache memory block. Way. The method of claim 22, wherein the cache memory address, And displaying the address of the sub memory block corresponding to the cache memory block. The method of claim 22, wherein (c) is (c1) if one of the write address and the read address matches the cache memory address, an operation corresponding to the address matched with the cache memory address is performed in the cache memory block, and the cache address does not match the cache memory address. Performing an operation corresponding to an address in the memory block; And (c2) if both the write address and the read address coincide with the cache memory address, a read operation is performed in the cache memory block, a write operation is performed in the memory block, and the data is written into the memory block. And updating the information, wherein the reading and writing operations of the data are performed simultaneously. The method of claim 22, wherein step (b) (b1) determining whether the write address and the read address match the cache memory address if the upper address of the write address and the upper address of the read address are not the same; (b2) if any one of the write address and the read address matches the cache memory address, an operation corresponding to the address matched with the cache memory address is performed in the cache memory block and does not match the cache memory address. Performing an operation corresponding to an unaddressed address in the memory block; (b3) If both the write address and the read address match the cache memory address, a read operation is performed in the cache memory block, a write operation is performed in the memory block, and then the data written to the memory block is written. Updating the relevant information; And (b4) if both the write address and the read address do not match the cache memory address, a write operation and a read operation are performed in different sub memory blocks corresponding to the write address and the read address among the selected memory blocks; And performing a read operation and a write operation of data at the same time. The method of claim 22, wherein the step (a), determining whether any one of the input write address and the read address coincides with the cache memory address when only one of the write address and the read address is input; (a2) if the input write address or the read address matches the cache memory address, performing an operation corresponding to the write address or read address matched with the cache memory address in the cache memory block; And (a3) if the input write address or read address does not match the cache memory address, performing an operation corresponding to the write address or read address that does not match the cache memory address in the memory block; And simultaneously reading and writing data. The method of claim 22, And memory cells having the same lower address among different sub memory blocks in the memory block correspond to one memory cell of the cache memory block. The method of claim 22, wherein the size of the cache memory block, And simultaneously reading and writing data, wherein the size of the one sub memory block is equal to or larger than the size of the one sub memory block. The method of claim 22, wherein the data, A method of simultaneously performing a read operation and a write operation of data, wherein the data is input or output at a single data rate (SDR) or a double data rate (DDR).