KR970022776A

KR970022776A - Memory access device and method

Info

Publication number: KR970022776A
Application number: KR1019950035342A
Authority: KR
Inventors: 치 융 우; 쳉 유 쿠오
Original assignee: 존슨 인; 홀테크 마이크로일렉트로닉스 인코포레이티드
Priority date: 1995-10-13
Filing date: 1995-10-13
Publication date: 1997-05-30

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

메모리 억세스의 인터페이스회로 및 메모리 억세스 방법에 관한 것이다.The present invention relates to an interface circuit for memory access and a memory access method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

효과적으로 메모리 데이터의 억세스 속도를 향상시키는 메모리 억세스의 인터페이스회로 및 메모리 억세스의 방법을 제공한다.An interface circuit of memory access and a method of memory access that effectively improve the access speed of memory data are provided.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

각 어드레스가 각각 1데이타에 대응하는 복수의 어드레스를 구비한 디코드 메모리소자의 데이터를 독출하는 인터페이스회로에 있어서, 외부 시스템으로부터 몇회에 나누어 직렬적으로 입력된 상기 디코드 메모리소자의 1어드레스 신호를 기억하고, 동일 시간에 상기 어드레스신호를 상기 디코드 메모리소자에 출력하는 어드레스회로와, 상기 어드레스신호와 대응되는 상기 디코드 메모리소자의 데이터를 일시 기억하는 데이터출력 완충회로와, 상기 어드레스 기억회로와 상기 데이터 출력 완충회로에 전기적으로 접속되어 상기 어드레스 기억회로를 동일 시점에 수신 가능한 비트수로, 그리고 상기 데이터 출력 완충회로를 동일 시점에 출력 가능한 비트수로 설정하는 비트선택회로와, 상기 어드레스 기억회로와 상기 데이터출력 완충회로에 전기적으로 접속되어 상기 어드레스 기억회로 및 상기 데이터출력 완충회로에 요구되는 인에이블신호와, 상기 디코드 메모리소자에 요구되는 서입신호를 제공하는 제어회로를 구비한다.An interface circuit which reads data of a decode memory device having a plurality of addresses each address corresponding to one data, and stores one address signal of the decode memory device input in series several times from an external system An address circuit for outputting the address signal to the decode memory element at the same time, a data output buffer circuit for temporarily storing data of the decode memory element corresponding to the address signal, the address memory circuit and the data output A bit selection circuit electrically connected to a buffer circuit for setting the address memory circuit to the number of bits that can be received at the same time and the data output buffer circuit to the number of bits that can be output at the same time; and the address memory circuit and the data. Electrical to output buffer circuit It is connected in a control circuit for providing the enable signal required for the address memory circuit and the data output buffer circuit, seoip signals required to decode the memory element.

4. 발명의 중요한 용도4. Important uses of the invention

실제로 필요한 독출속도의 요구에 따라서, 인터페이스회로의 필요핀의 수를 조정할 수 있는 메모리 억세스의 인터페이스회로를 제공한다.According to the demand of the read speed actually required, an interface circuit for memory access that can adjust the number of required pins of the interface circuit is provided.

Description

Memory access device and method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 관련된 메모리 독출인터페이스회로의 바람직한 실시예의 블럭구성도.1 is a block diagram of a preferred embodiment of a memory read interface circuit according to the present invention.

Claims

An interface circuit which reads data of a decode memory element having a plurality of addresses each address corresponding to one data, and stores one address signal of the decode memory element input in series several times from an external system An address memory circuit for outputting the address signal to the decode memory element at the same time, a data output buffer circuit for temporarily storing data of the decode memory element corresponding to the address signal, the address memory circuit and the data A bit selection circuit electrically connected to an output buffer circuit for setting the address memory circuit to the number of bits receivable at the same time and the data output buffer circuit to the number of bits output at the same time, and the address memory circuit and the Electrical to data output buffer circuit And a control circuit connected to each other to provide an enable signal required for the address memory circuit and the data output buffer circuit, and a write signal required for the decode memory device.

2. An address counter according to claim 1, wherein an address counter electrically connected to said decode memory element, said control circuit, and said decode memory element, which is a read-only memory device, stores said address signal, said set selection circuit, said address counter, and said Electrically connected to a control circuit, generating a plurality of address indicator signals based on the number of bits set in the bit selection circuit, and providing the address indicator signals each time an address signal of the decode memory element is input from an external system. And said address memory circuit comprising an address indicator having said address counter as an address indicator for storing said address.

3. The data output buffer circuit according to claim 2, wherein said data output buffer circuit is electrically connected to said control circuit and said decode memory element to temporarily store data corresponding to said address signal output by said decode memory element, and said decode memory element. A one-way data buffer which serially outputs data corresponding to the address of the circuit several times, and is electrically connected to the bit selection circuit, the data buffer and the control circuit, and is plural in accordance with the number of bits set in the bit selection circuit. Generating a data output indicator of the memory buffer, wherein the data buffer comprises a data indicator for determining each data bit to be output by the data buffer based on the plurality of data output indicators. .

3. The data according to claim 1 or 2, wherein the number of bits of an address when the address memory circuit has received is smaller than the number of bits of an address of each of the decode memory elements and is output by the data output buffer circuit. And the number of bits of is smaller than the number of bits of data corresponding to each address of said decode memory element.

An interface circuit for accessing data of a decode memory element having two states of reading and writing, wherein the address signal of the decode memory element input in series several times from an external system is stored, and the address is stored at the same time. An address memory circuit for outputting a signal to the decode memory element, and data of the decode memory element corresponding to the address signal when the interface circuit is in a read state temporarily; on the contrary, when the interface circuit is in a write state. A data output buffer circuit for temporarily storing data input from an external system, and the number of bits electrically connected to the address memory circuit and the data buffer circuit to receive the address memory circuit at the same time, and the data buffer circuit are the same. At the point A bit selection circuit for setting the number of bits that can be output, an enable signal electrically connected to the address memory circuit and the data output buffer circuit, required for the address memory circuit and the data output buffer circuit, and the decode memory element. And a control circuit for generating a signal for controlling the interface circuit while providing a required read / write signal.

6. An address counter according to claim 5, wherein said decode memory element, which is a direct access decode memory element, an address counter electrically connected to said control circuit and said decode memory element, for storing said address signal, said bit selection circuit, said address counter, Electrically connected to the control circuit, generating a plurality of address indicator signals based on the number of bits set in the bit selection circuit, and providing the address indicator signals whenever an address signal of the decode memory element is input from an external system; And the address memory circuit comprising an address indicator having the address counter as an address indicator required for storing the address.

The data output buffer circuit according to claim 5, wherein the data output buffer circuit is electrically connected to the control circuit and the decode memory element, and the data of the decode memory element corresponding to the address signal when in the read state by the interface circuit. Is stored temporarily, and outputs data corresponding to the address of the decode memory element serially in several circuits. On the contrary, when the interface circuit is in the write-in state, the data inputted several times is temporarily stored to correspond to the address signal. A two-way data buffer for allowing the data to be written to the position of the decode memory element, and electrically connected to the bit selection circuit, the two-way data buffer and the control circuit, based on the number of bits set in the bit selection circuit. The data output indicator signal in the two directions By providing a data buffer, the memory read out of the interface circuit, characterized in that the data includes an index to determine the input / output data bits to be output each time by the two-way data buffer.

The number of bits of the address when the address memory circuit is received is less than the number of bits of the addresses of the respective decode memory elements, and the output / input is performed by the data output buffer. And the number of data bits is less than the number of bits of data corresponding to each address of said decode memory element.

A method of reading data stored in a decode memory device, the method comprising sequentially receiving and storing a part of the address signal until the one address signal of the decode memory device is completely stored, and simultaneously outputting the address signal. And simultaneously receiving and storing data corresponding to the address signal, and sequentially outputting a part of the data of the decode memory element corresponding to the address signal until the data corresponding to the address signal is completely output. Memory reading method comprising the.

A method of writing data into a decode memory element, comprising: sequentially receiving and storing a portion of the address signal until one address signal of the decode memory element is completely stored, and data corresponding to the address signal are completely stored And sequentially storing and storing a part of data of the decode memory element corresponding to the address signal, and simultaneously writing data corresponding to the address signal to the decode memory element. A writing method of a decode memory device.

※ Note: The disclosure is based on the initial application.