KR960001999A

KR960001999A - Memory bank select circuit

Info

Publication number: KR960001999A
Application number: KR1019940013037A
Authority: KR
Inventors: 김양진
Original assignee: 김용현; 주식회사 큐닉스 컴퓨터
Priority date: 1994-06-09
Filing date: 1994-06-09
Publication date: 1996-01-26

Abstract

본 발명은 메모리뱅크 선택회로에 관한 것으로, 특히 시스템버스를 통해 인가되는 어드레스신호(SA0~SA8)의 상태를 감지하고 내부에 설정되어 있는 입ㆍ출력 포트 데이타와 비교하여 클락신호(CLK)를 출력하는 디코더수단(10); 상기 시스템버스를 통해 인가되는 입ㆍ출력 포트 데이타 신호(SD0,SD1)를 각각 인가받아 상기 디코더수단(10)에서 출력되는 클락신호(CLK)에 따라 구동하여 선택신호(S)와 인에이블 신호(EN)를 출력하는 버퍼수단(21,22); 상기 버퍼수단(21,22)에서 출력되는 인에이블 신호(EN)와 선택신호(S)에 따라 입력되는 RAS신호(RAS1, RAS2) (RAS2, RAS3)중 일측 신호를 선택적으로 출력하는 선택수단(31,32)을 구비하여, 사용되는 메모리의 용량을 검색하고 상기 메모리뱅크의 용량에 따라 적절한 RAS(Row Address Strobe)신호를 인가하여 사용될 메모리뱅크를 자동으로 설정함에 따라 점퍼의 세팅이 불필요하고 따라서 점퍼세팅이 오류로 인한 시스템의 오동작을 막을 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory bank selection circuit. In particular, the present invention detects a state of address signals SA0 to SA8 applied through a system bus and outputs a clock signal CLK by comparing the input / output port data set therein. Decoder means for performing; The input / output port data signals SD0 and SD1 applied through the system bus are respectively applied and driven according to the clock signal CLK output from the decoder means 10 to select the signal S and the enable signal. Buffer means 21 and 22 for outputting EN); Selection means for selectively outputting one of the RAS signal (RAS1, RAS2) (RAS2, RAS3) input according to the enable signal (EN) output from the buffer means (21, 22) and the selection signal (S) ( 31, 32) to search the capacity of the memory to be used, and to set the memory bank to be used automatically by applying the appropriate RAS (Row Address Strobe) signal according to the capacity of the memory bank, the setting of the jumper is unnecessary and therefore Jumper setting can prevent malfunction of the system due to error.

Description

Memory bank select circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 메모리뱅크의 선택회로도.3 is a circuit diagram of a memory bank according to the present invention.

Claims

Decoder means (10) for detecting a state of address signals (SA0 to SA8) applied through the system bus and outputting a clock signal (CLK) by comparing with input / output port data set therein; The input / output port data signals SD0 and SD1 applied through the system bus are respectively applied and driven according to the clock signal CLK output from the decoder means 10 to select the signal S and the enable signal. Buffer means 21 and 22 for outputting EN); Selection means for selectively outputting one of the RAS signal (RAS1, RAS2) (RAS2, RAS2) input according to the enable signal (EN) output from the buffer means (21, 22) and the selection signal (S) ( 31, 32, characterized in that the memory bank selection circuit.

2. The memory bank selection circuit as claimed in claim 1, wherein said buffer means (21, 22) are D-flip flops and said selection means (31, 32) are multiplexers.

※ Note: The disclosure is based on the initial application.