JP4220351B2 - Integrated circuit and method capable of simultaneously executing data reading operation and writing operation - Google Patents

Description

  The present invention relates to an integrated circuit, and more particularly to an integrated circuit and a method capable of simultaneously executing a data read operation and a write operation in an integrated circuit with separated input / output ports.

  A general synchronous RAM (SRAM) can transmit only one of read data and write data every clock cycle.

  A double data rate RAM (DRAM) doubles the data transmission rate by transmitting data at each rising and falling edge of the clock. However, in a general memory device, data input and data output are performed through one pin. In the method using the common input / output port, the data input frequency and output frequency are limited because the data input and output are not controlled independently.

  In response to the increased bandwidth of memory devices, products that use separate I / O ports have emerged. That is, the input pin and the output pin are separated so that data input and output can be controlled independently. A memory device having separate input pins and output pins can receive both a read command and a read address, or a write command, a write address, and write data within one cycle of the clock, so that the operating frequency can be increased.

  However, even in a memory device having a separate input / output port, when a read command and a read address or a write command and a write address and write data are received within one clock cycle, the read operation and the write operation are performed with one clock. In order to be executed within a cycle, two memory cell accesses must be executed.

  That is, the activation of the word line for reading and writing data must be executed twice in one cycle of the clock, so that the clock frequency is limited by the activation time of the word line.

  FIG. 1 is a timing diagram illustrating an operation of a memory device having separated input / output ports.

  Since the relationship between the address and the word line and the latency of the input data and output data vary depending on the circuit configuration of the memory device, they are not considered in FIG.

  Referring to FIG. 1, both the write address WADD and the read address RADD are input within one cycle of the clock signal CLK. Addresses A0, A2, A4, A6 input at the rising edge of the clock signal CLK are read addresses RADD, and addresses A1, A3, A5, A7 input at the falling edge of the clock signal CLK are write addresses WADD. .

  RES and WES are a read selection signal and a write selection signal for selecting a read address RADD and a write address WADD, respectively.

  The word line AWL0 is activated by the read address RADD = A0, and data Q0 is output in response to the word line AWL0. If the word line AWL1 is activated in response to the write address WADD = A1, the input data D1 is input.

  Therefore, the length of one cycle of the clock signal CLK is limited to activate the word line AWL0 for the read operation and the word line AWL1 for the write operation. That is, since it is necessary to sequentially access memory cells having different addresses during one cycle of the clock signal, there is a problem that it is difficult to shorten the cycle of the clock signal CLK.

  A technical problem to be solved by the present invention is to provide an integrated circuit capable of increasing the operating frequency of a clock signal by simultaneously executing a read operation and a write operation on a memory cell within one cycle of the clock signal. is there.

  Another technical problem to be solved by the present invention is to provide a method capable of increasing the operating frequency of a clock signal by simultaneously executing a read operation and a write operation on a memory cell within one cycle of the clock signal. It is in.

  In an integrated circuit according to a first embodiment of the present invention for achieving the above technical problem, an input / output port is separated and a write address and a read address are input during one cycle of a clock signal. The memory block includes a plurality of sub memory blocks, a cache memory block corresponding to the memory block, and a tag memory control unit.

  The tag memory control unit reads data stored in the memory block and the cache memory block in response to the write address or the read address, or writes the data to the memory block and the cache memory block.

  In particular, the tag memory control unit may execute the data read operation and the write operation separately for the memory block and the cache memory block, when the write address and the read address are the same. It is characterized by controlling to.

  When the write address and the read address are different, two different sub memory blocks corresponding to the respective write and read addresses are respectively decoded.

  The integrated circuit includes a write address decoding path and a read address decoding path which are separated from each other, and the sub memory block is connected to the write address decoding path and the read address decoding path, respectively. The

  A memory cell having the same lower address among different sub-memory blocks in the memory block corresponds to one memory cell of the cache memory block. The size of the cache memory block is equal to or larger than the size of the one sub memory block.

  The tag memory control unit stores a cache memory address indicating an address of the sub memory block corresponding to the cache memory block and validity determination information for determining whether or not data stored in the cache memory block is valid. To do.

  When the upper address of the write address that selects one of the sub memory blocks is equal to the upper address of the read address, the tag memory control unit determines that both the write address and the read address are the cache memory. If it is not the same as the address, a read operation is executed in the memory block corresponding to the read address, a write operation is executed in the cache memory block, and the read operation and the write operation are executed simultaneously.

  The tag memory control unit may select one of the write address and the read address when the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are equal to each other. If the address matches, the operation corresponding to the address that matches the cache memory address is executed in the cache memory block, and the operation corresponding to the address that does not match is executed in the memory block.

  If both the write address and the read address match the cache memory address, a read operation is executed in the cache memory block, a write operation is executed in the memory block, and the read operation and the write operation are executed simultaneously. The

  When the upper address of the write address that selects one of the sub memory blocks is different from the upper address of the read address, the tag memory control unit determines that one of the write address and the read address is the cache If it matches the memory address, the operation corresponding to the address that matches the cache memory address is executed in the cache memory block, and the operation corresponding to the address that does not match is executed in the memory block.

  If both the write address and the read address match the cache memory address, a read operation is executed in the cache memory block, and a write operation is executed in the memory block.

  If the write address and the read address do not all match the cache memory address, a write operation and a read operation are executed in different sub memory blocks corresponding to the write address and the read address among the selected memory blocks. The read operation and the write operation are performed simultaneously.

  The data is input or output at a single data rate (SDR) or a double data rate (DDR).

  According to a second embodiment of the present invention for achieving the above technical problem, an integrated circuit includes a memory block, a cache memory block, and a decoding block each having a plurality of sub memory blocks in an integrated circuit in which input / output ports are separated. And a tag memory control unit.

  The cache memory block corresponds to each memory block, and stored data is output or written in response to a predetermined cache control signal. The decoding unit generates a decoding signal corresponding to each memory block and controlling the sub memory block in response to a write address or a read address and a predetermined decoding control signal.

  The tag memory control unit receives the write selection signal or the read selection signal, the write address or the read address, and determines whether the write address and the read address input during one cycle of the clock signal are the same. The cache control signal or the decoding control signal is generated so that the data write operation and the data read operation are executed simultaneously.

  The decoding unit includes a plurality of decoding circuits each corresponding to the sub memory block. The decoding circuit is connected to a write address decoding path and a read address decoding path which are separated from each other, and the sub memory block is connected to the write address decoding path and the read address decoding path, respectively.

  The method for simultaneously executing the data read operation and the write operation according to the first embodiment of the present invention to achieve the other technical problem is that the input / output ports are separated and the clock signal is transmitted during one cycle. A write address and a read address are inputted, and a data read operation and a write operation of a plurality of memory blocks each having a plurality of sub memory blocks and a cache memory block corresponding to the memory block are simultaneously executed. (A) determining whether all of the write address and the read address are input or only one of the write address and the read address is input during one period of the clock signal. (B) the write address and the read address If all are input, determining whether the upper address of the write address is the same as the upper address of the read address; (c) if the upper address of the write address and the upper address of the read address are the same For example, determining whether the write address and the read address are the same as a predetermined cache memory address, and (d) if neither the write address nor the read address is the same as the cache memory address Performing a read operation on the memory block corresponding to the read address and executing a write operation on the cache memory block.

  The step d includes (d1) determining whether or not the data stored in the cache memory block is valid, and (d2) if the data stored in the cache memory block is not valid, the reading is performed. Performing a read operation on the memory block corresponding to the address and executing a write operation on the cache memory block; (d3) updating information on data written to the cache memory block; (d4) the cache If the data stored in the memory block is valid, the memory block corresponding to the read address is read, and the valid data stored in the cache memory is read to correspond to the memory block. And (d ) The running write operation to the cache memory block, comprising the step of updating the information about the data written in the cache memory block.

  The cache memory address indicates an address of the sub memory block corresponding to the cache memory block.

  (C) (c1) If one of the write address and the read address matches the cache memory address, the cache memory block performs an operation corresponding to the address that matches the cache memory address. Performing an operation corresponding to an address that does not match the cache memory address in the memory block, and (c2) if both the write address and the read address match the cache memory address, Performing a read operation, performing a write operation on the memory block, and updating information relating to data written to the memory block.

  In the step (b), (b1) if the upper address of the write address and the upper address of the read address are not the same, it is determined whether the write address and the read address match the cache memory address. (B2) If any one of the write address and the read address matches the cache memory address, an operation corresponding to the address that matches the cache memory address is executed in the cache memory block; Performing an operation in the memory block that matches an address that does not match a memory address; (b3) If both the write address and the read address match the cache memory address, read in the cache memory block Performing the operation and updating the information about the data written in the memory block after executing the write operation in the memory block, and (b4) both the write address and the read address are the cache memory address and If they do not match, the method includes performing a write operation and a read operation on different sub memory blocks corresponding to the write address and the read address among the selected memory blocks.

  In the step (a), (a1) if only one of the write address and the read address is input, one of the input write address and the read address is the cache memory address. (A2) If the inputted write address or read address matches the cache memory address, an operation corresponding to the write address or read address that matches the cache memory address is performed. (A3) if the input write address or read address does not match the cache memory address, the write address or read address that does not match the cache memory address; An operation corresponding to less comprising the step of performing in the memory block.

  A memory cell having the same lower address among different sub-memory blocks in the memory block corresponds to one memory cell of the cache memory block.

  The size of the cache memory block is equal to or larger than the size of the one sub memory block.

  An integrated circuit and a method of simultaneously executing a read operation and a write operation according to the present invention include a decoding circuit capable of partitioning a memory block into a plurality of sub memory blocks and decoding each sub memory block, and any sub memory block. Are separately provided with a write address decoding pass and a read address decoding pass, and a cache memory block is provided, and a read operation and a write operation are performed in the memory block and the cache memory block within one cycle of the clock signal. There is an advantage that the operating frequency of the clock signal can be increased by being divided and executed simultaneously.

  For a full understanding of the present invention, its operational advantages, and the objectives achieved by the practice of the present invention, reference should be made to the drawings illustrating the preferred embodiments of the invention and the contents described in the drawings. .

  Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the drawings. The same reference numerals provided in each drawing indicate the same components.

  FIG. 2 is a block diagram showing an integrated circuit according to the first embodiment. Referring to FIG. 2, the integrated circuit 200 corresponds to the memory blocks MB1, MB2, MB3, and MB4 each including a plurality of sub memory blocks SMB1, SMB2 to SMBM, and the memory blocks MB1, MB2, MB3, and MB4. Cache memory blocks CMB1, CMB2, CMB3, and CMB4, and a tag memory control unit 210. In the integrated circuit 200 of FIG. 2, the input / output ports are separated, and the write address WADD and the read address RADD are input during one cycle of the clock signal.

  Since the memory blocks MB1, MB2, MB3, and MB4 have the same structure, and the cache memory blocks CMB1, CMB2, CMB3, and CMB4 have the same structure, the second memory block among the memory blocks MB1, MB2, MB3, and MB4. Description will be made centering on MB2 and the second cache memory block CMB2.

  The write address WADD and the read address RADD are divided into an upper address and a lower address, respectively. The upper address is an address that specifies any one of the plurality of sub memory blocks.

  The basic principle of the present invention is that when the write address WADD and the read address RADD are the same, a data read operation and a write operation are divided into a memory block and a cache memory block and executed simultaneously. This is in the point of shortening the period.

  That is, when the write address WADD and the read address RADD are the same and the same sub memory block (for example, SMB2) among one memory block (for example, the second memory block MB2) is to be accessed at the same time, the sub memory block SMB2 If the data read operation is executed, the data write operation is executed in the cache memory block CMB2 corresponding to the sub memory block SMB2.

  Conversely, if a data write operation is executed in the memory block MB2, the data read operation is executed in the cache memory block CMB2 corresponding to the memory block MB2. By doing so, the data read operation and the data write operation are simultaneously performed in parallel, and the cycle of the clock signal can be shortened.

  Therefore, a memory cell having the same lower address among different sub-memory blocks SMB1, SMB2, and SMB3 to SMBM in the memory block MB2 is made to correspond to one memory cell of the cache memory block CMB2. In addition, since the write operation and the read operation may continue to be executed on the same sub memory block, the size of the cache memory block is the same as or larger than the size of one sub memory block. There must be.

  Such an operation is executed by the tag memory control unit 210. The tag memory control unit 210 reads data stored in the memory blocks MB1, MB2, MB3, MB4 and the cache memory blocks CMB1, CMB2, CMB3, CMB4 in response to the write address WADD or the read address RADD, or the memory block MB1. , MB2, MB3, MB4 and data are written in the cache memory blocks CMB1, CMB2, CMB3, CMB4.

  When the write address WADD and the read address RADD are the same, a read operation is executed in one sub memory block of the memory block MB2, and a write operation is executed in the cache memory block CMB2, the write address WADD and the read address RADD are written in the cache memory block CMB2. The address of the sub memory block in the memory block MB2 to which the data is originally written is stored in the tag memory control unit 210 as a cache memory address.

  That is, the cache memory address is an upper address that designates a sub memory block in which data stored in the cache memory block CNB2 is originally stored.

  The cache memory address stored in the tag memory control unit 210 is accessed using the lower address among the input addresses, and the accessed cache memory address is compared with the upper address of the input address.

  Since the next write address WADD and the read address RADD are the same, and the previous write address WADD and the read address RADD are also the same, the write operation to the cache memory block CMB2 should be executed again. In this case, it must be determined whether the data previously written in the cache memory block CMB2 is valid data.

  If it is valid data, the data previously written in the cache memory block CMB2 is read and written in the corresponding sub memory block of the memory block MB2, and then the data corresponding to the next write address WADD is stored in the cache memory block CMB2. Because it must be written to. Validity determination information for determining whether the data stored in the cache memory block CMB2 is valid is also stored in the tag memory control unit 210.

  When the write address WADD and the read address RADD are different from each other, two different sub-memory blocks corresponding to the write address WADD and the read address RADD are respectively decoded.

  For this, the integrated circuit 200 must be separated such that a write address decoding path (not shown) and a read address decoding path (not shown) are independent of each other. The sub memory blocks SMB1, SMB2, and SMB3 to SMBM must be connected to a write address decoding pass and a read address decoding pass, respectively.

  Data is input or output through an input pin or an output pin in SDR or DDR.

  The operation in which the tag memory control unit 210 controls the memory block MB2 and the cache memory block CMB2 to read and write data will be described later with reference to FIGS.

  FIG. 3 is a block diagram showing an integrated circuit according to the second embodiment. The integrated circuit 300 includes a memory block including a plurality of sub memory blocks SMB1, SMB2, and SMB3 to SMBM, a cache memory block, a decoding unit, and a tag memory control unit 310.

  A cache memory block corresponds to each memory block, and stored data is output or data is written in response to a predetermined cache control signal CCLS. The decoding unit corresponds to each memory block, and generates a decoding signal DS for controlling the sub memory blocks SMB1, SMB2, and SMB3 to SMBM in response to a write address WADD or a read address RADD and a predetermined decoding control signal DCLS. To do.

  FIG. 3 illustrates one memory block MB2 of the plurality of memory blocks, one decoding unit 320 of the plurality of decoding units, and one cache memory block CMB2 of the plurality of cache memory blocks.

  Therefore, the operation of the integrated circuit 300 according to the second embodiment will also be described using the memory block MB2, the cache memory block CMB2, the decoding unit 320, and the tag memory control unit 310 shown in FIG.

  The tag memory control unit 310 receives the write selection signal WES or the read selection signal RES, the write address WADD or the read address RADD, and the write address WADD and the read address RADD input during one cycle of the clock signal are the same. Depending on whether or not there is, the cache control signal CCLS or the decoding control signal DCLS is generated so that the data write operation and the data read operation are executed simultaneously. Although not shown in the drawing, the read selection signal RES and the write selection signal WES can also be applied to the memory block MB2 and the cache memory block CMB2.

  Like the integrated circuit 200 of FIG. 2, the decoding unit includes a plurality of decoding circuits (not shown) corresponding to the sub memory blocks SMB1, SMB2, and SMB3 to SMBM, respectively. This is because when the input write address WADD and the read address RADD are different, two different sub-memory blocks corresponding to the write address WADD and the read address RADD must be decoded.

  For this, a decoding circuit (not shown) is connected to a write address decoding path (not shown) and a read address decoding path (not shown) which are separated from each other, and the sub memory blocks SMB1, SMB2 and SMB3 to SMBM are connected to a write address decoding pass (not shown) and a read address decoding pass (not shown), respectively.

  FIG. 4 is a flowchart illustrating a method for simultaneously executing a data reading operation and a writing operation according to another embodiment. FIG. 5 is a flowchart illustrating step 440 of FIG. FIG. 6 is a flowchart illustrating step 445 of FIG. FIG. 7 is a flowchart illustrating step 455 of FIG.

  Hereinafter, an integrated circuit and method for simultaneously executing a data reading operation and a writing operation will be described with reference to FIGS.

  First, it is determined whether a write address and a read address are input during one cycle of the clock signal, or only one of the write address and the read address is input (step 410). This can be determined by the write selection signal WES and the read selection signal RES in FIG.

  Here, it is assumed that when the write selection signal WES is at a low level or the read selection signal RES is at a low level, a write address WADD and a read address RADD are input, respectively. Of course, the circuit can be configured so that the write address WADD and the read address RADD are input when the levels of the write selection signal WES and the read selection signal RES are high.

  The tag memory control unit 310 receives the write selection signal WES and the read selection signal RES, and receives the write address WADD and the read address RADD.

  If both the write address and the read address are input, it is determined whether the upper address of the write address is the same as the upper address of the read address (step 420).

  The write address WADD and the read address RADD have information specifying the sub memory block in the upper bits. Therefore, when the write address WADD or the read address RADD is input, first, the upper address of the write address WADD or the read address RADD is recognized to determine which submemory block is designated.

  If the upper address of the write address and the upper address of the read address are the same, it is determined whether the write address and the read address are the same as a predetermined cache memory address (step 430).

  If the upper address of the write address WADD is the same as the upper address of the read address RADD, the sub memory block having the same write address WADD and read address RADD is designated.

  The tag memory control unit 310 stores a cache memory address therein. The cache memory address indicates the address of the sub memory block corresponding to the cache memory block CMB2. If the write address WADD is the same as the cache memory address, the write operation must be performed in the cache memory block CMB2.

  If neither the write address nor the read address is the same as the cache memory address, a read operation is performed on the memory block corresponding to the read address, and a write operation is performed on the cache memory block (step 440).

  Step 440 is further described with reference to FIG. If neither the write address nor the read address is the same as the cache memory address, it is determined whether the data stored in the cache memory block is valid (step 510).

  The fact that neither the write address WADD nor the read address RADD is the same as the cache memory address means that the write operation and the read operation must be executed in the same sub memory block of the memory block MB2. However, the write word line and the read word line cannot be simultaneously enabled in the same sub memory block. Therefore, the cache memory block CMB2 is used.

  If the data stored in the cache memory block is not valid, a read operation is performed on the memory block corresponding to the read address, and a write operation is performed on the cache memory block (step 540).

  If the write operation and the read operation are to be executed in the same sub-memory block, the read operation is preferentially executed. Therefore, the read operation is executed in the sub memory block of the memory block MB2 corresponding to the read address RADD. Since the data stored in the cache memory block CMB2 is not valid, a write operation is performed on the cache memory block CMB2.

  The tag memory control unit 310 applies a decoding control signal DCLS to the decoding unit 320. Then, the decoding circuit corresponding to the read address RADD among the decoding circuits (not shown) in the decoding unit 320 generates the decoding signal DS and decodes the corresponding sub memory block. Then, the data stored in the sub memory block is output. In FIG. 3, MDOUT is a path through which data stored in the memory block MB2 is output. Q means an output pin. The output pin Q and the input pin D are separated.

  Further, the tag memory control unit 310 generates a cache control signal CCLS and executes a write operation in the cache memory block MB2.

  Since the data stored in the cache memory block CMB2 has been changed, information about the data written in the cache memory block is updated (step 550). Such update of information is executed by the tag memory control unit 310.

  If the data stored in the cache memory block is valid, a read operation is performed on the memory block corresponding to the read address, and the valid data stored in the cache memory block is read to correspond to the memory. Write to the block (step 520).

  When the write operation and the read operation are to be executed in the same sub memory block, the read operation is preferentially executed. Therefore, the read operation is executed in the sub memory block of the memory block MB2 corresponding to the read address RADD. The reading operation is executed by a decoding control signal DCLS generated by the tag memory control unit 310.

  Since the data stored in the cache memory block CMB2 is valid data, the valid data stored in the cache memory block CMB2 must first be read and the read data must be written to the corresponding sub memory block of the memory block. I must. Then, a write operation is performed on the cache memory block CMB2 in response to the cache control signal CCLS to update information on the data written to the cache memory block CMB2 (step 530). Information update is also executed by the tag memory control unit 310.

  Such data writing operation and reading operation are performed simultaneously. That is, since the write operation and the read operation are performed independently in the sub memory block and the cache memory block CMB2, the write word line and the read word line can be enabled simultaneously. Accordingly, it is possible to solve the problem that a limitation occurs in reducing the cycle of the clock signal by sequentially enabling the write word line and the read word line.

  A write operation and a read operation are performed by determining whether one of the write address and the read address matches the cache memory address, or whether all of the write address and the read address match the cache memory address. Perform (step 445).

  Step 445 is further described with reference to FIG. If one of the write address and the read address matches the cache memory address, an operation corresponding to the address that matches the cache memory address is executed in the cache memory block, and an address that does not match the cache memory address is set. A corresponding operation is performed on the memory block (step 610).

  That is, if the read address RADD matches the cache memory address and the write address WADD does not match the cache memory address, the read operation is executed in the cache memory block CMB2. The tag memory control unit 310 executes the reading operation by applying the cache control signal CCLS to the cache memory block CMB2. The read data is shown as CDOUT in FIG.

  Further, the tag memory control unit 310 generates a decoding control signal DCLS and causes the memory block MB2 to perform a write operation.

  Conversely, if the write address WADD matches the cache memory address and the read address RADD does not match the cache memory address, the write operation is executed in the cache memory block CMB2, and the read operation is executed in the memory block MB2.

  If both the write address and the read address match the cache memory address, a read operation is executed in the cache memory block, a write operation is executed in the memory block, and information about data written in the memory block is obtained. Update (step 620).

  If the write address and the read address all match the cache memory address, it means that all the write and read operations must be performed in the cache memory block CMB2. However, this is not possible for the same reason that the write operation and the read operation are not executed simultaneously in the same sub memory block.

  Therefore, the read operation is executed in the cache memory block CMB2 in response to the cache control signal CCLS. Then, in response to the decoding control signal DCLS, the write operation is executed in the corresponding sub memory block of the memory block MB2. Since the data to be originally written in the cache memory block CMB2 has been written in the sub memory block, the data currently stored in the cache memory block CMB2 becomes invalid data. Therefore, the tag memory control unit 310 is updated with such information.

  In step 420, if the upper address of the write address and the upper address of the read address are not the same, it is determined whether the write address and the read address match the cache memory address (step 450).

The write operation and the read operation are executed by determining whether one of the write address and the read address matches the cache memory address, or whether both the write address and the read address match the cache memory address. To do. (Step 455)
Step 455 is further described with reference to FIG. If any one of the write address and the read address matches the cache memory address, an operation corresponding to the address that matches the cache memory address is executed in the cache memory block and does not match the cache memory address. An operation matching the address is performed on the memory block (step 710).

  That is, if the read address RADD matches the cache memory address and the write address WADD does not match the cache memory address, a read operation is performed in the cache memory block CMB2 in response to the cache control signal CCLS. Further, the tag memory control unit 310 generates a decoding control signal DCLS and causes the memory block MB2 to perform a write operation.

  Conversely, if the write address WADD matches the cache memory address and the read address RADD does not match the cache memory address, the write operation is executed in the cache memory block CMB2, and the read operation is executed in the memory block MB2.

  If both the write address and the read address match the cache memory address, a read operation is executed in the cache memory block, a write operation is executed in the memory block, and information about data written in the memory block is obtained. Update (step 720).

  If both the write address and the read address match the cache memory address, it means that both the write operation and the read operation must be performed in the cache memory block CMB2. However, this is not possible for the same reason that the write operation and the read operation are not executed simultaneously in the same sub memory block.

  Therefore, the read operation is executed in the cache memory block CMB2 in response to the cache control signal CCLS. Then, in response to the decoding control signal DCLS, the write operation is executed in the corresponding sub memory block of the memory block MB2. Since the data to be originally written in the cache memory block CMB2 has been written in the sub memory block, the data currently stored in the cache memory block CMB2 becomes invalid data. Therefore, the tag memory control unit 310 is updated with such information.

  If it is determined in step 450 that the write address and the read address do not match the cache memory address, different sub-memory blocks corresponding to the write address and the read address among the selected memory blocks. A write operation and a read operation are performed (step 460).

  In this case, sub-memory blocks having different write addresses WADD and read addresses RADD are designated. Since different sub memory blocks are designated, a data reading operation and a writing operation are executed using a decoding circuit (not shown) corresponding to each sub memory block.

  A separate decoding circuit capable of decoding each sub memory block is provided, and the write address decoding pass and the read address decoding pass are independently separated. If the sub memory blocks are different, the read operation and the write operation can be executed simultaneously.

  In step 410, if only one of the write address and the read address is input, it is determined whether any one of the input write address and the read address matches the cache memory address. (Step 465).

  If the inputted write address or read address matches the cache memory address, an operation corresponding to the write address or read address that matches the cache memory address is performed in the cache memory block (step 470). In this case, only one of the write address WADD and the read address RADD is input during one cycle of the clock signal.

  At this time, if the input address matches the cache memory address, the corresponding operation is executed in the cache memory block, and if it does not match the cache memory address, the corresponding operation is executed in the memory block MB2.

  That is, if only the write address WADD is input and the input write address WADD coincides with the cache memory address, a write operation is performed on the cache memory block CMB2. Conversely, if only the read address RADD is input and the input read address RADD matches the cache memory address, a read operation is executed on the cache memory block CMB2. At this time, the tag memory control unit 310 generates a cache control signal CCLS and causes the cache memory block CMB2 to perform a write or read operation.

  If the input write address or read address does not match the cache memory address, an operation corresponding to the write address or read address that does not match the cache memory address is performed in the memory block (step 475).

  FIG. 8 is a timing chart for explaining the operation of the integrated circuit of the present invention. Referring to FIG. 8, it can be seen that one cycle of the clock signal CLK is shortened to half of one cycle of the clock signal CLK of FIG. This means that the frequency of the clock signal CLK has been doubled.

  Conventionally, since the word line for the write operation and the word line for the read operation are sequentially enabled during one cycle of the clock signal CLK, it is difficult to shorten the cycle of the clock signal CLK.

  However, according to the integrated circuit and method of the present invention, as can be seen from FIG. 8, the word line WL1 for the read operation and the word line WL2 for the write operation are simultaneously enabled during one period of the clock signal CLK. Therefore, the cycle of the clock signal CLK can be shortened.

  The present invention can be applied to various integrated circuits in which input / output ports are separated and both a write address and a read address can be received within one cycle of a clock signal. Data can be input / output through input pins or output pins separated into SDR or DDR.

  As described above, the preferred embodiment has been disclosed in the drawings and specification. Certain terminology has been used herein for the purpose of describing the present invention only, and is intended to limit the scope of the invention as defined in the meaning and claims. It was not used. Accordingly, those skilled in the art will appreciate that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention must be defined by the technical idea of the claims.

  The present invention relates to an integrated circuit, and can be suitably used particularly in a semiconductor integrated circuit having a high operation speed and separated input / output ports, such as a double data rate RAM (DDR RAM).

FIG. 5 is a timing diagram illustrating an operation of a memory device having separated input / output ports. 1 is a block diagram showing an integrated circuit according to a first embodiment. It is a block diagram which shows the integrated circuit by 2nd Example. 6 is a flowchart illustrating a method for simultaneously executing a data reading operation and a writing operation according to another embodiment. FIG. 5 is a flowchart illustrating step 440 in FIG. 4. FIG. FIG. 5 is a flowchart illustrating step 445 in FIG. 4. FIG. FIG. 5 is a flowchart illustrating step 455 of FIG. 4. FIG. 6 is a timing chart for explaining the operation of the integrated circuit of the present invention.

Explanation of symbols

200 Integrated circuit 210 Tag memory control unit SMB1 to SMBM Sub memory block MB1, MB2, MB3, MB4 Memory block CMB1, CMB2, CMB3, CMB4 Cache memory block WADD Write address RADD Read address

Claims (32)

In an integrated circuit in which an input / output port is separated and a write address and a read address may be input during one cycle of a clock signal,
Memory blocks each having a plurality of sub-memory blocks;
A cache memory block corresponding to the memory block;
A tag memory control unit that reads data stored in the memory block and the cache memory block in response to the write address or the read address, or writes the data to the memory block and the cache memory block. And
The tag memory control unit
When the write address and the upper address of the read address input during one cycle of the clock signal are the same, the data read operation and the write operation are performed on the memory block and the cache memory block, respectively. integrated circuit according to claim and Turkey controls to run simultaneously during the one period is divided.   2. The integration according to claim 1, wherein when the write address and the read address are different, two different sub-memory blocks corresponding to the write address and the read address are respectively decoded. circuit. The integrated circuit comprises:
A write address decoding path and a read address decoding path which are separated from each other;
The sub memory block is
2. The integrated circuit of claim 1, wherein the integrated circuit is connected to the write address decoding pass and the read address decoding pass, respectively.   2. The integrated circuit according to claim 1, wherein memory cells having the same lower address among different sub-memory blocks in the memory block correspond to one memory cell of the cache memory block.   2. The integrated circuit according to claim 1, wherein a size of the cache memory block is equal to or larger than a size of the one sub memory block.   The tag memory control unit stores a cache memory address indicating an address of the sub memory block corresponding to the cache memory block and validity determination information for determining whether or not data stored in the cache memory block is valid. The integrated circuit according to claim 1. The tag memory control unit
When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are equal,
If neither the write address nor the read address is the same as the cache memory address, execute a read operation on the memory block corresponding to the read address and execute a write operation on the cache memory block,
The integrated circuit according to claim 6, wherein the read operation and the write operation are performed simultaneously. The tag memory control unit
When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are equal,
If one of the write address and the read address matches the cache memory address,
An operation corresponding to an address that matches the cache memory address is performed in the cache memory block, and an operation corresponding to an address that does not match is performed in the memory block;
If both the write address and the read address match the cache memory address,
A read operation is performed on the cache memory block and a write operation is performed on the memory block;
The integrated circuit according to claim 6, wherein the read operation and the write operation are performed simultaneously. The tag memory control unit
When the upper address of the write address and the upper address of the read address for selecting one of the sub memory blocks are different,
If one of the write address and the read address matches the cache memory address,
An operation corresponding to an address that matches the cache memory address is performed in the cache memory block, and an operation corresponding to an address that does not match is performed in the memory block;
If both the write address and the read address match the cache memory address,
A read operation is performed on the cache memory block and a write operation is performed on the memory block;
If both the write address and the read address do not match the cache memory address,
A write operation and a read operation are executed in different sub memory blocks corresponding to the write address and the read address among the selected memory blocks,
The integrated circuit according to claim 6, wherein the read operation and the write operation are performed simultaneously.   The integrated circuit according to claim 1, wherein the data is input or output by SDR or DDR. In an integrated circuit where the input and output ports are separated,
Memory blocks each having a plurality of sub-memory blocks;
A plurality of cache memory blocks corresponding to the respective memory blocks, in which data stored in response to a predetermined cache control signal is output or data is written;
A plurality of decoding units corresponding to the respective memory blocks, and generating a decoding signal for controlling the sub memory block in response to a write address or a read address, and a predetermined decoding control signal;
Write select signal or a read select signal, receiving the write address or the read address, if said write address input during one cycle of the clock signal and the read address are the same, it said data write operation and an integrated circuit read operation, characterized by comprising: a tag memory control unit for generating by Ru runs urchin said cache control signal and the decoded control signals simultaneously during the single cycle.   12. The integrated circuit of claim 11, wherein each of the decoding units includes a plurality of decoding circuits corresponding to the sub memory blocks. The decoding circuit is connected to a write address decoding path and a read address decoding path which are separated from each other,
The integrated circuit of claim 12, wherein the sub memory block is connected to the write address decoding pass and the read address decoding pass, respectively.   The integrated circuit of claim 11, wherein when the write address and the read address are different, two different sub-memory blocks respectively corresponding to the write address and the read address are decoded. circuit.   12. The integrated circuit according to claim 11, wherein memory cells having the same lower address among different sub-memory blocks in the memory block correspond to one memory cell of the cache memory block.   12. The integrated circuit according to claim 11, wherein the size of the cache memory block is equal to or larger than the size of the one sub memory block.   The tag memory control unit stores a cache memory address indicating an address of the sub memory block corresponding to the cache memory block and validity determination information for determining whether data stored in the cache memory block is valid. The integrated circuit according to claim 11. The tag memory control unit
When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are equal,
If neither the write address nor the read address is the same as the cache memory address, the decoding control signal is generated to perform a read operation on the memory block corresponding to the read address, and the cache control signal is Occurs and performs a write operation on the cache memory block;
The integrated circuit of claim 17, wherein the read operation and the write operation are performed simultaneously. The tag memory control unit
When the upper address of the write address and the upper address of the read address that select one of the sub memory blocks are equal,
If one of the write address and the read address matches the cache memory address,
An operation corresponding to an address that matches the cache memory address by generating the cache control signal is executed in the cache memory block, and an operation corresponding to an address that does not match the cache memory address by generating the decoding control signal Is executed on the memory block,
If both the write address and the read address match the cache memory address,
Generating the cache control signal to perform a read operation in the cache memory block, generating the decoding control signal to perform a write operation in the memory block;
The integrated circuit of claim 17, wherein the read operation and the write operation are performed simultaneously. The tag memory control unit
When the upper address of the write address and the upper address of the read address for selecting one of the sub memory blocks are different,
If one of the write address and the read address matches the cache memory address,
An operation corresponding to an address that matches the cache memory address by generating the cache control signal is executed in the cache memory block, and an operation corresponding to an address that does not match the cache memory address by generating the decoding control signal Is executed on the memory block,
If both the write address and the read address match the cache memory address,
Generating the cache control signal to perform a read operation in the cache memory block, generating the decoding control signal to perform a write operation in the memory block;
If the write address and the read address do not all match the cache memory address,
Generating a decoding control signal to perform a write operation and a read operation in different sub-memory blocks corresponding to the write address and the read address among the selected memory blocks;
The integrated circuit of claim 17, wherein the read operation and the write operation are performed simultaneously.   The integrated circuit according to claim 11, wherein the data is input or output by SDR or DDR. The input / output ports are separated, and a write address and a read address may be input during one cycle of the clock signal. A plurality of memory blocks each having a plurality of sub memory blocks, and the memory block In a method of simultaneously executing a data read operation and a write operation of an integrated circuit having a corresponding cache memory block,
(A) determining whether the write address and the read address are input together or only one of the write address and the read address is input during one cycle of the clock signal;
(B) determining whether the upper address of the write address and the upper address of the read address are the same if the write address and the read address are input together;
(C) if the upper address of the write address and the upper address of the read address are the same, determining whether the write address and the read address are the same as a predetermined cache memory address;
(D) If neither the write address nor the read address is the same as the cache memory address, performing a read operation on the memory block corresponding to the read address and executing a write operation on the cache memory block And comprising
Step (d), how to perform the read operation and the write operation and the clock signal of 1 running simultaneously during a period to the data characterizing the benzalkonium the read and write operations at the same time. In step (d),
(D1) determining whether the data stored in the cache memory block is valid;
(D2) If the data stored in the cache memory block is not valid, performing a read operation on the memory block corresponding to the read address and executing a write operation on the cache memory block;
(D3) updating information related to data written to the cache memory block;
(D4) If the data stored in the cache memory block is valid, a read operation is executed on the memory block corresponding to the read address, and the valid data stored in the cache memory block is read. Writing to the corresponding memory block;
The data read operation according to claim 22, further comprising: (d5) performing a write operation on the cache memory block to update information on the data written to the cache memory block. A method of executing a write operation simultaneously.   23. The method according to claim 22, wherein the cache memory address represents an address of the sub memory block corresponding to the cache memory block. In step (c),
(C1) If one of the write address and the read address matches the cache memory address, an operation corresponding to the address that matches the cache memory address is executed in the cache memory block, and the cache memory address matches Performing an operation corresponding to a non-address on the memory block;
(C2) If both the write address and the read address match the cache memory address, a read operation is executed in the cache memory block, a write operation is executed in the memory block, and the data written in the memory block 23. The method for simultaneously executing a data reading operation and a data writing operation according to claim 22, further comprising the step of updating information on the data. The step (b)
(B1) If the upper address of the write address and the upper address of the read address are not the same, determining whether the write address and the read address match the cache memory address;
(B2) If any one of the write address and the read address matches the cache memory address, an operation corresponding to the address that matches the cache memory address is executed in the cache memory block, and the cache memory address Performing an operation on the memory block corresponding to an address that does not match
(B3) If both the write address and the read address coincide with the cache memory address, a read operation is executed in the cache memory block, a write operation is executed in the memory block, and then written in the memory block Updating information about the data,
(B4) If both the write address and the read address do not match the cache memory address, a write operation and a read are performed in different sub memory blocks corresponding to the write address and the read address among the selected memory blocks. The method of performing the data reading operation and the writing operation simultaneously according to claim 22, comprising: performing an operation. The step (a) includes:
(A1) If only one of the write address and the read address is input, determining whether one of the input write address and the read address matches the cache memory address When,
(A2) If the inputted write address or read address matches the cache memory address, executing an operation corresponding to the write address or read address matching the cache memory address in the cache memory block;
(A3) If the inputted write address or read address does not match the cache memory address, performing an operation corresponding to the write address or read address not matching the cache memory address in the memory block; 23. The method according to claim 22, wherein the data read operation and the data write operation are performed simultaneously.   23. The data reading operation and writing according to claim 22, wherein memory cells having the same lower address among different sub-memory blocks in the memory block correspond to one memory cell of the cache memory block. A method of performing operations simultaneously.   The method according to claim 22, wherein a size of the cache memory block is equal to or larger than a size of the one sub memory block.   The method according to claim 22, wherein the data is input or output by SDR or DDR. A separate input and output data port; and
A memory block comprising a plurality of sub-memory blocks;
A cache memory block capable of storing at least the same amount of data as data stored in one sub-memory block;
When a valid entry is made in a cache memory block having a corresponding sub memory block address, and the address at which the read operation and the write operation are performed indicates the same sub memory block, one of two operations is performed as the cache. integrated circuit, characterized by comprising a control to filter Gumemori controller to execute concurrently the read and write operations during one cycle of the clock signal by performing using the memory block. Partitioning the memory block into a plurality of sub-memory blocks;
Maintaining a cache memory block capable of storing at least as much data as data stored in one sub-memory block;
Making a valid entry in a cache memory block having a corresponding sub-memory block address;
When a memory block having the same address at which a read operation and a write operation are performed is designated, a clock signal is used for the read operation and the write operation by executing one of the two operations using the cache memory block. performed simultaneously during one cycle of,
Performing simultaneous read and write operations in different sub memory blocks during one period of the clock signal, if possible, in an integrated circuit simultaneously How to run.

Images