JP2009217310A - Memory access method and memory access device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform burst transfer from a write buffer to a memory in write cycles fewer than a conventional manner. <P>SOLUTION: A bus master 11 writes an address, a byte mask, and write data in a write buffer 12. The write buffer control unit 13 determines data to be transferred to a shared memory 20 based on the state of a byte mask output to be output from the write buffer 12, and controls a register update control signal. Thus, data to be transferred to the shared memory 20 are set in a register 14. When the data transfer to the shared memory 20 is started, the write buffer control unit 13 controls a selector control signal, and causes a selector 15 to select data with no byte mask set thereto and stored in the register 14, and performs burst transfer through a shared bus 40 to the shared memory 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory access method and a memory access device, and more particularly to a memory access method and a memory access device that enable memory writing using a byte mask function.

  Conventionally, in a memory access method in which a central processing unit (CPU) writes data to a memory, a write buffer is provided between the CPU and the memory, and the CPU includes a write address, write data, and a byte mask. Data is once written, and then the write buffer control unit performs a write operation to the memory.

  In addition, a memory access method in which the write buffer control unit burst-transfers data written to the write buffer a plurality of times by the CPU to the memory is also known (see, for example, Patent Document 1).

  A write access operation by burst transfer from a write buffer to a shared memory in a shared memory architecture (UMA) system by the memory access method described in Patent Document 1 will be described with reference to FIG.

  Assume that the shared memory is an SDR SDRAM (Single Data Rate Synchronous Dynamic Random Access Memory) having a data bus width of 32 bits. FIG. 7A shows an operation clock CLK of the SDRAM, and FIG. 7B shows a command signal for controlling the SDRAM. This command signal includes CS (Chip Select), RAS (Row Address Strobe), CAS (Cas Address Strobe), and WE (Write Enable).

  In FIG. 7B, “ACT” on the command bus represents an ACTIVE command, and “WRITEa” and “WRITEb” represent WRITE commands. FIG. 7C shows byte mask data DQM, and FIG. 7D shows data bus data DQ. These command signals, DQM, and DQ values are taken into the SDRAM at the rising edge of the clock CLK.

  The burst transfer mode to SDRAM which is a shared memory is set to BL (Burst Length) = 4, for example. First, as shown in FIG. 7B, the CPU issues an ACT command, and after 3 cycles, issues a WRITEa command to control the 4-cycle periods DQM and DQ. Subsequently, a WRITEb command is issued to control the DQM and DQ during the 4-cycle period. In normal SDRAM access, a PRE (Precharge) command continues, but is omitted here. The row addresses (row addresses) accessed by WRITEa and WRITEb are the same. In this operation, 11 cycles are required from the ACT to the completion of the WRITE operation.

  FIG. 8 shows a sequence diagram according to this conventional memory access method. This sequence diagram is a system in which a shared memory 50 is connected to a bus master 51 and a peripheral bus master 52 in a CPU via a shared bus. The bus master 51 reads data from a write buffer (not shown) and burst-transfers and writes the data to the shared memory 50 via the shared bus (denoted by 53 in FIG. 8).

  Thereafter, the peripheral bus master 52 reads the data from the write buffer, writes the data by burst transfer to the shared memory 50 via the shared bus (indicated by 54 in FIG. 8). In this example, the peripheral bus master 52 performs burst transfer after the transfer waiting time T1 elapses after the bus master 51 performs burst transfer.

  In this way, it is possible to shorten the time that the CPU waits for the completion of memory writing and to increase the memory transfer efficiency. In particular, the faster the CPU operating clock is, the greater the effect obtained.

JP 2001-147854 A

  However, in particular, when the bus width of the shared bus is wider than the processing data width of the bus master, and the CPU as the bus master performs a memory write operation with a single or a short number of words, in order to protect data that cannot be rewritten. A lot of byte masks are used. As a result, when burst transfer is performed from the write buffer to the memory, a situation occurs in which a byte mask is set for all data to be written in a certain write cycle. Such a write cycle is an essentially unnecessary write cycle because no change is made to the data in the memory, and is not preferable in terms of memory access efficiency.

  For example, in the conventional memory access method described with reference to FIG. 7, there are a total of 6 cycles in which DQM [3: 0] is 0xf as shown in FIG. Regardless, since data rewriting of the shared memory (SDRAM) does not occur, this is a useless write cycle.

  The present invention has been made in view of the above points, and an object thereof is to provide a memory access method and a memory access device capable of performing burst transfer from a write buffer to a memory with a smaller number of write cycles than in the prior art.

  To achieve the above object, according to a first aspect of the present invention, there is provided a memory access method in which data is burst-transferred and written to a shared memory via a shared bus, and the data, byte mask, and address are temporarily written from a bus master to a write buffer. 1 and when the data and address written in the write buffer are burst transferred to the shared memory, it is determined whether or not the data to be transferred is data in which all the byte masks corresponding to the data are set. And a third step of selecting data determined not to have all the byte masks set by the second step and transferring the burst together with the address to the shared memory via the shared bus It is characterized by including.

  In order to achieve the above object, the second invention provides a bus master that outputs data, a byte mask, and an address in a memory access device that writes data by burst transfer to a shared memory via a shared bus; The write buffer that temporarily writes the data, byte mask, and address output from the memory, and when the data and address written in the write buffer are burst transferred to the shared memory, the data to be transferred has a byte mask corresponding to the data. A write buffer control unit that determines whether or not all data is set, and a data that is determined not to have all byte masks set by the write buffer control unit, and a shared bus together with an address Burst transfer to shared memory via And having a-option means.

  In the first and second aspects of the invention, data for which all byte masks are set is not transferred, and data determined not to be set for all byte masks is selected for burst transfer to the shared memory. This eliminates the need for a data write cycle in which all the byte masks that do not change the data in the shared memory are set.

  According to the present invention, burst transfer from the write buffer to the memory can be performed with a smaller number of write cycles than before in memory writing in which the bus master frequently uses byte masks, thereby improving the memory access efficiency of the entire system. You can also.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of a memory access apparatus according to the present invention. The memory access device 10 is connected to the shared memory 20 and the peripheral bus master 30 via the shared bus 40. The memory access device 10 includes a bus master 11, a write buffer 12, a write buffer control unit 13, a plurality of registers 14, and a selector 15 by a CPU. That is, the write buffer 12 and the write buffer control unit 13 are provided between the bus master 11 and the shared bus 40, and a plurality of registers 14 and a selector 15 are arranged between the write buffer 12 and the shared memory 20. Yes.

  The bus master 11 supplies them to the write buffer 12 in units of addresses, data, and byte masks. The write buffer control unit 13 receives a data write request signal from the bus master 11 and outputs a data write approval signal. Further, the write buffer control unit 13 supplies a buffer control signal to the write buffer 12. The write buffer 12 supplies a byte mask to the write buffer control unit 13 and outputs an address and data to a plurality of registers 14, respectively.

  The plurality of registers 14 are registers having the same bit width as the shared bus 40. The selector 15 is for connecting one of the plurality of registers 14 to the shared bus 40 based on a selector control signal from the write buffer control unit 13. The plurality of registers 14 are controlled to be updated by a register update control signal from the write buffer control unit 13.

  The shared memory 20 includes an SDRAM 22 as a memory unit that stores data entities, and a shared memory controller (SDRAM controller) 21 that is a control unit that performs data write control on the SDRAM 22. The shared memory controller 21 performs control to write data output from the write buffer 12 through the shared bus 40 to the SDRAM 22.

  Here, a control signal (Command), an address signal (Address), and a byte mask (DQM) are output from the shared memory controller 21 to the SDRAM 22. Data (DQ) is transferred between the shared memory controller 21 and the SDRAM 22.

  The clock (CLK) used for the bus master 11, the write buffer 12, the write buffer control unit 13, and the plurality of registers 14 and the clock (CLK) input to the shared memory controller 21 and SDRAM 22 are common clocks. Operate in sync with each other.

  In this embodiment, data transfer from the write buffer 12 to the shared memory 20 is performed by burst transfer. At this time, as will be described later, the data for which the byte mask is set is not transferred to the shared memory 20 and is transferred from the write buffer 12 to the shared memory 20 by a plurality of registers 14 and selectors 15. The transfer data is selected so that the transfer data is not interrupted.

  Next, the operation of the present embodiment will be described in more detail with reference to the flowchart of FIG. First, when the bus master 11 performs a write access to the shared memory 20, it once communicates with the write buffer control unit 13 to write the address, byte mask, and write data to the write buffer.

  That is, first, the bus master 11 outputs a data write request signal to the write buffer control unit 13. Thereby, the write buffer control unit 13 determines whether or not writing to the write buffer 12 is possible (step S1). When the write buffer control unit 13 determines that data can be written to the write buffer 12, it outputs a data write approval signal to the bus master 11.

  Upon receiving this data write approval signal as an input, the bus master 11 writes an address, byte mask, and write data for one word into the write buffer 12 (step S2), and then determines whether all data has been written (step S3). ) Repeat steps S2 and S3 until all data is written.

  Subsequently, after all the data has been written, the write buffer control unit 13 determines whether or not to wait for the bus master 11 to perform data write processing a plurality of times (step S4), and performs the plurality of write processing. When waiting, the process returns to step S1, and when not waiting, it is determined whether data transfer from the write buffer 12 to the shared memory 20 is possible (step S5).

  When the write buffer control unit 13 determines in step S5 that data transfer from the write buffer 12 to the shared memory 20 is possible, the write buffer control unit 13 first controls the buffer control signal, and outputs the byte mask output and data output output from the write buffer 12. Then, based on the updated byte mask output state, it is determined which data is transferred to the shared memory 20, and the register update control signal is controlled. As a result, data transferred to the shared memory 20 is set in the register 14. Then, when the data transfer to the shared memory 20 starts, the write buffer control unit 13 controls the selector control signal to cause the selector 15 to select one word of data for which the byte mask stored in the register 14 is not set. Is transferred to the shared memory 20 via the shared bus 40 (step S6).

  Subsequently, the write buffer control unit 13 determines whether or not the transfer of all data prepared in the write buffer 12 is completed (step S7), and repeats the processes of steps S6 and S7 until the transfer of all data is completed. At this time, the write buffer control unit 13 checks the remaining amount of data stored in the register 14 and controls the buffer control signal and the register update control signal before the burst transfer is interrupted. Get byte mask output.

  In this way, when the transfer of all the prepared data in the write buffer 12 is completed, the data transfer process is terminated, and the process proceeds to a data write control process from the bus master 11 to the write buffer 12.

  FIG. 3 shows a sequence diagram when the write buffer control unit 13 determines to wait for the bus master 11 to finish the two write operations in step S4 of FIG. As shown in FIG. 3, after waiting for the bus master 11 to sequentially perform the first memory write access and the second memory write access to the write buffer control unit 13 (steps S11 and S12), the write buffer control is performed. The unit 13 collectively transfers the address and data of the address, data, and byte mask written in the write buffer 12 to the shared memory 20 (step S13; steps S5 to S7 in FIG. 2).

  Next, the data storage configuration of the write buffer 12 will be described. The contents stored in the write buffer 12 are a set of addresses, byte masks, and data, and have a size of one word or more (the addresses are outside the scope of the present invention).

  In the configuration of the present embodiment shown in FIG. 1, if the data bus width of the shared bus 40 is 128 bits and the byte mask is 16 bits, the write buffer for data of 8 bits (= 1 byte) per 1 byte mask. The control unit 13 controls whether to write to the shared memory 20 or not. Here, when the value of the byte mask is “1”, “data is not written”, and when the value is “0”, “data is written”. Note that a byte mask value of “1” means that a byte mask is set (all set) for data corresponding to the byte mask. The byte mask value of “0” means that no byte mask is set for the data corresponding to the byte mask (all are not set).

  When the bus master 11 is a 32-bit processing CPU, the contents of the write buffer 12 are as shown in FIG. 4 when a single word write access is performed twice. In the first memory write access of the bus master 11, only the byte mask corresponding to Da0 among the byte masks corresponding to the written data Da0, Da1, Da2, and Da3 in FIG. ”, The value of the byte mask corresponding to Da0 to Da3 is“ 1 ”. Therefore, in the first memory write access of the bus master 11, the data of Da0 is to be written. On the other hand, the data Da1 to Da3 are output to the data bus, but are not written to the shared memory 20 due to the byte mask whose value is “1”.

  In the second write access of the bus master 11, only the byte mask corresponding to Db1 among the byte masks corresponding to the written data Db0, Db1, Db2, and Db3 in FIG. “0”, the value of the byte mask corresponding to Db0, Db2, and Db3 is “1”. Therefore, in the second memory write access of the bus master 11, data of Db1 in FIG. 4 is to be written. On the other hand, the data Db0, Db2, and Db3 are not written to the shared memory 20 by the byte mask.

  Next, a write access operation to the SDRAM 22 in the shared memory 20 by the memory access method of the present embodiment will be described with reference to the timing chart of FIG. In the memory access method of the present embodiment, the SDRAM 22 is controlled with BL (Burst Length) = 1.

  First, the shared memory controller 21 issues an ACT command to the SDRAM 22 as a control signal (Command) as shown in FIG. Subsequently, after three cycles of the clock (CLK) shown in FIG. 5A, a WRITEa command is issued as shown in FIG. 5B, and Da0 is output as data DQ as shown in FIG. 5D. , 0x0 is output to the byte mask DQM as shown in FIG.

  Then, after one cycle, the shared memory controller 21 does not issue a WRITE command for Da1 to Da3 in which DQM is set to 0xF in the conventional method, and issues a WRITEb command as shown in FIG. Db1 and 0x0 are output to DQM.

  Thus, since the WRITE command that outputs Db0 and Db2 to Db3 to DQ in the conventional method as shown in FIG. 7 is not issued, the write operation that took 11 cycles in the conventional method as shown in FIG. However, in this embodiment, it can be completed in 5 cycles.

  As described above, in the present embodiment, the write buffer control unit 13 is provided with a function for controlling the write cycle issuance using the byte mask in the write buffer 12, thereby performing burst transfer from the write buffer 12 to the shared memory 20. It is possible to prevent useless write cycles in operation.

  By the way, when another bus master is ready to access the shared memory 20 while a certain bus master is accessing the shared memory 20, the other bus masters complete the current memory access. Memory access is awaited.

  That is, also in this embodiment, as shown in the sequence diagram of FIG. 6, after the burst transfer of data from the bus master 11 to the shared memory 20 is completed (step S21), the peripheral bus master 30 performs the burst transfer of data to the shared memory 20. Is started (step S22). However, in this embodiment, as a result of optimization and shortening of access to the shared memory 20 of the bus master 11, the transfer waiting time of the peripheral bus master 30 is shown in FIG. 6 from T1 of the conventional method shown in FIG. Shortened to T2.

  Therefore, according to the present embodiment, when the peripheral bus master 30 is ready to transfer data during memory access of the shared memory 20 of the bus master 11, the peripheral bus master 30 transfers data faster than the conventional method. Therefore, it can be said that this embodiment can also improve the memory access efficiency of the entire system.

It is a block diagram of one embodiment of a memory access device of the present invention. It is a flowchart for operation | movement description of the apparatus shown in FIG. It is a sequence diagram which shows an example of the write-in operation | movement from the bus master in this invention apparatus to shared memory. It is a block diagram of an example of the data stored in the write buffer in this invention apparatus. 6 is a timing chart for explaining an example of operation when data in a write buffer is written into a shared memory by the method of the present invention. It is a sequence diagram showing the memory access efficiency improvement including the peripheral bus master by this invention. 10 is a timing chart for explaining an example of operation when data in a write buffer is written into a shared memory by a conventional method. It is a sequence diagram showing memory access including a peripheral bus master by a conventional method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory access apparatus 11 Bus master 12 Write buffer 13 Write buffer control unit 14 Register 15 Selector 20 Shared memory 21 Shared memory controller (SDRAM controller)
22 SDRAM
30 Peripheral bus master 40 Shared bus

Claims (2)

In a memory access method for writing data by burst transfer to a shared memory via a shared bus,
A first step of temporarily writing data, byte mask, and address from the bus master to the write buffer;
When burst-transferring the data and address written in the write buffer to the shared memory, it is determined whether the data to be transferred is data in which all the byte masks corresponding to the data are set. Two steps,
A third step of selecting data determined not to have all the byte masks set by the second step and transferring the burst together with the address to the shared memory via the shared bus; and A memory access method comprising: In a memory access device that writes data by burst transfer to a shared memory via a shared bus,
A bus master that outputs data, byte masks, and addresses;
A write buffer for temporarily writing the data, byte mask, and address output from the bus master;
When burst-transferring the data and address written in the write buffer to the shared memory, writing to determine whether the data to be transferred is data in which all the byte masks corresponding to the data are set A buffer control unit;
Selecting means for selecting, by the write buffer control unit, data that is determined not to have all the byte masks set therein, and burst-transferring the address together with the address to the shared memory via the shared bus; A memory access device.

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