JP2616714B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a bank configuration. The present invention also relates to an address generation method for a memory having a bank configuration.

[0002]

2. Description of the Related Art As the capacity of a semiconductor memory device has been increased, various methods have conventionally been taken to shorten the test time.

For example, Japanese Patent Application Laid-Open No. 4-349300 discloses a semiconductor memory device which solves the problem that the test requires a long time and the productivity of an integrated circuit is reduced, as shown in FIG. A semiconductor memory device which reads out storage information of a memory cell by row-decoding an upper bit to select a word line and column-decoding a lower bit of the address signal to select a bit line. A plurality of first column decoders (53) which divide the cell into a plurality of parts and decode the upper bits of the lower bits of the address signal to select the bit lines of each of the divided memory cells.
And a plurality of column latch circuits (55) for respectively latching the outputs of the first column decoders (53), and a lower-order bit of the lower-order bits of the address signal to decode one of the column latch circuits (55). ) And select
A second column decoder (56) for outputting the latch information
Has been proposed.

That is, Japanese Patent Application Laid-Open No. 4-349300 discloses that the lower bits of an address signal are further divided and the upper bits are divided into a plurality of first column decoders (53).
And the lower bit is sent to the second column decoder (56) at a timing later than the upper bit, and the storage information read from each of the plurality of divided memory cells (54) is latched. After that, by selecting one by one, the access time at the time of the test is reduced.

In order to shorten the test time of a memory cell, for example, Japanese Patent Application Laid-Open No. 62-84499 discloses that a memory cell matrix is divided into a plurality of sections so that address designation and data input / output can be performed in parallel. Configured to
There is disclosed a semiconductor memory device that reduces test time by performing parallel processing when testing a memory cell.

Further, as an address generation method of a pattern generator which enables a division test when testing an IC memory, for example, JP-A-59-14839 discloses an address generation method.
An address generation register for determining a division width in the X and Y directions, a register for specifying an address of a division unit divided by the register, and a register for specifying an address in the division unit; A scheme has been proposed. In this method, the register for generating addresses in the X direction and the Y direction has a double structure, and the address is divided into arbitrary units to reduce the test time.

[0007]

As described above, in order to increase the capacity of a semiconductor memory device (also referred to simply as a "memory"), the test time has conventionally been shortened by a division process.

However, in a small-capacity memory, in order to avoid an increase in hardware, the above-described division processing is not generally performed, and a test is performed in accordance with a normal access method.

As shown in FIG. 4, a memory composed of a plurality of banks includes, as address specification registers, a bank specification register 41 for specifying a bank, an in-bank address specification register 42 for specifying an address in the bank,
, And each has a built-in incrementer to specify an address. The memory includes, as shown in FIG. 2, an address designation register 21 for giving an address and a memory 22.
FIG. 4 is a diagram showing a conventional circuit configuration of the addressing register 21 of FIG.

Referring to FIG. 4, the MSB (most significant bit) of the incrementer of the in-bank addressing register 42
Is input to an AND gate 44, and is logically ANDed with the test mode signal 43, and the AND gate 44
Is the L of the incrementer of the bank designation register 41.
Connected to carry input of SB (least significant bit).

Next, the operation of the addressing register shown in FIG. 4 will be described.

Normally, the test mode signal 43 is set to logic "0", the output of the AND gate 44 is always set to logic "0", and carry from the in-bank address designation register 42 to the bank designation register 41 is ignored.

Therefore, the bank designation register 41 and the in-bank address designation register 42 are separated from each other.

However, when the bank designation register 41 and the in-bank address designation register 42 are separated,
In testing a memory, it is usually necessary to specify all addresses, and the in-bank addressing register 42
At the time when the count of the bank designation register 41 is completed.
The trouble of resetting is generated.

Therefore, at the time of testing, the test mode signal 43 is set to logic "1" in order to speed up the test, and the carry output of the MSB (most significant bit) of the incrementer of the in-bank addressing register 42 is ANDed. By configuring the gate 44 to be conductive so as to effectively propagate to the bank designation register 41, the in-bank address designation register 42 is connected to the bank designation register 41. The in-bank address designation register 42 outputs the lower bits of the address, and the bank designation register 41 outputs the upper bits of the address.

By simply incrementing (adding one by one) from the start address to the end address, it is possible to change the address and perform a test.

However, in this conventional method, the in-bank addressing register 42 (the number of bits is n)
When the memory range specified by (i.e., the memory capacity of one bank) matches 2 ⁿ (power of 2), all addresses can be tested without waste by a simple increment operation of the addressing register. If the memory range (that is, the memory capacity of one bank) specified by the in-bank addressing register 42 (the number of bits is n) is 2
^If it is not ⁿ (power of 2), a state in which an address is specified also occurs in an area where no memory actually exists.

More specifically, for example, the memory is composed of four banks (bank 0 to bank 3), and the address range of one bank is 5, which is different from a power of 2, (comprising five memory cells). In the case, the bank designation register 41
Is composed of 2 bits, and the in-bank address designation register 42 is composed of 3 bits. In the test, when the LSB of the bank designation register 41 is connected to the MSB of the in-bank address designation register 42 and these registers are sequentially incremented, the contents of the in-bank address designation register 42 are set to "000" for each bank. "To" 1
Up to "00", the address of the memory cell is specified. However, there is no memory cell in the subsequently output addresses "101" to "111", and the memory cell is composed of five memory cells.
The test is not performed for three cycles per bank.

In testing memory, marching,
In many cases, all addresses are repeatedly accessed by a checker board or the like, and if there is useless access, the overhead of the test time increases, and therefore, there is a problem that the time required for testing the memory is extra.

Therefore, the present invention solves the above-mentioned problem, and in a memory having a bank configuration, even when the address range of the register in the bank is not a power of 2, no useless address is generated, and the speed of the test is increased. It is an object of the present invention to provide a semiconductor memory device capable of performing such operations.

[0021]

In order to achieve the above object, the present invention has a bank configuration in which the address range in a bank is different from a power of two and the number of banks is a power of two (= 2 ^m ). , A bank designating register for designating a bank,
A semiconductor memory device including an in-bank addressing register for designating an address in a bank, a carry output of an MSB of an address calculator in the bank designating register and the in-bank addressing register in accordance with a test operation / normal operation. And a means for connecting / disconnecting the LSB carry input of the address arithmetic unit within the semiconductor memory device from each other.

In the semiconductor memory device of the present invention, preferably, the address range in the bank is different from a power of two,
A semiconductor memory having a bank configuration in which the number of banks is a power of 2 (= 2 ^m ), including a bank designation register (m bits) for designating a bank and an in-bank address designation register for designating an address in the bank In the apparatus, at the time of a test, the contents of the bank designation register are changed with respect to one address in the bank designated by the address designation register in the bank, and the address is sequentially shifted between the banks. You. In this case, during the test, the carry output of the MSB of the address operation unit of the bank designation register and the carry input of the LSB of the address operation unit in the address designation register in the bank are connected to each other. The designation register and the in-bank address designation register operate independently of each other.

In the present invention, preferably,
A mode control signal for designating a test mode / normal operation mode is input, and an AND output of a carry output of the MSB of the bank designation register and the mode control signal is connected to a carry input of an LSB of the address designation register in the bank. It is characterized by the following.

Further, the present invention is characterized in that, at the time of a test, the result of the increment operation or the decrement operation from the bank designation register side is transmitted to the in-bank address designation register.

In addition, the address range in the bank is different from the power of two, and the number of banks is a power of two (= 2 ^m ). A bank designation register for designating a bank, and an in-bank address designation register for designating an address in the bank. During a test, a carry output of the MSB of the bank designation register and a carry input of an LSB in the address designation register for the bank are provided. Are connected to each other, and the result of the increment operation or the decrement operation from the bank designation register side is transmitted to the in-bank address designation register.

[0026]

According to the present invention, unlike the configuration of the conventional addressing register shown in FIG. 4, when the address range of the register in the bank is not a power of two, the simple addressing register is simply tested during the test. Since only the increment operation does not cause extra addressing, the overhead of the conventional addressing register configuration is eliminated, and the test time is reduced by a simple circuit configuration.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention.

In the semiconductor memory device according to this embodiment,
As shown in FIG. 2, the periphery of the memory in the semiconductor integrated circuit is:
Address designation register 21 for giving an address and memory 2
2 is comprised. FIG. 1 is a diagram showing a circuit configuration of the address designation register 21 of FIG.

In FIG. 2, the memory 22 has a bank structure. The address designation register 21 has a bank designation register 11 for designating a bank and an in-bank address designation for designating an address in the bank, as shown in FIG. A register 12 is provided. Each of the bank designation register 11 and the in-bank address designation register 12 includes an incrementer (not shown).

Referring to FIG. 1, bank designation register 11
The carry output of the MSB of the incrementer is input to the AND gate 14 together with the test mode signal 13, and
The output of the ND gate 14 is connected to the carry input of the LSB of the incrementer of the in-bank addressing register 12. The test mode signal 13 is input as a control signal to the bank designation register 11 and the in-bank address designation register 12, respectively.

Next, the operation of this embodiment will be described.

During normal operation, the test mode signal 13 is set to logic "0", the output of the AND gate 14 is set to logic "0", and the MS of the incrementer of the bank designation register 11 is set to "0".
The carry output of B is stored in the bank addressing register 12
Is not transmitted to

For this reason, the bank designation register 11 and the in-bank address designation register 12 are separated from each other, so that during normal operation, the bank designation register 11 and the in-bank address designation register 12 can operate separately. .

At the time of testing the memory, by setting the mode selection signal to logic "1", the bank designation register 11 and the in-bank address designation register 12 each become an incrementer. The carry output of the MSB of the incrementer of the register 11 is connected to the carry input of the LSB of the incrementer of the in-bank addressing register 12.

FIG. 3 for explaining the concept of address arrangement
The operation of this embodiment will be further described with reference to FIG. FIG. 3 shows a memory in which the number of banks = 4 and the address in the bank = 5 (different from a power of 2). In this case, the bank designation register 11 is composed of 2 bits, and the in-bank address designation register 12 is composed of 3 bits.

In normal operation, when the initial value of the bank specifying register 11 is "00" and the initial value of the in-bank address specifying register 12 is "000", the address specified by the address specifying register is 11 in FIG. . In the array of FIG. 3, the numbers in each array element are the numbers indicating the row and column, and more specifically, the bank numbers (1 to 4)
And the address number in the bank (5 from 1).

Referring to FIG. 3, when the in-bank address designation register 12 designates the increment operation, the address moves within the same bank as 11 → 12 → 13 → 14 → 15 → 11. Here, bank designation register 1
When 1 is rewritten to, for example, "10", the address switches from 11 to 31.

In the test, if the initial value of the bank specifying register 11 is "00" and the initial value of the in-bank address specifying register 12 is "000", the address specified by the address specifying register is the same as in the normal operation. It is 11 of 3

Referring to FIG. 1, at the time of test, test mode signal 13 is set to logic "1", so that bank designation register 11 and in-bank address designation register 12 are provided.
Operate as incrementers, and the carry output of the MSB of the incrementer of the bank designation register 11 is conducted through the AND gate 14 and propagated to the carry input of the LSB of the incrementer of the address designation register 12 within the bank.

When the test mode signal 13 is active, the value of the bank designation register 11 after one cycle becomes "01" because the bank designation register 11 performs an increment operation every cycle, and the address designation within the bank is performed. The value of the register 12 is “000”.

Therefore, unlike the normal operation, this cycle indicates the address 21 in FIG. 3 (bank = “01”, address in bank = “000”).

Thereafter, the banks are sequentially moved, and the bank is shifted to the right in FIG. 3. When the address 41 in FIG. 3 is pointed out, the contents of the bank designation register 11 are "11", and the contents of the in-bank address designation register 12 are “000”.

At the next cycle, the carry output is transmitted from the MSB of the bank designation register 11 to the LSB of the in-bank address designation register 12, so that the content of the bank designation register 11 is "00" and the address of the in-bank address is designated. The content of the register 12 is "001", which indicates the address 12 in FIG.

Thereafter, in each cycle, in the increment operation, it moves rightward and downward in FIG. 3 to reach the final address 45. At this time, the bank designation register 11 = “11”, the in-bank address designation register 12 =
It is “100”.

Even when the addressing register has a decrement function, the configuration by the incrementer is as follows.
The memory can be tested in exactly the same manner, except that the address moves in the opposite direction, that is, from the lower right to the upper left in FIG.

That is, the initial value of the bank specifying register 11 is set to "11", the initial value of the in-bank address specifying register 12 is set to "100", and the address specifying registers correspond to the addresses 45, 35, 25 and 15 in FIG. The same address is designated, and in the next cycle, the bank designation register 11
Is "11", a carry (borrow) is output from the MSB of the decrementer of the bank designation register 11, and the initial value of the in-bank address designation register 12 is decremented by one to "011". 44.

In this embodiment, the configuration of the register changes only at the time of the test. In the case of a memory test, it is sufficient that all the addresses can be specified without changing the address from the lower bit side. At
There is no special effect on the test function, and the test time can be reduced.

The configuration of the address designation register in the semiconductor memory device of the present invention can be similarly applied to a test pattern generator for a memory having a bank configuration.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment but includes various embodiments according to the principle of the present invention.

[0051]

The present invention described above, according to the present invention takes a bank configuration, and not the power of the memory area 2 (2 ⁿ⁾ that can be specified by the bank address register, the memory area can be specified by the bank specifying register 2 ^m , the MS of the incrementer of the bank designation register
Since there is means for connecting / disconnecting B and the LSB of the incrementer of the address designation register in the bank, all addresses can be tested by a simple increment / decrement operation without unnecessary access. Therefore, according to the present invention, there is an effect that the time required for the memory test can be reduced without increasing the hardware.

According to the preferred embodiment of the present invention, all addresses can be tested without unnecessary access by simple increment / decrement operations of the addressing register. The effect of shortening the time required for testing the memory can be similarly achieved without increasing the number of hardware.

Further, according to the address generation method of the present invention, the memory area which has a bank structure and can be specified by the in-bank address specifying register is not a power of 2 (2 ⁿ ), but the memory area which can be specified by the bank specifying register. to shorten the testing of the memory is 2 ^m.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration around a memory;

FIG. 3 is an explanatory diagram showing an address arrangement of a bank configuration type memory for explaining the operation of one embodiment of the present invention;

FIG. 4 is a diagram showing a configuration of an address designation register of a conventional bank configuration type memory.

FIG. 5 is a diagram showing a configuration of a conventional semiconductor memory device for reducing a test time.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Bank designation register 12 In-bank address designation register 13 Test mode signal 14 AND gate 21 Address designation register 22 Memory 41 Bank designation register 42 In-bank address designation register 43 Test mode signal 44 AND gate

Claims (6)

(57) [Claims] An address range in a bank is different from a power of two, and the number of banks is set to a power of two (= 2 ^m ). A bank designating register for specifying a bank and an address in the bank are provided. And a carry output of an MSB of an address calculator in the bank designation register and an address calculation in the bank address designation register in accordance with a test operation / normal operation. Vessel LS
A semiconductor memory device comprising means for connecting / disconnecting a carry input of B with each other. 2. A bank configuration in which an address range in a bank is different from a power of 2 and the number of banks is a power of 2 (= 2 ^m ), and a bank designation register (m
Bit) and an in-bank addressing register for designating an address in the bank. In a test operation, one address in the bank specified by the in-bank addressing register is The contents of the bank designating register are changed so that the address is sequentially shifted between the banks , and the memory actually exists.
Configured so that addresses are not generated for areas that do not
The semiconductor memory device which is characterized in that by comprising. 3. In a test operation, the carry output of the MSB of the address operation unit of the bank designation register and the L of the address operation unit in the address designation register in the bank are provided.
3. The semiconductor memory device according to claim 2, wherein a carry input of the SB is connected to each other, and in a normal operation, the bank designation register and the in-bank address designation register operate independently of each other. 4. A mode control signal for designating either a test operation or a normal operation is inputted, and a logical product output of a carry output of the MSB of the bank designation register and the mode control signal is outputted from the address designation register in the bank. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a carry input of an LSB. 5. The test operation according to claim 1, wherein a result of the increment operation or the decrement operation from the bank designation register side is transmitted to the address designation register in the bank. Semiconductor storage device. 6. A method for generating an address of a memory having a bank configuration in which the address range in a bank is different from a power of 2 and the number of banks is a power of 2 (= 2 ^m ). A bank designation register for designating an address in the bank; and a carry output of the MSB of the bank designation register and an LSB in the address designation register for the bank during a test.
And a carry input of the bank designation register are connected to each other, and a result of the increment operation or the decrement operation from the bank designation register side is transmitted to the address designation register in the bank.