JP2922963B2 - Sequence controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller, and more particularly, to a sequence controller suitable for reducing a delay of a logical operation time.

[Related Art] A sequence controller executes a preset logical operation based on the ON / OFF states of a large number of input signals, and outputs a result of the logical operation to a control target as a control signal. The conventional sequence controller has a problem that it takes a long calculation time because the CPU performs a logical operation by software. Therefore, as described in Japanese Patent Application Laid-Open Nos. 62-5407 and 60-46125, a part of the logic function is assembled in a logic array (PLA) to speed up the processing. However, the sequence controller using this logical array is based on software processing,
Since the configuration is such that a part of the processing is performed by hardware, there is still a processing time, which is not suitable for high-speed sequence control.

As another prior art, there is a sequence controller in which a logical operation result is written in a memory IC in advance, and a control signal is read from the memory IC using an input signal as an address signal to reduce a time delay due to the logical operation. . This will be described with reference to FIG.

The sequence controller shown in FIG.
A0 to A15 are input as address signals, and the memory IC 13 is accessed with 65536 kinds of signals decoded by the decoder 4, and the read 8-bit signal is used as an output signal. Output states of all types of the input 16-bit signal are stored in the memory IC 13 in advance, and a signal corresponding to the input signal is read and output. For example, input 0
Assuming that only the number is “1” and the numbers 1 to 15 are “0”,
The uppermost register constituting the memory IC 13 is selected, and the contents of the 8 bits of the register (output 0 = 1, output 1 =
0, output 2 = 1,... Output 7 = 1).

[Problem to be Solved by the Invention] The prior art using the above-described logic array has a problem that it takes a long processing time because the basic processing of the logical operation is software. In the conventional technology using a memory IC, the number of output lines can be doubled by connecting input lines in parallel, but it is necessary to double the memory to increase the number of input lines by one. is there. FIG. 9 shows that the address input line has 16
This is a memory IC with an 8-bit output type and a memory capacity of 512K bits (the current memory IC is the largest of this size)
FIG. 3 is a configuration diagram of a sequence controller using a. With this configuration, each time one input line is added, the memory capacity up to now must be doubled. Therefore, when the number of input lines is set to 20, it is necessary to use 32 memory ICs. In this case, the cost and space are increased, and the complexity of the wiring is added.

An object of the present invention is to provide a sequence controller which can easily cope with a short logical operation time and an increase in the number of input signals.

[Means for Solving the Problems] The above object is to provide a sequence controller which executes a logical operation on a large number of input signals to be operated from the outside and outputs a result of the logical operation as a control signal, and Each of the two operand inputs is one input, and the other one input is a pair of exclusive OR gates, each of which is a first logical function designating bit commonly designated from the outside, and a signal from each of the exclusive OR gates. An AND gate for ANDing the outputs; and an exclusive OR gate for inputting the output from the AND gate and a second logical function designation bit specified from the outside. AND function, NAND function,
2 that can be set arbitrarily to either the OR function or the NOR function
A two-input operation circuit group in which a plurality of input operation circuits are connected in series and a control signal is output from the last-stage two-input operation circuit while using the output of the preceding two-input operation circuit as one input while using the input operation circuit as a basic operation circuit.

b) A first group of registers for designating the first and second logical function designation bits as updatable for each of the two-input operation circuits constituting the two-input operation circuit group.

c) Of the plurality of two-input arithmetic circuits constituting the two-input arithmetic circuit group, two foremost input signals are supplied to the foremost two-input arithmetic circuit, and two-input arithmetic circuits other than the foremost two-input arithmetic circuit are provided. Each has one other input signal as another input,
Or an input signal selection switch group for selectively outputting the output of the preceding two-input arithmetic circuit.

d) A second register group for designating the selected output control signal as updatable for each of the input signal selection switches constituting the input signal selection switch group.

Is achieved by providing a logic operation unit formed in the gate array for each circuit unit of the sequence circuit.

[Operation] Since all functions for executing logical operations are logical circuits having a hardware configuration and no logical operations are performed by software, high-speed processing can be performed. Further, since the circuit groups having the above-described configurations a to d are set in the gate array having a large number of terminals, the number of input lines can be easily increased even if the number of input signals to be operated increases.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram showing an example of a logical operation circuit capable of changing a logical function set in a gate array. This logical operation circuit includes a 2-bit register 1, an AND gate 2,
It consists of three exclusive OR gates 3, 4, and 5. This logical operation circuit becomes four logical circuits shown in FIGS. 4 (a), (b), (c) and (d) according to the data stored in the register 1. That is, when "00" is written to the register 1, it has an AND circuit function and "01"
When "1" is written, it has the function of an AND / NOT (NAND) circuit. When "11" is written, it has the function of an OR circuit.

FIG. 5A is a ladder diagram of one circuit when performing sequence control, and FIG. 5B is a corresponding logic circuit diagram. OR connection of make contacts in parallel 10
The direct connection of the output and the break contact corresponds to the NAND circuit 11, the parallel connection of the output and the make contact corresponds to the OR circuit 12, and the parallel connection of the output and the make contact corresponds to the OR circuit 13. , The parallel connection of the output and the break contact corresponds to the NOR circuit 14, the series connection of the output and the make contact corresponds to the AND circuit 15, and the series connection of the output and the break contact corresponds to the NAND circuit. Corresponds to 16. Therefore, the above-mentioned logic circuits 10 to 16 form a series-connected logic circuit group shown in FIG. 5B by writing the register of the logic operation circuit shown in FIG. 3 by the user as shown in FIG. can do. Then, by selecting one of the contact signals to and inputting it to the logic circuit, a control signal for performing the sequence control shown in the ladder diagram of FIG. 5A can be obtained.

FIG. 6 is a diagram schematically showing a logical operation circuit capable of selecting a logical function, a signal selection switch to be input to each logical operation circuit, and a unit for designating a selection signal to each signal selection switch. By writing data as shown in each of the two-bit registers of the seven logical operation circuits, the logical circuits 10 to 16 shown in FIG. 5B are assembled, and the switch 17 for selecting a signal to be input to each logical circuit is set. Provided and each switch 17
This is configured by providing a means for designating a signal to be selected, for example, a register 18. These logical operation circuits, signal selection switches, and selection signal designating means are created in the gate array.

In the above description, only the required number of logic circuits are configured. However, in practice, a predetermined number of logic operation circuits are created, and only the required number of logic operation circuits are used. However, in such a case, since the unnecessary logic circuit cannot be physically removed, the logic circuit needs to be in a data-through state so that the input signal is output as it is. Therefore, in this embodiment, as shown in FIG. 7, the 0th input of the switch 17 is input to the switch 17 corresponding to the next-stage logic circuit (which is an AND circuit), and the 0th input is Is selected, the 0th input is input to the AND circuit. As a result, both inputs of the AND circuit are output signals of the previous stage, and this signal is directly used as an output signal of the AND circuit.

Next, a sequence controller configured using the gate array created according to the above-described principle will be described.

FIG. 2 is an overall configuration diagram of the sequence controller. The sequence controller 19 includes a logical operation unit 20 configured by a gate array, a control circuit 21 that performs the register write control of the logical operation unit 20 according to a user designation from an input device 24, and takes in an input signal and performs level conversion. An input circuit 22 for converting the control input signal into an optical signal and then converting it into an electric signal again to insulate and output the signal to the logical operation unit 20; And an output circuit 23 that performs level conversion and outputs a control signal to a control target. In the sequence controller 19, after the user specifies the logic circuit, the control circuit 21 constituted by a microcomputer or the like does not participate in the logic operation itself, and performs all the logic operations in the hardware logic circuit. It has become.

FIG. 1 is a diagram showing a detailed configuration of one circuit of a ladder diagram of the logical operation unit 20 shown in FIG.

The logical operation unit 20 in this embodiment is cascaded with eight stages of logical operation circuits capable of changing the logical function as one circuit of a ladder diagram. The reason why the number of stages is eight is that one circuit has eight stages or less in many sequence controls. If nine or more stages are required, continuous logic operations can be performed by using the output signal of the eighth stage as the first-stage input signal of a group of eight-stage logic operation circuits for another circuit.

Each 2-bit register 32 of the eight-stage logic operation circuit 31 is addressed, and the control circuit writes data to the corresponding register 31 according to a user input.
Set each logical function. The input terminals of the switches 33 are connected to the first to nth input signal lines.
A signal selection register 34 provided in each of the switches 33 is also addressed, and the control circuit writes data to the corresponding register 34 in accordance with a user input, and specifies an input signal to each logical operation circuit 31.

Outputs a _{1 to} am of the final stage logic operation circuits of each of the eight stages of logic operation circuits 31 are input to output selection switches 35, respectively. The output is the output signal of the logical operation unit 20.
Each register 36 is addressed, and the control circuit writes data to the corresponding register 36 according to a user input.

Normally, the gate array has a standard number of pins of about 64 pins, and the number of gates exceeds 10,000 gates.
Therefore, when wiring is performed to form the logic circuit of FIG. 1 using this gate array, the number of logic circuits that can be created is not practically limited. For example, a case where a gate array having 20 input signal lines and 16 output signal lines is used for a sequence controller as shown in FIG. 8 and a case where a memory IC is used as shown in FIG. As shown in FIG. 9, when the same number of signal lines is used using a memory IC, the gate array requires only 1/16 of the space and 1/10 of the price.
Will be done. Further, according to the above-described embodiment, a desired logic function can be set by rewriting the contents of each register, so that the circuit can be changed even during operation.

[Effects of the Invention] According to the present invention, a gate array is used, and a logic circuit function can be rewritten by a user, so that the arithmetic processing time is high and a large number of input / output lines can be handled. It is possible to obtain a low-priced small-sized sequence controller capable of performing the following.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of a gate array according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a sequence controller, FIG.
The figure is a configuration diagram of an example of a logic operation circuit capable of changing the logic function,
FIGS. 4 (a), (b), (c) and (d) are explanatory diagrams when a logical function is designated by the logical operation circuit shown in FIG. 3, and FIG.
6A and 6B are diagrams showing a configuration of one ladder circuit and a corresponding logic circuit diagram, FIG. 6 is an explanatory diagram when a sequence circuit is incorporated in a gate array, and FIG. 7 is an output of the logic circuit. FIG. 8 and FIG. 9 are explanatory diagrams showing a comparison between a case using a gate array and a conventional example using a memory IC, and FIG. 10 is an explanatory diagram of a memory IC. is there. 1,32 ... 2-bit register, 2 ... AND gate, 3,4,5 ...
Exclusive OR gate, 19: sequence controller, 20: logical operation unit, 33: input signal selection switch, 34
... Signal selection register.

Claims (1)

(57) [Claims] 1. A sequence controller for executing a logical operation on a large number of externally operated input signals and outputting a result of the logical operation as a control signal. Two exclusive OR gates, each of which has a first logical function designation bit commonly designated from the outside as an input, and an AND gate for ANDing outputs from the exclusive OR gates , An exclusive OR gate for inputting an output from the AND gate and a second logical function designation bit specified from the outside, and the overall logical function is an AND function, a NAND function,
2 that can be set arbitrarily to either the OR function or the NOR function
A two-input operation circuit group in which a plurality of input operation circuits are connected in series and a control signal is output from the last-stage two-input operation circuit while using the output of the preceding two-input operation circuit as one input while using the input operation circuit as a basic operation circuit. b) A first group of registers for designating the first and second logical function designation bits as updatable for each of the two-input operation circuits constituting the two-input operation circuit group. c) Of the plurality of two-input arithmetic circuits constituting the two-input arithmetic circuit group, two foremost input signals are supplied to the foremost two-input arithmetic circuit, and two-input arithmetic circuits other than the foremost two-input arithmetic circuit are provided. Each has one other input signal as another input,
Or an input signal selection switch group for selectively outputting the output of the preceding two-input arithmetic circuit. d) A second register group for designating the selected output control signal as updatable for each of the input signal selection switches constituting the input signal selection switch group. A sequence controller comprising: a logic operation unit in which the constituent elements are created in the gate array for each circuit unit of the sequence circuit.