JP2613963B2 - Data input / output device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output device, and more particularly, to a data input / output device for simultaneously accessing a plurality of or continuous addresses to input / output data.

[Conventional technology]

Conventionally, this type of data input / output device has been used as an example of a second device.
As shown in the figure, lower-order M (in this example, M = 2, hereinafter described as M = 2) bits A ₀ , A
₁ and the upper bits (A ₂ to A ₂₎ other than the lower M bits of the address signal for each row.
A _N ) A plurality of data registers R arranged in a matrix with a row address specified by _N ), each of which holds input data and outputs the held data.
₁₀ to R _13, R ₂₀ and to R _23, a data input and output lines DL ₀ through DL ₃ provided in common therein to the data register of the same individual address of each row, the upper bits of the input address signal
A row address selection circuit 1 _A for selecting one of the row addresses A ₂ to A _N by the data register _{R 10 ~R 13, R 20 ~R} 23, a row address selected by the row address selection circuit 1 _A lower M bits of each data register (e.g., R ₁₀ to R ₁₃₎ and the transfer gate T ₃₁ through T ₃₈ for connecting the input and output terminals of the data input and output line DL ₀ through DL ₃ corresponding respectively, the input address signal Start address decoder 2 _A that specifies the start address of data input / output for individual address by A ₀ and A ₁
When a 2 ^M = 4 bits of data input and output terminals TM ₀ to Tm ₂ provided corresponding to each individual address, in accordance with the start address designated by the start address decoders 2 _A, individual address corresponding to the start address Data output lines (DL _{0 to} DL ₃
One) to the bottom of the data input-output terminal TM _0, data input and output terminals of the sequential upper to the individual address order data input and output lines of the individual address in the upper side of the start address (TM ₁ to Tm ₃ of ) to, has been a structure and a switching circuit 3 _a that connects the data input lines of the individual address sequentially more data input and output terminals of the upper to the individual address order on the lower side of the start address.

[Problems to be solved by the invention]

The conventional data input-output device described above, the row address selection circuit one row address by 1 _A is selected, the data register of the selected row address _{(R 10 ~R 13, R 20} ~R 23)
Since the input and output terminals has a configuration that connects to the corresponding one data input and output lines of each present DL ₀ through DL _3, when the start address for inputting and outputting data other than the lowest individual address (e.g. " 10 ") is performed to input and output data by connecting the output terminal of the data register of the row address selected (e.g. R _12, R ₁₃₎ to the corresponding data input and output lines (e.g. DL _2, DL ₃₎ After switching the input address signal,
Select the row address of address higher, data register (R _20, R ₂₁₎ must perform the input and output of data by connecting to the data input and output lines (DL _0, DL _1), the time for input and output of data However, there was a drawback that it took.

An object of the present invention is to enable input / output of data corresponding to one row (the number of individual addresses) by one address signal input even when the start address is other than the lowest order of the individual addresses,
An object of the present invention is to provide a data input / output device capable of shortening data input / output time.

[Means for solving the problem]

The data input / output device according to the present invention comprises: an individual address specified by the lower M bits of an address signal in a row direction; and a row address specified by an upper bit other than the lower M bits of the address signal for each row. And a plurality of data registers for holding input data and outputting the held data, and a first register commonly provided for the data register of the same individual address in each row. And a second data input / output line, a row address selection circuit for selecting one of the row addresses of the data register according to the upper bit of the input address signal, and a row address selected by the row address selection circuit And the input / output terminals of each data register are connected to corresponding first data input / output lines, respectively.
A plurality of transfer gates for connecting input / output terminals of each data output register of a row address one address higher than the selected row address to a corresponding second data input / output line; A start address decoder for designating a start address of data input / output with respect to the individual address by a side M bit, a plurality of input / output terminals provided corresponding to the individual addresses,
According to the start address specified by the start address decoder, the first data input / output line of the individual address corresponding to the start address is connected to the lowest data input / output terminal, and the individual address on the upper side of the start address is A first data input / output line is sequentially connected to the data input / output terminal in the order of the individual address, and a second data input / output line of an individual address located below the start address is sequentially connected to the input / output terminal in the order of the individual address. A switching circuit connected to the output terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the lower M bits of the address signal in the row direction (M = 2 in this embodiment, hereinafter described as M = 2) bits
An individual address designated by A ₀ , A ₁ and an upper bit A ₂ other than the lower M bits of the address signal for each row.
To a plurality of data registers R arranged in a matrix with row addresses specified by A _N for holding input data and outputting the held data, respectively.
₁₀ and ~R _13, R ₂₀ ~R _23, each row of the same individual address of the data register _{(R 10, R 20, R} 11, R 21 , etc.) to the first and second data input that respectively provided in common Output line (DL ₀₁ , DL _{02
~DL 21, DL 22, DL 31} , DL 32 data register R ₁₀ is not required), the most significant bits A ₂ to A _N of the input address signal
To R ₁₃ , R _{20 to} R ₂₃ , and each data register (for example, R ₁₀ to R ₁₀ ) of the row address selected by the row address selection circuit 1.
R ₁₃ , described below in this example), are connected to the corresponding first data input / output lines DL ₀₁ , DL ₁₁ , DL ₂₁ , DL _{31 respectively, and} are connected by one address higher than the selected row address. a plurality of transfer gates T ₁ through T ₁₄ for connecting the input and output terminals of each data register (R ₂₀ ~R ₂₃₎ of the row address to a second data input and output line DL _02, DL _12, DL ₂₂ corresponding respectively, A start address decoder 2 for designating a start address of data input / output with respect to an individual address by the lower M bits A ₀ and A ₁ of the input address signal, and a plurality of start addresses provided in correspondence with each individual address (in this embodiment, 2 ^M = 2 ^M = 4) input / output terminals TM _{0 to} TM ₃ and a plurality of transfer gates T _{15 to} T _30, and a start address specified by the start address decoder 2 (for example, “10”; Address). Less the corresponding first data input and output lines of the individual address (DL ₂₁₎ to the lowest data input terminal (DT _0), a first individual address on the upper side of the start address ( "11") Data input / output line (D
L ₃₁ ) are sequentially transferred to the upper data input / output terminal (TM ₁ ) in the order of the individual addresses, and the second data input / output lines (DL ₁₂ ) of the individual addresses (“01”, “00”) located on the lower side of the start address. , DL
₀₂₎ sequentially higher input and output terminals to the individual address order (TM _3, TM
₂ ) and a switching circuit 3 connected thereto.

 Next, the operation of this embodiment will be described.

The last three digits of the individual address of the data register _{R 10 ~R 13, R 20 ~R} 23 "000" ~ "011", and "100" - "111".

Now, it is assumed that the last three digits “A ₂ , A ₁ , A ₀ ” of the input address signal are “010”. Then, the row address selection circuit 1
Data row address register R ₁₀ to R ₁₃ is selected, the transfer gate _{T 2, T 4, T 6} , the data register R ₁₀ to R ₁₃ input and output terminals of data output lines DL ₀₁ of the T ₇ by, DL ₁₁ , DL
₂₁ and DL ₃₁ , respectively, and at the same time, by transfer gates T ₈ , T ₁₀ and T ₁₂ , the data registers R _{20 to} R ₂₂ of the row address higher by one address (the individual addresses of the lower three digits, “ Input / output terminals of 100 "to" 110 ") are data input / output lines
DL ₀₂ , DL ₁₂ and DL ₂₂ are respectively connected.

The start address decoder 2 determines the lower M of the address signal.
(2) bits A _0, specify the start address "10" of the input and output for the individual address according A _1, the start address "1
0 "corresponding to the transfer gates T ₁₇ , T ₂₁ ,
T ₂₅ and T ₂₉ are turned on, and the data input / output line DL ₂₁ corresponding to the start address “10” is connected to the lowest data input terminal TM.
₀ , the data input / output line DL ₃₁ of the upper individual address “11” of the start address “10” is connected to the upper data input / output terminal TM ₁ and the lower individual address “10” of the start address “10”. The data input / output lines DL ₀₂ and DL ₁₂ of “00” and “01” are sequentially connected to the higher-order data input / output terminals TM ₂ and TM ₃ in the order of individual addresses.

Therefore, in this case, four consecutive data in the data registers R ₁₂ , R ₁₃ , R ₂₀ , and R ₂₁ are input / output in parallel from the data input / output terminals TM _{0 to} TM _{3 at a} time by one address signal input. Is done. In such a case, in the conventional example, input / output cannot be performed unless the address signal is input twice, and thus the data input / output speed is doubled in the present invention.

〔The invention's effect〕

As described above, according to the present invention, the first and second data input / output lines are provided in common for the same individual address in each row (however, only the first may be provided for the uppermost individual address), and the address signal may be provided. Is connected to the first data input / output line, the data register of one address higher is connected to the second data input / output line, and specified by the lower bit of the address signal. The first data input / output line of the individual address corresponding to the start address to be connected is set to the lowest data input / output terminal, and the first data input / output line of the individual address higher to the start address is set to the upper data input / output terminal. The second data input / output line of the individual address on the lower side of the start address is sequentially connected to the data input / output terminal on the upper side in order of the individual address. Even when the start address is not the lowest order of the individual addresses, the data of the number of the individual addresses can be input / output in parallel at one time by the input of the address signal at one time, so that the data input / output time can be shortened. is there.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional data input / output device. 1,1 _A: Row address selection circuit, 2,2 _A: Start address decoder, 3,3 _A: Switching circuit, DL _{0 to} DL ₃ , DL ₀₁ , DL _{02 to} D
_{L 21, DL 22, DL 31} ...... data input and output lines, T ₁ ~T ₃₈ ...... transfer gates, TM ₀ ~TM ₃ ...... data input-output terminal.

Claims (1)

(57) [Claims] 1. A matrix comprising, in a row direction, an individual address specified by lower M bits of an address signal and a row address specified by upper bits other than the lower M bits of the address signal for each row. Arrayed,
A plurality of data registers for holding input data and outputting the held data, and first and second data input / outputs provided in common with the data registers of the same individual address in each row, respectively. A line, a row address selection circuit for selecting one of the row addresses of the data register according to the upper bits of the input address signal, and input / output of each data register of the row address selected by the row address selection circuit The respective ends are connected to the corresponding first data input / output lines, and the input / output ends of the data registers of the row addresses one address higher than the selected row address are connected to the corresponding second data input / output lines. A plurality of transfer gates, and the lower M bits of the input address signal, the data corresponding to the individual address. A start address decoder for designating an output start address, a plurality of input / output terminals provided corresponding to the individual addresses, and an individual address corresponding to the start address according to the start address designated by the start address decoder The first data input / output line is connected to the lowermost data input / output terminal, and the first data input / output line of the individual address on the upper side of the start address is sequentially set to the higher order of the individual address. A data input / output device, further comprising a switching circuit for sequentially connecting a second data input / output line of an individual address on the lower side of the start address to the input / output terminal in a higher order in the order of the individual address.