JPS60182587A - Memory control circuit - Google Patents

Abstract

PURPOSE:To use effectively an address space of a memory by connecting plural memories of small units and constituting a titled circuit in such a way that a row address of each memory can be specified by a counter. CONSTITUTION:A code signal CS1 is latched by a latch circuit 22. A two-bit counter 23 is cleared by a start pulse P1, a clock CK1 is counted from the initial condition, and a nine-bit shift register 25 is loaded. A carrier output from the counter 23 is utilized as a clock and memories M1-M9 are sequentially set to the readout condition. Data of one character is outputted to a data bus BU3 by such data reading. In order to read out data of one character, the code signal CS1 specifies addresses in the entire memories M1-M9, a row address of each memory is automatically renewed by the register 25 and the counter 23 in sequence, thereby obtaining data of 9X4 bits =36 bits. Thus an address space in a memory can be used effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory control circuit used in a character data generator or the like.

[Technical background of the invention and its problems]

A system is required that sends a code signal using a telephone line, and on the receiving side, discriminates the code signal, generates address data, and reads or writes data to that address. In this system, a display control circuit is provided which displays pattern data read out from the character memory in accordance with the address data on all television receivers.

As shown in Figure 1, the address array for one character in the character memory 11 is arranged in 1 row x j columns.

If the number of rows (n) is a power of 2 (I=2k), the signal is used to obtain address data.

It is set as follows. That is, by adding additional code 13 of the lower KK bits of address data No. 2 and changing this additional code J3 from "00...0 to 11...11", a row address can be specified. The address code 12 is used as data indicating the address area of each character. In this way, if the number of rows in the address area for one character is l=n=2K, the entire data area for one character can be effectively used.

However, if the address arrangement of the data area for one character is I to 2 as shown in Figure 2, an additional bit code 13 is added to the lower part of the address code 12 as described above. Just by doing IJI, the character,
(There will be a portion 14 that will not be used at all. Figure 2 shows.

2''<n<2, that is, the number of rows in the data area for one character is l - n.

In this way, in the case of 1 (2), depending on the value of the number of rows, there is a problem that the amount of unused memory becomes very large.

[Purpose of the invention]

The present invention has been developed in view of the above circumstances, and an object of the present invention is to provide a memory control circuit that has a simple configuration and can effectively utilize the address space of a memory.

[A essential point of the invention]

According to this invention, n pieces of data are n = m
For example, as shown in Figure 3, 1m memories (Mz-M9) are connected in parallel, and the latch circuit 2
Note the output of 2! I (Ml to M9) as a whole, while each memo 9 (Mj
-Ml9)f: The sequential read mode is specified, and the row address of each memory is specified by the output VC of the kakunta 23. Even when n=2, memory usage efficiency can be improved.

[Embodiments of the invention]

Hereinafter, an example of "this address" will be explained with reference to the drawings.

Figure 3 shows an embodiment of the present invention, where (BUD) is a bus to which the code signal (C10) is input, and launch circuit 2
Connected to 2 is pregnant. The output pin and address data of this latch circuit 22 are as follows.

Furthermore, additional data from, for example, the 2-bit kakunta 23 is added to the first bit. This address data bus (BU2) is connected 8 to the address designation line of the character memory 24. (BU3) is a character data bus.

In the case of the present invention, pattern data consisting of one character '; Therefore, in order to read out all the pattern data for one character, Memo!J(?vIJ)~(Nl9) <The address data of the specified program.

It is good to create address data for sequentially reading out four pieces of data in each memory. The signal for designating the memories (Mz) to (M9) as a whole (blockwise), which store data for one character, is the code signal (C8J) from the bus (B[J)'). Then 1 individual note 9 (R4
The signal for sequentially specifying 1) to (M 9 )f is from the divided memo 9 specifying circuit by the shift register 25. Next, in each memory, specify four rows in order (No. 3 is.

Obtained from Kawanta 23.

Now, when a code signal (C8J) that specifies the memory (Ml-M9) as a whole is given, and a start pulse (P)) is given to the terminal 26, the code (B code (C8)) is given as follows.
Latte circuit 22 is closed. In addition, the 2-bit counter 23 is cleared by the start pulse (PJ'), and the tarok (CK2)'Ik count starts from the initial state. Furthermore, the 9-bit shift register y2
srd, loaded by start pulse (PJ);
The carry output from the 2-bit counter 23 is used as a clock. In this state, the shift register 25 first sets the memory (Ml) to the output state. Next, the content of 2-bit kakunta 23 is “oon, l'-ox J
.

"lo j, [llJ", so the memory (M7
) are output to data bus BU3.

Next, when there is a carry output from the 2-bit Kawanta 23,
Is shift register 25 a memory CM this time? ) k Set to read state. As a result, four rows of data in the memory (Mz) can be sequentially addressed and read out by the output of the 2-bit counter 23. When there is a carry output from the 2-bit counter 23, the shift register 25 sets the next memory (M, :l)'&read state. This kind of data reading is possible with Memo 9C.
If H2)'i is executed, data for one character will be output to the data bus CBU3).

Therefore, to read data for one character, the code signal (C8J) should be data that collectively addresses the memories (MJ to M9), and the row address of each memory is automatically set in the shift register. 25.2 bits are updated one after another by the kakunta 23. As a result, for example, 36 bytes (9 pieces x 4 bytes) of data can be obtained.

The above can be expressed using a general formula as follows. In other words, if you want to obtain n pieces of data for the input of one code signal, and n=mX2d (m is an unnumbered number), set m memories that exist in parallel and access those memories. As a blank address, all l-bit binary counter outputs are added as the lower bits of the code signal, and the carry output of this binary counter is used as a tarok of the shift register for specifying memo 9 of the fm pit, and m pieces exist in parallel. This method reads data sequentially from memory.

FIG. 4 shows another embodiment of the present invention, in which a vVc% 6-bit counter 31 and a decoder 32 are used in place of the 12-bit counter 23 and shift register 25.

For the clear input terminal of 6-bit kakunta 3.

A start pulse (PJ) is input via the terminal 26. This start pulse (P) is also used as a code signal latch pulse for the latte circuit 22.

Now, memory (Ivlz~M9) a? When a code signal (C8J) that specifies the entire code is given and a start pulse (PJ) is given to the terminal 26, the code signal (CTJ) is given.
) is ratified by the ratte circuit 22. Furthermore, the 6-bit counter 31 is cleared by the start pulse (P).

Next, a clock pulse is applied to the clock terminal 33 of the 6-bit counter 31 as a read timing signal. As a result, the count of the 6-bit counter 31 advances. The upper 4 bits of the 6-pit kakunta 31 are sent to the decoder 32, and the lower 2 bits are sent to the latch circuit 2.
It can be added to the lower digits as an additional bit of the output of step 2.

Figure 5 shows the upper 4 bits 3Z of the 6-bit Kawanta 31.
A shows how the lower two bits 31B change and the corresponding 36 data addresses 31Cf are shown. The decoded output to the upper 4 bits 31 is the block (m7 to m
As shown in 9), note! J (Mz-R1?) can be set to read mode one by one. Further, the lower two bits 31B can specify the row address (four rows) of each memory by changing from l'-00j to "llJ."

〔Effect of the invention〕

According to the present invention described above, the entire memory area can be used effectively without wasting it by the simple configuration of the rIA.

According to traditional memory control circuit.

The number of slave addresses is 0 and 2, that is, 2"< n < 2
, the unused area becomes thicker depending on the value of The address is configured so that it can be automatically specified by line kakuntas. Also, the number of 1-line addresses is n
== Even if it is 2, the memory area can be effectively reused by 1.

[Brief explanation of the drawing]

FIGS. 1 and 2 are an address explanatory diagram for explaining the addressing method of a conventional memory control circuit, and FIG.
4 is an explanatory diagram of the configuration showing one embodiment of the present invention, FIG. 4 is an explanatory diagram of the configuration of another embodiment of the invention, and FIG. 5 is an explanatory diagram of the address shown in the explanation of the operation of the circuit in FIG. 4. be. 22...Latch circuit, 23...2 bit kakunta. 24...Character memory, 25...Soft register, 31...6 pittokwanta, 32...Decoder. Ml-Ml...Memory. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] (υ n data of which one is an arbitrary bit is n =
m x 21, there are m memories with data buses connected in parallel, i1 blocks, and one code (a latch circuit that addresses all of the m memories based on the input of g). , a counter for specifying the row address of each memory by adding the l-bit additional code to the least significant bit of the output address data of the latch circuit, and a counter for specifying the row address of each memory; A memory control circuit characterized in that it is equipped with means for switching the m memories to a sequential read mode. 2. The memory control circuit according to claim 1, wherein the switching means is a shift register for the m-bit output, which is clocked by the carry output of the gi-bit counter. A counter having a number of bits larger than the l bits is used, and the output of the next bit from the least significant bit is used as the additional code, and the remaining p bits are input to a decoder that decodes it, 2. A memory control circuit according to claim 1, wherein said decoder is configured as means for switching said m memories into a sequential read mode.