SU1005065A1 - Associative matrix processor - Google Patents

Description

The invention relates to computing and can be used for parallel processing of information.

An associative matrix processor is known, which contains three associative memory matrices made on special associative storage elements, a local control device, an external control device and input devices with polling registers, write and read registers 3

However, at present, such processors are not practical applications because of the high cost of special elements, the bulkiness of the associative memory, and hence the entire processor, and the high power consumption.

An associative matrix processor is also known, which contains a control device, a parallel input / output unit, an associative matrix module containing a memory matrix, processing elements for each memory line, a permutation network, a multiplexer — a switching unit C23.

The transformation of information takes place in the processing elements by

J sequential removal of the bit cut from the matrix. The sampling of the bit slice is performed using a complex permutation network constituting 80% of the cost of the memory array.

The disadvantage of this processor is the need to transfer information in the memory recording mode,

10 and in the sampling mode through a complex permutation network, which leads to a significant decrease in the speed of the process, as well as the reliability of the processor as a whole, since the interrupted 15 network consists of a large number of elements.

The purpose of the invention is to reduce the amount of hardware and increase processor performance.

20

This goal is achieved by the fact that an associative matrix processor containing memory blocks, arithmetic logic units according to the number of memory blocks, a control unit, input and output switch blocks, the outputs of the memory blocks are connected to information inputs of the corresponding arithmetic logic blocks and input information inputs

30 blocks of switches, the first and second blocks of buffer memory are introduced and. two groups of switches, the total number of which is equal to the number of memory blocks, the first and second information inputs of the buffer memory blocks are connected respectively to the information input of the processor and the output of the input switch block, the first information outputs of the first and second blocks of the buffer percentage are connected respectively to the first and the second informational inputs of the output block of switches, the output of which is connected to the information output of the processor, the second information outputs of the first and second blocks of the buffer The first memory inputs are connected to the first information inputs of the switches of the first and second groups, the second information inputs of the switches are connected to the information outputs of the corresponding arithmetic logic units, and the outputs of these switches are connected to the control inputs of the corresponding memory blocks, the first input and the transfer output of each arithmetic -logical block connected respectively to the second output and the transfer input of the neighboring arithmetic logic unit and the first, second, third, fourth, fifth, schest second and seventh outputs of the control unit are respectively connected with the control inputs of the block of switches, the first and second blocks of buffer memory, and switches the first i.vtoroy groups, the address inputs of memory units and the control inputs of the arithmetic-logic unit and the output unit switches. In this case, the control unit contains a sync signal generator, a register “(ascend, a memory of control commands, a memory of micro-instructions, a register of control commands, a register of micro-instructions, two. Groups of AND elements, a group of OR elements, a decoder, and three elements AND, and the second outputs of the state register are connected respectively to the first inputs of the elements of the first group and the clock generator input, x. the first inputs of the elements of the second group are connected to the first output of the register of control commands, the second output of which is connected to input the microinstructions memory house, the second inputs of the elements of the first and second groups are connected respectively to the first and second outputs of the clock generator, the third, fourth and fifth outputs of which are connected respectively to the control inputs of the register of control commands, the register of microcommands and the first inputs of the first, the second and third elements AND, the first and second inputs of the OR elements of the group are connected to the outputs of the AND elements of the first and second groups, respectively, and their output is connected to the memory input of control commands, the memory outputs rokomand and memory of control commands are connected to information inputs of the register of microinstructions and the register of control commands, respectively, the first, second, third, fourth, fifth, sixth and seventh outputs of the register of microinstructions are connected to the first output of the block, the second inputs of the first and The second element And, the fourth output of the block, the input of the decoder, the second input of the third element And and the seventh output of the block, and the outputs of the first, second, and third elements And And are connected respectively to the second, third and sixth output dam block. Figure 1 shows a structural diagram of an associative matrix processor; Fig. 2 shows functional diagrams of the buffer memory blocks and switches; FIG. 3 shows the partitioning of switches into odd and even groups in order to connect them to the registers of the buffer memory blocks; Fig. 4 is a schematic diagram of the output switch unit; Fig. 5 is a functional block diagram of the control unit; in FIG. the basic scheme of the arithmetic logic unit; figure 7 - the truth table of the arithmetic logic unit. The processor contains (Fig. 1) a memory matrix consisting of km of blocks (random access memory) with random access, arithmetic logic units 2-2, control block 3, switch input block 4, switch output block 5, first and second blocks 6 and 7 of the buffer memory, switches 8 -. The processor input 9, which also has bits, is connected to the parallel inputs of blocks 6 and 7 of the buffer memory, the parallel outputs of which are connected to the corresponding input block 5 of switches, and the serial outputs to switches B - 8, grouped in a certain way into odd and even groups of switchboards in each group (Fig. 3), successive inputs of blocks 6 and 7 are connected to the outputs of the input block 4 of switches. The output of each switch 8 is connected to the information input of the corresponding memory block 1, the output of which is connected to the corresponding block 2 and information input of the switch block 4. The first vertical inputs and outputs of each block 2 are connected respectively to the second vertical output and the input of the previous block 2, and the first vertical input and output of block 2 are connected to the second vertical output and input of the block 2yy, respectively. The horizontal output of the first and last blocks 2 are connected respectively to one of

inputs of the first and subsequent switches 8. The control inputs of all the processor units are connected to the outputs 10-16 of the control unit 3. The output 17 of the output unit 5 of the switches is with the output of the processor.

Each of blocks 6 and 7 of the buffer memory consists (Fig. 2) of registers 6 - br 7 - 7 and shift, respectively, the number and size of which are determined by the width of the input 9 of the 10 processor. At the same time, the parallel inputs of the registers 6-6i and 7-7c are combined and are the parallel inputs 9c-9i of the processor.

Switches 6 - Qy (FIG. 2) contain an element NOT 18, two elements AND 19 and 0, an element OR 21, whose inputs are connected to the outputs of elements 19 and 20. The second inputs of elements 19 of all switches 8 are connected to the output 13 bpo-jq

There are 3 controls to which the first inputs of the elements of 20 all switches are also connected via elements 18, the first inputs of elements 19 of all the first and subsequent switches of the odd-25 groups, for example, 8-8ts, Bi. etc., combined and connected to the serial output of the first and, respectively. subsequent registers cd:; wig unit 6, for example, the inputs | g switches in, 82.p - “- etc. combined and connected to the serial output of register 64. Similarly, the first inputs of the elements of the 19. switches of even groups are connected to the registers of the shift of block 7, for example, the inputs of switches 8 „4 | hz ii85I | etc., they are connected and connected to the serial output of the register 7. The second input of the element 20 of each switch B is connected to the horizontal output of the corresponding block 2.

The output block 5 of the switches (figure 4) contains two groups of switches 2 2, - 22 y, and - 23, and groups of logic elements, each of which consists of two elements AND 24 and 25 and one element OR 26, and the element NOT 27. At the same time, the informational inputs of the nefiBoa switch groups 22 —– 22y, through the informational information buses 28–23c, are connected to the parallel outputs of the corresponding registers b — 6ts of block 6, and the informational inputs of the second group of switches 23, -. 23 55 through the input information bus 29 - 29 "connected to the parallel outputs with The corresponding registers 1l - 1p of block 7. The outputs of the first “second group of switches are connected 60 respectively to the first inputs of the first and second elements AND 24 and 25 sqex groups of logical elements, in which the second BXOJ9J of the first elements AND 24 are combined and connected to the output element j

that NOT 27, and the second inputs of the second elements AND 25, as well as the input of the element NOT 27 are combined and connected to the output of the control output 16 of block 3. The control inputs of all the switches are 22and 23-23 and are connected and connected to the control outputs 16 to 16, where. The outputs of the elements 24 and 25 of all groups are connected to the inputs of the elements 26, the outputs of which are the outputs 17 17u of unit 5.

The control unit 3 (FIG. 5) consists of a firmware control unit 30, a clock signal generator 31, and a status register 32, the firmware control node 3 contains a memory of control commands 33, a memory of micro commands 34, a control command register 35, register 36 microinstructions, groups of logic elements, each of which consists of two elements AND 37 and 38 and one element OR 39, and a decoder 40. At the same time, the inputs of the elements OR 39 are connected to the outputs of the elements AND 37 and 38, and the outputs to the address inputs. memory 33, the output of which; the swarm is connected / to the information These inputs are register 35. The first group of outputs of this register is connected to the address inputs of memory 34, and the second to the first inputs of the second elements 38 of all groups. The first inputs of all elements 37 are connected to the first group of outputs of the register 32, and the second group of its outputs is connected to the input of the generator 31, to the four outputs of which, respectively, are connected the second inputs of the elements 37 and 38 of all groups and the control inputs of the registers 35 and 36. Information inputs the register 36 is connected to the output of pg. 34. The fifth output group of the register 36 is connected to the input of the decoder 40. All outputs of the register 36, except for the fifth output group and the last output, the outputs of the decoder 40, and also the fifth output of the generator 31 odes 10 - 16, the control unit 3.

The arithmetic logic unit 2 (Fig. 6); 6 holds the elements AND 41.42 and 43, the element OR 44, triggers 45.46

Claims (2)

and 47, arithmetic logic module 48, horizontal input and output buses 49 and 50. Element 44 Bxojcuii is connected to the outputs of elements 41, 42 and 43, the first inputs of which are connected to the vertical input bus 51, the horizontal input bus 49 and the vertical input bus bus 52, and the second inputs - respectively to the outputs 15h 152. and block 3 of the control. Module 48 has inputs 53 - 61 and outputs 62 and 63. Inputs 53, 55 and 57 of the module; l 48 are combined and connected to the output 154 of the block 3, and the combined inputs 54, 56 and 58 are connected to the output of the 155-block 3. The input 59 of the module 48 is unified with the input of the trigger 45 and connected to the output of the element 44, the input 60 to the output of the trigger 45 and input 61 to the output of trigger 47. The inputs of the trigger 46 and 47, respectively, are connected to outputs 62 and 63 of module 48, control inputs 64 - 68 of which are connected respectively to outputs 15 - block 3. Outputs 15 -15 /), block 3 are connected respectively to the control inputs of the flip-flops 45, 46 and 47. You move the flip-flop 46 is connected to the first and second vertical you odnym tires and to bus unit 50 2. The operation of the associative matrix processor is as follows. The input-and-bit words to the memory matrix are made through two blocks 6 and 7, and first from the control: output 11 of block 3 to all the registers of block 6 a code combination is supplied, which adjusts them to the parallel reception mode. During the first AND cycles, the AND-bit information B of AND registers 6x is sequentially entered (-6 ,. At this time, and block 3, the code combination registers at output 12 and receives the code combination during the first. And cycles keep these registers in After the ikits expire, the control signals from outputs 11 and 12 of the block transfer the registers of block 6 to the sequential shift mode, and the registers of block 7 to parallel mode, hold down. This is how the filling of the registers of block 6 and reading from the registers of block 7 alternate. and then read from block ka 6 and filling in block 7. Information read from the registers of block 6 is transmitted to the corresponding and switches of all odd groups at the same time, for example, Svi, 82.hvt 8bp from the registers of block 7 to the corresponding switches of all even groups simultaneously for example, 8 "n. - 820/8, - 8 4.VI. De 13 of block 3 permits the passage of information from blocks 6 and 7 through switches 8 to blocks 1. At the same time, in all blocks 1, the same addresses are sampled in accordance with Crasdone, where K is 02 2. P is the bit size of the memory cell, the code combination coming from you 14 block 3. The recording of information in the corresponding groups of VI blocks 1 is carried out strictly in accordance with the control signals on the same output 14. Thus, each I-bit word recorded per cycle in the shift registers is entered into the corresponding block 1 is consecutively in VI cycles. But since the loading occurs simultaneously in l blocks 1, then during these h cycles there are inputting words into the memory matrix. Depending on the size of block 1, one, two or more zones can be organized. Usually, 16 or 32 bits are entered at the same time, and as block 1, a block of operative memory is taken with a random sample of 256 or more bits of one bit. So you can organize a multizone memory matrix. The processing of information stored in the memory matrices is carried out in blocks 2, in which the set of arithmetic and logical operations is determined by module 48. As module 48, the K155IPZ chip is used commercially, designed for logical and arithmetic processing of two four-bit operands. However, in order to organize one-bit (one-bit) arithmetic operations, its three minor inputs 53, 55 and 57 of one operand are combined and connected to output 15 of the COIiSt O block 3, and the three minor inputs of 54, 56 and 58 of the second operand are combined and are connected to the output iSjCOhS-t of block 3. Thus, the processed bits of the two operands go to the two higher inputs 5E for module 48. Depending on the code combination, the outputs 15–15 of block 3 in block 2 can have one of sixteen arithmetic or logical functions in accordance with with tab "lyceum (Fig. 7). . The selection of the mode of logical or arithmetic information processing is carried out using output 15, block 3. If there is a logical O on this output, block 2 performs logical operations, otherwise, arithmetic. Trigger 45 serves to memorize one of the operands when working with two operands, trigger 46 to memorize the result of performing an operation, trigger 47 to memorize the transfer when performing logical operations. All triggers memorize information received at their first inputs upon arrival at their second inputs of clock signals from the outputs of block 3. Initially, one bit of the first operand is read from the memory array and written to trigger 45, the output of which is connected to the high input 60 of one of the operands of module 48 One bit of the second operand is then read, which, to Trigger 45, goes to the high-end input 59 of the second operand. The result of processing two bits1 of the two operands is read from the output of 62G. Module 48 and written to the trigger 46. If logical operations are performed in module 48, the result of these actions at output 62 does not depend on the order of three pairs of lower inputs 53-58 transfer from wah da 15b. block 3 to the input 64 of the module 48 corresponds to the logical logical message. When there is a transfer signal transmitted from flip-flop 47 to input 61 of module 48, when performing the arithmetic operation of the preceding pair of bits, this transfer is added to the values continuously applied to the lower inputs 53 to 58 of module 48, and transmitted to the pair of inputs 59 and 60 , which receive the processed bits of two operands. The presence of a logical one at outputs 15–15 of block 3 ensures the reception of information from block 24, respectively, from three directions: either from the front of the block through bus 51 when information is shifted downwards, or from the block through bus 49, or from the subsequent block (bus 52 information is shifted upwards. Thus, the processing of two operands in blocks 2 is carried out in three steps. First, one bit of information from the first operand is read from block 1, which is written to flip-flop 45. Then one bit of information from the second operand is read from block 1, the output operation code is output from the outputs, and the signal from output 15 is written to the trigger 47. In the third stage, the result of the operation from the trigger 46 is written to the corresponding block 1. When processing one operand, for example, in search operations the next bit is read from block 1 and transmitted to block 2, which is already tuned to the corresponding operation. The result is recorded in trigger 46 and then rewritten to corresponding block 1. The result of arithmetic and logical operations on data arrays from blocks 2 is written to the memory matrix, from where it can be read with a view to wiring it out of the processor. For this, unit 4, by means of control signals at the output 10 of unit 3, switches the information read from the memory matrix for recording it first in one block of buffer memory and then in another. The filling of all registers of blocks from blocks 6 and 7 is carried out sequentially by bits. Information is retrieved from the process of block through block 5. An example of the implementation of the registers is 1 g of blocks 6 and 7 is a commercially available K155IR13 chip. The proposed processor is easy to manufacture and has high speed. In the known processor, executed on a high-speed series by the ECL technology, the access time to the memory is approximately 120 not (40 NS each for reading or writing information into the memory and for the multiplexer and the permutation network). In the proposed processor, the time of accessing the memory matrix in the data processing processor is approximately 40 NS due to the fact that the information from the memory matrix is directly entered into arithmetic logic units. The load of W and bit words into the data processor is Ui + And clocks. The first clocks need to be spent on the initial load of the registers of one of the blocks of the buffer memory. In a known processor, data is loaded into m blocks of memory in km cycles. However, each of these cycles includes the time that must be spent on the passage of the multiplexer and the permutation network. For example, for a memory matrix of 1024 words by 256 bits in a known processor, this time is 122.9 ISS, and in the proposed 51, 2 ISS. Thus, with an increase in the amount of memory, the effectiveness of the proposed device for inputting information into the matrix increases. An important difference between this processor and the known one is that the 16 or 32-bit words come from the input of the processor directly to the memory. In a known processor, a pre-formation of 256-bit words is performed using an external interchange network. A feature of this processor is that the vertical shifts of information in two directions in combination with writing to the memory matrix at an arbitrary address allow complex operations with data arrays, such as permutation, sorting, transposition, and others. Formula 1. An associative matrix processor containing memory blocks, arithmetic logic units by the number of memory blocks, a control block, input and output blocks of the switches, the outputs of the memory blocks are connected to the information input The corresponding arithmetic logic blocks and information inputs of the input block of switches, distinguished by the fact that, in order to increase productivity, it contains the first and second blocks of the buffer memory and the switch groups, the total number of blocks is equal to the number of memory blocks, and the first and the second information inputs of the buffer memory blocks are connected respectively to the information input of the processor and the output of the input block of switches; the first information outputs of the first and second blocks of the buffer memory are connected respectively But with the first and second information inputs of the output switch unit whose output is connected to the information output of the processor, the second information outputs of the first and second blocks of the buffer memory are connected to the first information inputs of the first and second groups, the second information inputs of the switches are connected to informational; outputs are appropriate. the arithmetic logic units, and the outputs of these switches are connected to the control inputs of the respective memory blocks, the first input and the transfer output of each arithmetic logic unit are connected respectively to the second output and the transfer input from the middle arithmetic logic unit and the first, second, third, the fourth, fifth, sixth and seventh outputs of the control unit are connected, respectively, by the control inputs of the input unit of the co-switches, the first and second blocks of the buffer memory, and the switches of the first and second groups, the address inputs Wires of the memory blocks and control inputs of the arithmetic logic units and the output block of the switches 2. Processor POP.1, characterized in that the control unit contains a clock signal generator, a register of states, a memory of control commands, a microinstruction memory, a register control commands, microinstructions register, two groups of AND elements, a group of OR elements, a decoder and three AND elements, the first and second outputs of the state register are connected respectively to the first inputs of the AND elements of the first group and the sync signal generator input, The first inputs of elements AND of the second group are connected to the first output of the register of control commands, the second output of which is connected to the memory input of microcommands, the second inputs of the elements AND of the first and second groups are connected respectively to the first and second outputs of the generator ;, sync signals, the third, the fourth and fifth outputs of which are connected respectively to the control inputs of the register of control commands, the register of microcommands and the first inputs of the first, second and third elements AND, the first and second inputs of the elements OR. connected to the outputs of the elements And, respectively, of the first and second groups, and their outputs are connected to the input of the memory of control commands, the outputs of the memory of micro-commands and the memory of control commands are connected to the information inputs of the register of micro-commands and the register of control commands, respectively, the first, second, the third, fourth, fifth, sixth. and seventh outputs of the register of micro-commands are connected respectively to the first output of the block, the second inputs of the first and second elements I, the fourth output of the block, the input of the decoder, the second input of the third And lementa and seventh output unit, and outputs the first, second and third elements and connected respectively to the second, third and sixth outputs of the block. Sources of information taken into account during the examination 1. USSR author's certificate No. 4779114, cl. G06P 15/00, 1975. 2. US patent 3,800,289, cl. 340-172.5, published. 1974 (prototype.), / 7 t1. r5, f Jl -y t / 2. A n S, eight 2P : S m-zn 8mm- {n + i} mn P / J tfi.2 U 1b ... well. ten eleven M 12 ZV fS sixteen. And i. F