JPS5897083A - Vertical-horizontal conversion circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

The present invention relates to an aspect conversion circuit that rotates a dot matrix pattern by 9011E. For example, Japanese word processors have printers and CRT displays as output devices, but C
On an RT display, the display is written horizontally [If you do this, things will be complicated, whereas with a printer, when distributing a hard copy of the display content on a CRT display, even if it is written horizontally on the screen, it will be written horizontally on the screen because of the format. It may be necessary to write vertically. However, in order to have a printer print a horizontally written document as vertically written, all one has to do is change the memory access direction, but this was considered impossible. There is also a method of providing two types of memory that can be accessed in the row direction and one that can be accessed in the column direction, and converting a large amount of data between them. There may be undesirable aspects such as an increase in cost and an increase in the amount of circuitry. To avoid these problems, conventional Japanese word processors share memory for providing data to the CRT display and printer, so they are equipped with memory for column-direction access, for example, when a printer requires vertical writing. This was done using a circuit that had the function of rotating the data stored in the memory by 90 degrees. The conventional vertical/horizontal conversion operation procedure will be described below. For example, when writing a horizontally written document (Fig. 1(a)) vertically (Fig. 1(b)), character pattern memory 1, parallel-serial conversion circuit 2
, -Character 7a 3. R/W order control circuit 4, serial-parallel conversion circuit 5, output buffer memory 6, and a counter (
(not shown), etc. (not shown). Here, for example, rAJ and (one word horizontally written sentence n 90'
Considering the procedure for rotating and converting to vertical writing, we can see that: ■ The 8x8 dot matrix data (number 1 in Figure 3(a) The first line shown [0
0011100], the second line (0
0100010)% and below Similarly, the third line (0010001
0), 4th line (00111110), 5th line [0010
0010], 6th line (00100010), 7th line [0
0100010), 8th line Cooooooooo)) is specified as the row address. If the reading unit is specified, for example, 8 pits, the 1st line address is specified,
(00011100), when the second line address is specified (00100010), the eighth line (oooo
oooo)). ■This 8-bit parallel data (first line [0001110
0), etc.) is shifted by the parallel-to-frial conversion circuit 2 (shift register, etc.) in synchronization with a clock signal (not shown), and as serial data (the first row is
o, o, tall, (Ll, Ill. 田, IC)] ,■) - character buffer 3
This serial data is output as shown in Figure 3 (bl).
)), and when the column address is updated to a predetermined address, the row address is updated (for example, the output D for the first row, [11°0, ■, ω,
(l], (kl, after the mouth, the output for the second line is o, o
, tL1. o, o, o, tn, o, and so on, ic 8th line o minute o output o , o , to , o , o , [Ql
, lC1]. (up to ■) - written to the character buffer 3 in dot units (o. ■, etc.). ■- The character buffer 7 is written dot by dot, and the reconstruction of rAJ in the original character pattern memory l is shown in Figure 3 (C1
When the data is completed as shown in FIG.
The output from line 8 to line 8 is o, o, o, o, o, o
, the output from the 1st row to the 8th row of the 0.2nd column is 1
01.0), Q). ■, Q), [Ll, Q), ■ Similarly, the outputs from the 1st row of the 8th column to the 8th row are o, o, o, o. o, tm, o, o), and are read out dot by dot. ■ Read serial data (for example, output from the 1st column from the 1st line to the 8th line, ■, o, ■, ■, 0° [Ql, 0),
103) is converted into parallel data ((oooooooo
o), etc.) to the output buffer memory 6. ■This parallel data is written in writing units ((0oooooooo
) etc.), from the first line (00000000] (Figure 3 (d) O number 1) to the second line [ollllllo], and similarly from the 8th line (oo. 00000) (Figure 3 (d) number 8). By the above procedure, the content of character pattern memory l becomes 90.
degree and transferred to the output buffer memory 6. However, the method using the above circuit has the disadvantage that it requires two parallel-to-serial converter circuits and a one-character buffer memory, and also requires many circuits for the read/write control section of this memory. Ta. The present invention was made based on the above-mentioned circumstances, and it is an object of the present invention to simplify a data vertical/horizontal conversion circuit in a character pattern memory. An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 4 is a block diagram showing one embodiment of the present invention.
Character pattern memory 7, selector 8, shift register 9
, output buffer 7, Y address counter 11. It consists of an X address counter 12. The character pattern memory 7 holds character pattern data based on a dot matrix, and when a line address is specified,
Data is read in units of 8 bits. The selector 8 receives the data read from the character pattern memory 7 and outputs one bit out of the data bits. The shift register 9 receives the output of the selector 8 and
Bit data is latched, shifted in synchronization with the clock signal 13, and output to the output buffer memory. The output buffer memory 10 receives the output of the shift register 9, and when it receives an address designation signal 15 and a write timing designation signal 14, it can be written in a write unit. The Y address counter 11 receives a clock signal, counts with the clock signal, specifies the read line address of the character pattern memory 7, and sends the output of the counter to the output buffer memory 10 for write timing. The X address counter 12 receives and counts the output of the Y address counter 11, and sends the output of this counter to the write row address of the output buffer memory 10 and the output bit of the selector 8. The above is the configuration of one embodiment of the present invention. Next, the operation will be explained with reference to the drawings. For example, when the character rAJ is stored in an 8×8 dot matrix pattern memory. The stored information in the character pattern memory 7 is arranged as shown in FIG.
11100), the second row address 1 is (00100010), the third row address 2 is (00100010], and the fourth row address 3 is (00111110). )% 5th line to 9th line address 4 is (00100010), 6th line
The row address 5 is (0010001o
L 7th line to 9th line address 6 is (00100
010), the address 7 on the 8th line and 19th line is (o
oooooooo)). When the 0th line address is “0” and reading of the 1st line of t9 is specified in the character pattern memory 7, [0001110
0) data (FIG. 5(b)) is read out and the selector 8
is supplied to When the output bit specified by the output of the X address counter 12 is the fifth column from the right, the selector 8 selects the bit [1] (FIG. 5 (C )) is output to the shift register 9. The shift register 9 latches and shifts the clock signal in synchronization with the clock signal. Next, the row address is updated to "1". When the reading of the second row of the thumbnail is specified in the character pattern memory 7, data (00100010) is read out and supplied to the selector 8. In this case, the X address counter 12 has not been updated yet, and the output of the bit in the fifth column from the right remains specified, so the bit in the fifth column (#) to the right of (00100010)

[0] is output to the shift register 9. The shift register 9 receives this data bit in synchronization with the clock signal 13.

Latch [0] and shift. Thereafter, the designation of the row address of the character pattern memory is updated in the same manner until the X address counter 12 is updated, and the data bits output from the selector 8 are: ■ 9 ro, 0 . (
Ll, 0. B. Each mark is seven times. Each time these data bits are output from the selector 8, they are latched into the shift register 9 in synchronization with the clock signal 13 and shifted to become parallel data. The shift register 9 transfers parallel data (
The data converted to 10010000) is output by the write timing signal 14 by the output of the Y address counter 11.
In synchronization with this, data is written to the fifth row of four row addresses of the output buffer memory 10 in write units. ■Once again, when the line address is “0” and the reading of the first line is specified to the character pattern memory 7 (00011
・100] is read out and supplied to the selector 8. The selector 8 is the bit in the sixth column from the left of the above data (00011100) because the output bit specified by the output of the X address counter 12 is updated and becomes the sixth column from the right.

[0] is output to the shift register 9. Shift register 9 latches and shifts this data in synchronization with clock signal 13. Next, when the line address is updated and the readout of “1” or υ second line is specified in the character pattern memory 7, (oo
roooto) is read out and supplied to the selector 8. In this case, the selector 8 selects the bit in the sixth column from the right (ooz. 0010) because the X address counter 12 has not been updated yet and the output of the bit in the sixth column from the right remains specified. 1) is output to the shift register 9. Shift register 9 latches and shifts this data bit in synchronization with clock signal 13. Thereafter, the row address is updated in the same manner until the X address counter 12 is updated, and the data bits output from the selector 8 are o, +11, [Ll, ta, ■, ■. ■, 0. These data bits are latched and shifted in the shift register 9 in synchronization with the clock signal every time the selector 8 outputs them, and the data bits become parallel data. The data converted into parallel data [01111110) by the shift register 9 is written in write units to the output buffer memory at row address 5, the last row, in synchronization with the write timing signal 14 from the output of the Y address counter 11. . Thereafter, the row address of the output buffer memory 10 is updated in the same manner as in (1) and (2), and the parallel data in the shift register 9 is written to this memory 10. As a result, the output buffer memo 9100 line address “0
” In other words, the contents from the first line to the eighth line with the line address “7” are also shown in FIG. 5(e).
110), 3rd line (10010000), 4th line (
10010000), 5th line (10010000),
6th line (01111110), 7th line coooooo
ooo), and the 8th line (o. ooooooo). As described above, the data resulting from parallel conversion of the output of the selector 8 by the shift register 9 is one unit in the column direction of the original character pattern memory 7, so it is transferred to the output backup memory 10 in the row direction. When the character pattern memory 7 is stored as a unit, the contents of the character pattern memory 7 are rotated by 90 degrees and reconstructed in the output rough memory IO. In this way, the vertical and horizontal conversion of the character pattern is completed. In this embodiment, the character pattern memory is an 8 x 8 dot matrix, but in addition to this, a 16 x 16.2 dot matrix is used.
4X24.32X32.64X64 etc.8.12.16
We can also consider the case of a matrix consisting of multiples of . In this case, the reading unit of the character pattern memory is CP.
Since the number of bits is U, for example, it is necessary to divide data for one column into several times for reading/writing, and a circuit to control this operation is required. Further, although the present invention has been described with respect to conversion from vertical to horizontal, conversion from horizontal to vertical is also possible with the same configuration and operation. The effects of the present invention are as shown below. - There is no need for memory for the character buffer, and the so-called memory can be placed on the shift register 1 side. This rounding eliminates the need for the conventional control circuit (R/W order control circuit), and the overall amount of circuitry is small and simple, so the impact it has on the product is significant, such as improving reliability. . As described above, the present invention is characterized in that when data is transferred between memories and the contents are converted vertically and horizontally, a character buffer is used to streamline the circuit.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of a format, FIG. 2 is a block diagram showing a conventional example, FIG. 3 is a plan view showing an example of reading/writing from various types of memory in the conventional example, and FIG. FIG. 5, a block diagram showing an embodiment of the present invention, is a plan view showing a read/write state of the memory according to an embodiment of the present invention. 7...Character pattern 8...Selector 9...
・Shift register 10... Output buffer memory 11
... Y address counter 12 ... X address counter 13 ... Clock signal 14 ... Output buffer memory data write timing signal 15 ... Output buffer memory row address designation signal Agent Patent attorney Noriyuki Chika (1 other person)

Claims (1)

[Claims] A pattern memory in which a dot matrix pattern is stored, data is read in the X direction by supplying a Y address to the memory, the Y address is updated based on a clock supplied from an external source, and the Y address is updated and supplied to the memory. A Y address counter, an X address counter whose address is updated by a carry output issued by the Y address counter and supplied to the memory, and one bit of the read data is output to the X address counter. a selector that selectively outputs based on the X address;
A vertical/horizontal conversion circuit comprising a shift register for shifting and storing data obtained through the selector based on the clock.