JPS60209880A - Write controller of image memory - Google Patents

Abstract

PURPOSE:To write data in a high speed and designate minute character positions by designating coordinates in each bit unit in case of arrangement of characters and writing in 32-bit units. CONSTITUTION:If a start address (x) of a print character is on the 7th bit of the 3rd block B2 of a section Si, this four byte data is justified down in a shift register SR and fills lower four bytes of the register SR with upper two bytes left empty. Upper two bits U2 are ''10'' (binary) and lower three bits D3 are ''110'' with respect to upper five bits of the start address (x) of the character, and data is shifted in the register SR by complement ''010'' of eight in these lower three bits. Next, 22 ''0'' ader added to the left of 10 bits of the left of one dot line DL to write these 32 bits in the section Si simultaneously, and 10 ''0''s are added to the right of 22 bits of the right to write these 32 bits in a section Sj.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a display image memory write control device for a non-impact printer.

Prior Art and Problems Non-impact printers obtain dot pattern data of characters to be printed from a character generator (CG) and print the characters on paper by controlling, for example, a laser beam according to the data. Characters, in this case kanji, are represented by dot patterns such as 30x30 dots, but there are other methods in which laser light is controlled by reading out the dot pattern of one line of character strings for each tontoline (horizontal dot row). A dot pattern of a group of characters for one page is developed into one of a pair of image memories, printing starts when the development is completed, and at the same time, development of a group of characters for the next page into the other image memory is started. There is also a method in which continuous printing is performed while alternately using image memories. The present invention relates to the latter, and makes it possible to store character data (dot pattern data) at precisely specified positions on the image memory at high speed.

If character data is stored in the image memory one dot at a time (one bit in character data), this is the same as normal memory writing and there is no particular problem, but if an extremely large number of dot pattern data are stored one bit at a time, If you do that, it will take a lot of time. Therefore, a method is adopted in which a plurality of bits are written at once, and for example, 32 bits are adopted as the plurality of focuses. This reduces the memory word length to 3
2 bits, and 1 of the 32 bits is set with one address signal.
This can be done by allowing the word to be accessed.

The tontoline of one character is 30 bits as mentioned above,
If two points of focus are applied between characters, the above 32 bits becomes the dot line length (width) of one character. One page of X-
Considering on the Y two-dimensional image memory, each line in the X direction (a line or dot row in the X direction is called a line) is 32
It is divided into bits, and an address is given to the first bit of each section, and 30 lines in the Y direction corresponds to one character, so the address of the first bit of the above section on the topmost line of each 30 lines is This is the first address of each character.

The characters on one page may be densely packed from the beginning of the page, that is, the upper left corner, to the end, that is, the lower right corner of the page, but usually there are blank spaces.

Especially for headings, there is usually space on the left and right, and a little or a lot of space above and below. That is, the arrangement of characters is performed by specifying the coordinates of each character. Although the above-mentioned head address can be used as the coordinates for specifying the character position, it is only possible to specify the above-mentioned discrete address every 32 bits. If coordinates can be specified in units of bits, character positions can be specified quite precisely, and any desired format can be created. However, writing is performed in units of 32 bits as described above, thereby increasing the speed.

OBJECTS OF THE INVENTION The present invention addresses the above-mentioned problems and provides an apparatus for storing print data in an image memory, which enables high-speed writing and fine character position specification.

Structure of the Invention The present invention comprises a data register that receives character pattern data from a character generator, a register that receives X and Y addresses indicating display character positions, and an X address that receives the shift output of the data register as input. A shift register whose shift amount is determined by the lower bits of the register and the output of the blocked shift register are input, and data indicating how many times the same character pattern data is written as the middle bit of the X address register is used. The present invention is characterized in that it includes a multiplexer that selects a block of the output, and writes the output data of the multiplexer to a memory access address determined by all bits of the X address register and the upper bits of the X address register. This will be explained in detail with reference to.

Embodiment of the Invention FIG. 1 is a block diagram showing an embodiment of the invention, in which IMM is a print image memory and CG is a character generator. Also Y
AR is the X address register, XAR is the X address register, AR is the address register, GFR is the graphic register, CC is the clock control circuit, DR is the data register, SR is the shift register, MPX is the multiplexer,
DOR is a data output register.

The code and position data of each character in one page to be printed are sequentially output character by character from a memory (not shown), and the character code is set in the address register AR to become the address to access the character generator CG, and the position data is The X address of data A1 is set to register XAR, the Y address is set to MAR, and image memory I
This is the MM access address. Characters have different sizes, but the character pattern data stored in the CG is for 9 dots, and one character is 32×30 dots. When the character generator CG is accessed using the character code stored in the register AR, 32 bits for one ton trine (at the top of the first line) of the character are read out and sent to the data register D via the data bus DB.
Then, the address register AR is incremented by 1 by the increment mechanism, so that the 32-bit data of the next dot line is stored in the data register DR through the data bus DB, and this process is repeated 30 times. A tone pattern for one character is extracted from the CG.

In this example, the sizes of characters that can be printed are 9-bore, 7-bore, and 12-bore, but what is included in the character generator CG is the middle 9-bore, and for 7-bore and 12-bore, it can be enlarged, Deal with it by downsizing. This expansion and reduction is performed during the process of transferring the pattern data of each tontoline from the data register DR to the shift register SR.

That is, when the shift clock of the data register DR is stopped and the shift clock of the shift register SR is added, the data 2
Since repeated reading is performed, the character pattern is enlarged, and conversely, when the shift clock of the shift register SR is stopped and the shift clock of the data register DR is added, overwriting and bit truncation are performed, resulting in a reduction of the character pattern. If the shift clocks of registers DR and SR are added together, there will be no enlargement or reduction, and the result will be a mere isometric copy.

The circuit CC performs such clock control. Further, it is preferable to overwrite and read twice in an inconspicuous part of the character pattern, and this inconspicuous part differs from character to character. Control data is prepared for where to overwrite 72 degrees for each character to be written, and the control data is taken into the graphic flag register GFH for 1 ton trine of the character, and the control circuit CC is clocked. Supply control data.

The print character position data A1 consists of the X address and Y address of the memory IMM, as shown in FIG. In other words, the image memory IMM can be considered to be an X-Y plane with the upper left corner as the origin, and the printed character 1
One can be represented by a rectangular frame A. The scale attached to the X-axis is 3 above.
The lines are separated by 2 bits, and the scale marked on the Y-axis is marked every 20 lines for convenience. The width of the rectangular frame A is 32 bits horizontally (X) and 30 lines vertically (Y).

The starting end address X of the rectangular frame, that is, the print character area.

y is the X address and Y address included in the position data A1. This X address is in units of bits and not in units of divisions, so it may be located in the middle of divisions S as shown by X in the figure. Since the Y address is in units of lines (bits in the Y direction), it is not in the middle of the division like the X address.

Therefore, the Y address written to the register YAR immediately becomes the access address of the memory IMM. On the other hand, the X address of the register MAR except for the lower 5 bits (this indicates the address of the delimiter S) is led to the memory IMM and becomes an access address.

The lower 5 bits of the X address are 32 divided by S.
Indicates the address of each bit within the bit division. This is further divided into four blocks, each having four 8-bit blocks. Therefore, the upper 2 bits (medium in terms of the whole) of the lower 5 bits U2
is the block, and the lower three bits D3 indicate the address of the block content bits. In the present invention, these 5 bits are used to move on the register to change the position of the 1 ton line of the printed character on the above classification, so that the first address X of the printed character comes to the designated position as shown in Figure 2. Make it. Furthermore, this movement process is performed by selecting the block described above and shifting within the block by 8 focus or less, so that the required time is kept as short as possible.

Shift register SR is used for the above-mentioned intra-block shift, and is 5 bytes from register DR (3 bytes when enlarged).
It has a capacity of 6 bytes, which is 2 bits (4 bytes becomes 5 bytes) plus 1 byte as a shift space, and after inputting data for 1 ton trine from register DR, it is shifted by the lower 3 bits D3. Perform the operation. The 6-byte data of the register SR shifted in this way is applied to the multiplexer MPX, and the upper (or middle) 2
Receives byte selection processing by bit U2.

To explain this with reference to FIG. 2 Tb), the first address
In this case, the 1 ton trine DL of the character exists across the segment St and the next segment sj, and its left and right ends are blank spaces (generally, the left end contains the preceding character, and the following character is at the right end). In this case, it is assumed that one dot line DL is 4 bytes, that is, the character size is 9 points, and it is not enlarged or reduced.

These 4 bytes of data are packed into the shift register SR from the bottom, leaving the top 2 bytes of the register and filling the bottom 4 bytes, as shown in (2). The lower 5 bits of the first address
Then, the lower 3 bits are shifted by the 8's complement number 010, resulting in a state of ■. That is, the data is packed in the middle 32 bits of the 6-byte shift register SR, leaving the upper 14 bits and the lower 2 bits empty. The contents of the shift register are taken out by a multiplexer MPX according to the upper 2 bits U2 and a 2-bit signal W2 indicating whether the writing is the first, second, or third time from the memory access circuit MAC.

That is, as shown in FIG. 2 (in the BLO example, the 10 bits that fall into the section Si are written the first time, and the 22 bits that fall into the section Sj are written the second time. The third write is performed when it is enlarged. Printed characters If the start address X starts from the delimiter S and the number of bytes is 4, one write is sufficient. Therefore, the number of writes is determined by the start address and the number of bytes of one dot line. As is clear from the above, the left lO dot of the 1 ton trine DL is
Adding 22 zeros to the left side and writing 32 pins simultaneously to the section St, then adding 10 zeros to the right side of the 22 bits on the right side of the dot line DL and writing them to the section Sj, the dot line DL can be written. As specified, it is possible to write from the first address X.

To explain the processing at multiplexer MPX in Figure 3,
This MPX takes out designated 4 bytes from the 6-byte shift register SR and stores them in the 4-byte data output register DOR. Here, the readout output of each byte of the 6-byte shift register SR is a, b,...f
As shown in the figure, these outputs are added to the four groups of input terminals of the MPX as shown in the figure, and one of them is taken out from the output terminals 01 to 04 of the MPX and sequentially stuffed into each byte of the register DOR from the bottom as shown in the figure. It will be done. As shown in the figure, there are 9 types of input sets to the multiplexer MPX (therefore, there are 4 bits in total to select them: 2 bits of U2 and 2 bits of W2).
focus), ■ is a, b, c, d, ■ is 0. a, b, c,
■ is 0,0. a, b, ·--■ is f, 0, 0.0. As in the example in Figure 2, when data is stored in the lower 5 bytes leaving the upper 1 byte of register SR, a=0, and b
-f has data. If the upper 2 pins 1-U2 of the lower 5 bits of the start address are lO, the MPX selects the input pair ■ for the first time, and the register DOR contains Q, a
, b, and c are written. The two bytes O and a are all 0, and the upper 6 bits of byte b are unconditionally 0. The second time, the input set of MPX is taken out, and the d, e, and f bytes are written to the register DOR. The lower two bits of this f byte are unconditionally O.

Register DOR becomes the write data register for memory IMM, and before writing, the 4 bytes are read, the read output is ORed with the data in register DOR, and the OR output is re-sent to the register. This becomes the write data for the section Si. As mentioned above, the part to the left of the first address
It will definitely be written to t. This time, the latter half of the character can be simply written, but in order to perform the same operation, it is also read out, the output data is ORed with the data stored in the register DOR, it is reset to the register DOR, and the Writing to section Sj is performed according to the contents of DOR. Since the read data in this case is all 0, there is no particular problem in logic.

As described in detail, according to the present invention, print data can be precisely specified in the print image memory, the number of shifts can be reduced, and storage can be performed at high speed, which is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are operation explanatory diagrams. In the drawing, IMM is print image memory, CG is character generator, DR is data register, XAR is X address register, YAR is Y address register, D3 is lower bit, U
2 is a middle-order pin 1-1W2 is data indicating the number of writing, SR is a shift register, and MPX is a multiplexer. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi 2m (a) Cheetah 2 E-/) 010 Sono Diagram 3 Procedural Amendment (Voluntary) Indication of the May 1985 Pau Day Incident 1988 Patent Application No. 36804 2. Name of the invention: Image memory write control device 3. Relationship with the person who makes corrections Patent applicant address: 1 ois, Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Representative of Fujitsu Limited Takuma Yamamoto 4, Agent 101-5, Date of amendment order None 6, Number of inventions increased by amendment None 8 Contents of amendment (1) "Indication" on page 2, line 8 of the specification delete.

Claims (1)

[Claims] (11 A data register that receives character pattern data from a character generator as input, and an X that indicates the display character position. A register that receives a Y address as input, and A shift register whose shift amount is determined by the lower bits of the address register, and data indicating how many times the same character pattern data is written as the middle bit of the X address register, using the output of the blocked shift register as input. A write control for an image memory, comprising a multiplexer for selecting a block of the output according to the method, and writing output data of the multiplexer to a memory access address determined by all bits of a Y address register and upper bits of an X address register. Apparatus. (2) Each shift operation of the data register and the shift register is temporarily stopped in relation to each other so that display characters can be enlarged or reduced. The image memory write control device described above.