JPS59197083A - Crt display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to raster scan moats, furthermore in bitmap format.
The present invention relates to a CRT display device that can access video RAM in units of dots.

BACKGROUND OF THE INVENTION In recent years, as the price of semiconductors has decreased, the number of CRT display devices (hereinafter referred to as CRTs) that can access video RAM in the form of bitmaps is increasing in low-cost computers and terminals. Furthermore, in recent years, it has become OA! 0CRT is not only used as a display device, but there is even a movement toward turning it into printed matter. For this reason, advanced editing and fair copying functions are required.

One of them is movement of the display position such as right alignment, left alignment, and centering (f-rational space). This is possible with a normal character display map type CRT. However, if the write address of the video RAM deviates from the byte or word boundary, it must be constantly corrected using a shift command by the program, the processing speed is slow, and complicated control is required. , a huge control program is required.

Purpose The present invention has been developed in view of the above points, and is capable of processing character numbers even at addresses that do not match (straddle) byte or word boundaries at extremely high speed in a CRT device having a bitmap type video RAM. To provide a CRT display device in which turns can be easily written and the number of dots between each character box can be easily controlled.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 2 is a block diagram of the CRT display device of this embodiment. Reference numeral 1 denotes a video RAM, that is, a RAM for storing patterns to be displayed, and 4 turns are written by the CPU 2 through a video RAM writing circuit 3. 4 is C for displaying the pattern written in the video RAM on the CRT.
It is an RT controller. The video RAMI pattern is 20 loads/20 times under the control of the CRT controller 4.
The parallel signal is converted into a serial signal by the parallel-serial converter 5 according to the shift signal and the shift signal,
It is displayed on the CRT 7 via the video controller 6. 8 is a multiplexer for selecting an input signal to the video RAMI, and 9 is a path driver. Further, the signals outputted from the CRT controller 4 to the video controller 6 are a timing signal 17 and a horizontal synchronization signal 18, respectively.
and a vertical synchronization signal 19.

FIG. 3 is a block diagram of the video RAM filling circuit 3 in FIG. 2. In the figure, a character pattern address register 10 is a register indicating the memory address of a character pattern turn memory 16 in which character patterns, graphic patterns, etc.
AMIK letter A? Write address for writing the turn and 1: Bit offset within 1 byte of the write address. This is controlled by the CPU 2 and updated by the address addition circuit 14. The offset addition register 13 stores a value that is added to each address in the write address register 11 and video RAM offset register 12 at a bit offset relative to the address where the next character is to be written after writing one character pattern. The character pattern expansion circuit in which is stored reads the character pattern address register 11 and the video RAM offset register 1, which reads the character pattern address register 11 and the video RAM offset register 1.
This circuit writes the character Noreen into the video RAMI corresponding to No. 2. Here, the size of one character box, that is, the size of one character, and the number of scanning rasters are set in advance by the CRT controller 4.

Figure 4 shows the character pattern expansion circuit 1 shown in Figure 3.
5 is a conceptual diagram showing the operation of No. 5. FIG. In the figure, 16 is a character pattern memory in which character patterns are stored, and 17 is a character pattern read out from the character pattern memory 16 and set therein according to the set value of the video RAM offset register 12. A pattern shift register 18 shifts character pattern information, a pattern mask register 19 selects character pattern information to be written to the video RAM based on the value set in the video RAM offset register 12, This is a mask circuit that masks the character pattern information in the turn shift register based on the input signal and sends it to the video RAM.

Suppose that one character pattern consists of 8 dots horizontally x 9 dots vertically, and the pattern stored in the character/pattern memory 16 specified by the value set in character pattern address 10 is divided into 8 bits (8 Load the dot into the lower position (a) bit of the transistor 17. At this time, the lower 8 bits (b) of the pattern mask register 18 are turned on and the upper 8 bits are turned off. Then, based on the offset value set in the video RAM offset register 12 (from 8 to the offset value), the bit no. 4' turn shift register 17 and the no lean mask register 18 are shifted to the left.

If 4# is set in the video RAM offset register 12, the pattern shift register 17 and pattern mask register 18 are shifted to the left by 4 dots.
The turn mask register 18 is [: 0000111
It becomes 1111100001B.

The mux circuit i 9 converts the value of the pattern shift register corresponding to the ON bit of the pattern mask register 18 into MP.
The data is sent to X8 and used as rewriting information for the video RAM. Then, write the upper bit of the pattern information to the video RAM corresponding to the video RAM address stored in the write address register ll, and then write the lower bit Ie to the address ((upper bit write address n+1).The count up of this write address is This is done by the address addition circuit 14. This completes the writing of the character pattern in the most significant column.Next, the write address of the video RAM of the doro is added to the upper bit write address, and the write address of the video RAM is added to the character pattern address. The information on the dots in the second column of the ``p'' character pattern is set in the pattern shift register and transferred to the video RAM by the same operation as described above.

By repeating this operation for 9 vertical bits, the video RA
Character pattern information is written to M. In this way, the CPU 2 writes the write address register 11, video RAM offset register 12, and character pattern address register 1o-ivw, and after setting the character pattern address, information can be easily stored in the video RAM 1 by simply starting the video RAMO I built-in circuit 3. can be written and displayed on the CRT screen.

If right alignment is required, set a bit offset according to the bitmap in the offset addition Renosph when writing the character pattern.

Then, when writing a character pattern, the address adder circuit 14 analyzes the bit set in the offset adder 13, updates the address value of the write address adder circuit 11 and the offset value of the video RAM offset register 12 based on the analysis results, Character pattern address register 1 is added to the video RAMI in the same manner as above.
Writes the character pattern specified by 0.

Effects As explained above, according to the present invention, it is possible to display edited text in a bitmap format such as in a proportional space with less software load and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of writing characters to the video RAM, FIG. 2 is a CRT display display device solo 22 of this embodiment, FIG. 3 is a block diagram showing details of the video RAM writing circuit, and FIG. 4 is a diagram showing character writing circuits. FIG. 2 is a conceptual diagram of the operation of the GuTurf 1 expansion circuit. In the figure, 1 is a video RAM, 2 is a CPU, 3 is a video RAM writing circuit, 4 is a CRT controller, 5 is a serial converter, 6 is a video controller,
7 is a CRT display section, 8 is a marff lexer, 10 is a character pattern address register, 11 is a video RAM address register, 12 is a video RAM offset register, 1
3 is an offset addition register, 14 is an address addition circuit, 15 is a character pattern expansion circuit, 16 is a character pattern memory, 17 is a pattern shift register, 18 is a nosetan mask register, and 19U mask circuit. Patent applicant Canon Co., Ltd.

Claims (1)

[Claims] CR that can access video RAM by bitmap
In the T display device, there is a shift section for shifting a pattern specified for display, a designation means for designating the number of shifts to the shift section, and a shift section for shifting the video RA according to the shift number of the designation means.
address updating means for updating a writing address to M; and pattern masking means for writing only the display designation pattern of the shift section into the video RAM; R
Update the AM write address, shift the display designation pattern by a specific number in the shift section, and write the display designation pattern to the video RAM.
A CRT display device, wherein only the display pattern masked by the pattern masking means is written to the update address.