JPS60150089A - Memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a storage device in a graphic display or the like.

[Technical background of the invention and differences]

In a conventional graphic display, as shown in FIG. There is. Normally, the device (2) is divided into a plurality of punctures, and a continuous dot is written on each puncture as shown in FIG. Data can be written to the Jl dots at the same time, allowing high-speed operation. Hereinafter, the 111th data stored in the data acquisition at one time will be referred to as a word. Currently, one word is preferably about 8 bits or 64 bits (Fig. 2, j51, 161). Also, in graphic displays.

The motion of leaning over the previously displayed data is performed quite frequently, but this is nothing but a partial rewriting of data in the one-stroke, one-image storage device.

In a graphic display, it is preferable that the specified unit of this part 4@dae be a bit unit rather than a word unit, and for this purpose, within a word,
It is necessary to have a means to rewrite only specific bits.

Conventionally, partial rewriting of data within a word has been performed using the flow shown in FIG. 3, which required complicated control and a large amount of hardware. In other words, as shown in the flowchart, it takes a long time to process one image, as it requires the following steps: reading the data from the storage device, calculating the read data and writing data, and writing the data to the image storage device. Control was also complicated.

[Purpose of the invention]

The purpose of the present invention is to eliminate these drawbacks of the prior art.
Less hardware! An object of the present invention is to provide a writing device that can rewrite parts of a word at high speed with just a single touch.

[Summary of the invention]

The present invention provides an address line for inputting an addressing signal, a storage section having a plurality of memory banks that can be accessed simultaneously by inputting an addressing signal from this address, and a storage section for each of the plurality of memory banks in the storage section. a first register that holds write permission/disapproval information corresponding to one bit; a write request pulse line for inputting a write request signal; and a rewrite for each of a plurality of memory banks in the storage section. A second register holds data corresponding to one bit, and a write permission signal held in the first register is activated by a write request signal inputted from the write request pulse line. and a gate circuit that supplies disallowance information to each corresponding memory bank in the storage section, and the memory bank to which the write permission information is input from the gate circuit is controlled by an address designation signal manually inputted from the address I0. The rewrite data held in the corresponding bit of the second register is written to the specified address.

〔Effect of the invention〕

According to the present invention, there are two procedures: writing to a register and saving to a picture storage device, which enables high-speed operation, and also reduces the amount of hardware, resulting in improved efficiency.

[Embodiments of the invention]

FIG. 4 shows the configuration of an embodiment of the present invention.

In this embodiment, there are eight banks, that is, one word consists of eight dots, and eight dots can be accessed at one time. Also, the width of the display screen.

This will be explained as 1024 dots (128 words).

If the coordinates of the dot at the upper left corner of the screen (not shown) are (0, 0)
=p+q/8 (p*q is an integer 0≦q≦7), then it is stored at address p in bank q.

In FIG. 4, (11) to (18) are banks θ to 7,
(30) is a register that holds rewritten dots in a word, and has a number of bits corresponding to the number of banks (8 in this case), and each bit (31) to (3) of the register.
8) holds information on whether banks (11) to (18) should be rewritten. For example, (35).

11' and the other bits are 10" (15)
This indicates that the bank (Bank 4) is currently subject to vow change. (20) is the aroma request pulse line, which passes through (21) to (28) in bank (1).
1) A compliment request pulse is supplied to the base 18). (5
0] is an address line that connects each memory bank (11) to (1
8) Commonly given to both. (40) is a register that holds slightly changed data for each bank.

Now, let us consider the operation when rewriting three dots from (130, 5) in the screen memory to (1, 0, 1) as shown in FIG.

Since 5X12B+130/8=656+2/8, the dot data to be rewritten is bank 2. Bank 3, Bank 4 ((+3), (14) in Figure 4)
(15) ) is stored at -address 656.

Therefore, register (30) is set to ('00111000')
and set the register (40) to ('dd10
Perform a sect every 1ddd (d can be anything). After that, send an address 656 designation signal to the address line (50).

When a write request signal is sent to the input request pulse line (20), this write color request signal is (13), C14)
, because it is issued only to the bank in (15) (11)
, (12), (16), (17), (1
The dot data in the bank of 8) does not change (13),
(14J.

Only the data at address 656 of bank (15) is (J+Q
, 1') and the purpose is achieved.

In FIG. 6, there are three parts corresponding to the register [30] in the embodiment shown in FIG.
)) with its selection lines (39), (69), and (79). This time, as shown in Figure 7, (130,5)
Let us consider the case of changing the dot of ~(155,5). The above dots are word numbers 656, 657, 65.8
, 659. Also, for words 657 and 658, all dots in the word must be changed, but for word 656, only the 6 dots on the right must be changed, and for word 659, only the 4 dots on the left must be changed. Good. Therefore, register (30) contains '00'.
111111 'L/') star (60) jc is °11
111111' Register (70) has °111100
By retaining the data 00' and switching to use, continuous dots from (130,5] to (155,5) can be written at high speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the graphic display device 8, Fig. 2 is a diagram showing the relationship between dots on the display screen of the graphic display device and pictograms and storage locations on the device, and Fig. 3 is a diagram of the conventional The image according to the method shown in FIG.
The figure is a block diagram of an embodiment of the present invention, FIGS. 5 and 7 are diagrams showing the dot positions at the time of rewriting, and No. 6 is a block diagram of another embodiment of the paddle of the present invention. (11) to (18)... Bank, (20)... 1-way non-pulse line, (21) to (28)... Gate, (30), (110)... Register, (50)...
・Address line. Representative Patent Attorney Noriyuki Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] An address line for inputting an addressing signal, a storage section having a plurality of memory punctures that can be accessed simultaneously by inputting an addressing signal from the address line, and a plurality of memory punctures in the storage section. There is a first register that holds budding permission/non-permission information corresponding to one bit for each memory puncture, a write request pulse line for inputting a write request signal, and a write request pulse line for inputting a write request signal; A second register holds rewritten data corresponding to one bit for each of a plurality of memory punctures, and a write request signal inputted from the write request pulse line causes the register statement of Maki 1 to be held. and a gate circuit that supplies write permission/disapproval information for each corresponding memory puncture in the storage section.A memory puncture to which write permission information is input from the gate circuit is connected to a memory puncture input from the address line. A storage device characterized in that the data stored in the corresponding bit of the second register is transferred to the address specified by the address designation signal and transferred to the address specified by the address designation signal.