JPH0361276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor memory devices, and more particularly to continuous reading of information.

An example of the configuration of a conventional semiconductor memory device is shown in FIG. In Figure 1, column addresses (A ₀ , A ₁ ,
... A _o ) selects the i-th column of the memory cell matrix 2 through the column decoder 1. The output of the memory cell matrix 2 is then input to a sense amplifier and digit driver 4. On the other hand, the row address (B ₀ , B ₁ , . . . B _o ) passes through the row decoder 3 to select a specific row. If the switching signal G _a is not input, the input/output section switching device 7 connects the input/output line a from the input/output buffer 8 to the input/output line c to the sense amplifier and digit driver 4, and outputs the switching signal G _a If input is input, input/output buffer 8
An input/output line a from the shift register 6 is connected to an input/output line b to the shift register 6. In input/output buffer 8, when write signal WE is input, input/output line a and input terminal
When IN is connected and write signal WE is not input, input/output line a and output terminal OUT are connected.
In addition, there is a bidirectional gate 5 in the wiring between the sense amplifier and digit driver 4 and the shift register 6, which becomes conductive if the gate signal G _S is input, and becomes non-conductive if the gate signal G S is not input. to control information leakage. Here, the sense amplifier and digital driver 4, the bidirectional gate 5, and the shift register 6 are in a one-to-one correspondence, respectively. For example, if the memory cell matrix 2 has m rows, the sense amplifier and digit
The number of drivers 4 is m, the bidirectional gates 5 are m gates, and the shift register 6 is m bits.
In addition, the shift register 6 uses a shift signal S (clock).
If you input , it will shift by 1 bit per clock.

The continuous readout operation of this conventional example will be explained in detail with reference to FIG. Memory cell matrix 2
The information stored in the i-th column and j-th row of is hereinafter referred to as (i, j).

To selectively read one bit, the column _address (A ₀ , A ₁ ,...A _o ) and _row address (B ₀ , B ₁ ,...
B _o ) can be input in combination, (i, j)
is read out. To continuously read m-bit information (i, j), (i, 2), ..., (i, m) in the i-th column, first input the switching signal G _a ,
When the i-th column is selected by inputting the column address (A ₀ , A ₁ , ...A _o ), the sense amplifier and digit driver 4 have (i,1), (i,2), ...,
(i,m) is read. At this time, the gate signal
When _Gs is input, the bidirectional gate 5 becomes conductive and the information read out to the sense amplifier and digit driver 4 is transferred to the shift register 6. The input/output switching device 7 also has a switching signal G _a
is input, the input/output line b of the shift register 6 and the input/output line a to the input/output buffer 8 are already connected, and without inputting the write signal WE, the input/output line a becomes an output. Connected to terminal OUT. Here, when the shift signal S is input for one clock, the information in the shift register 6 is shifted up by one bit, and (i, 2) becomes (i, 1), and (i, 1) is the input/output of the shift register 6. line b
and the input/output switching device 7, the input/output line a of the input/output buffer 8, and the output terminal through the input/output buffer 8.
It appears on OUT, so it can be read. Then, when the shift signal S is input repeatedly (m-1) times, (i, 2), i, 3), ..., (i, m)
appears at the output terminal OUT in synchronization with the shift signal S, so it is read each time.

The time required to read m bits continuously at this time
T _rn is the time required to randomly read one bit, T _r is the period of the shift signal S, T _s is the period of the shift signal S, and T _p is the time required for transfer from the sense amplifier and digit driver 4 to the shift register 6. T _rn = T _r + T _p + m・T _s .

In addition, when reading information over M columns continuously, first read i by column address (A ₀ , A ₁ ,...A _o ).
Column is sense amplifier and digit driver 4
The information is read out to the shift register 6 by the gate signal _Gs , and the i'th column is immediately read out from the sense amplifier and digit driver 4 by the next column address (A ₀ , A ₁ ,...A _o )'. Therefore, the time T _rM required to read M columns at this time is T _rM = T _r + M・(T _p + m・T _s ), and the sense amplifier is During the time T _p required for information transfer from the digit driver 4 to the shift register 6, reading cannot be performed and time is wasted, and moreover, smooth reading cannot be performed at a uniform speed. There was a drawback.

The purpose of the present invention is to eliminate this drawback by replacing the shift register of a conventional semiconductor memory device with two sets of shift registers having functions controlled by control signals. The object of the present invention is to provide a semiconductor memory device that can read out several columns of information continuously at high speed and smoothly, without changing the information readout speed from the conventional one.

According to the present invention, at least a memory cell matrix, a column selection drive device for the memory cell matrix, a row selection drive device for the memory cell matrix, and a memory cell matrix corresponding to each row of the memory cell matrix, respectively. a sense amplifier and a digit driver provided, two sets of shift registers that are shiftable in the column direction and are provided one bit in parallel corresponding to each row of the memory cell matrix, and the sense amplifier and digit driver. or an input/output section switching device that selectively connects input/output sections to the two sets of shift registers;
When continuously reading information stored in the memory cell matrix using a set of shift registers, the second shift register
The information is transferred from the memory cell matrix to the shift register (first shift register), and as soon as information reading from the first shift register (second shift register) is completed, the information is transferred to the second shift register. A semiconductor memory device characterized in that it includes a driving means for reading information from (the first shift register) is obtained.

The present invention will be explained in detail below using typical examples.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention. For convenience of comparison, parts equivalent to those in FIG. 1 are given the same reference numerals.

What is different from the conventional example shown in FIG. 1 in FIG. 2 is that instead of the shift register 6 controlled only by the shift signal S, there is a shift register 60 whose operation is controlled by the shift signal S and control signals X ₀ and X ₁ . , 61. Shift registers 60 and 61 are control signals
When X ₀ and X ₁ are input, shift signal S
The shift operation is performed in synchronization with the control signals X ₀ ,
It has a function of reading into the information transferred through the bidirectional gate 5 without performing a shift operation when _X1 is not input.

Next, the operation of FIG. 2 will be explained. Random access can be performed in the same manner as in the conventional example. In addition, when reading out information in M columns (M x m bits) continuously, the information stored in the i-th column is first read out from the sense amplifier and digitizer using column addresses (A ₀ , A ₁ ,...A _o ). Read out to driver 4 and send gate signal
The information is transferred to the shift register side by _Gs . Here, if X ₀ is input without inputting the control signal X ₁ , the information on the i-th column that has already been read out is read into the shift register 60, and in synchronization with the shift signal S, (i, 1), ( i,2),...,(i,
m) is obtained from the output terminal OUT. Furthermore, before the continuous reading of the information in the i'th column is completed, input the column address (A ₀ , A ₁ ,...A _o )' to be read next, and read the information stored in the i'th column to the sense amplifier and digit. - Can be transferred to the shift register side through the driver 4 and bidirectional gate 5. At this time, since the control signal X ₁ is not input, the information in the i'th column is read into the shift register 61. Therefore, when all the information in the i-th column is read out from the shift register 60, the control signal
If you input X ₁ instead of X ₀ , the i'th column information read into the shift register 61 will be sent to the output terminal.
Obtained from OUT. Similarly, shift register 61
While reading information from the shift register 60, a new column address can be entered to load the shift register 60 with new information for that column. In this way, the control signal X ₀ ,
By alternately switching the shift operations of shift registers 60 and 61 using X ₁ , information covering M columns can be transferred.
Smooth continuous reading without waste becomes possible.

The time T _r ′ _M required for continuous reading of M columns (M×m bits) according to the present invention is T _r ′ _M = T _r + T _p + M・m・T _s , which is compared to the case of the conventional example described above. and (M
-1) The time required for reading is shortened by T _p , and a smooth reading operation synchronized with the shift signal S can be obtained.

The present invention has a sense amplifier and a digit amplifier in each row.
Widely useful for general memory with drivers. Furthermore, the same argument holds true no matter what kind of element is used, whether MOS or bipolar.

Furthermore, input lines to the outside of the shift registers 60 and 61 can be separated to simplify access to the shift registers 60 and 61.

Furthermore, if a signal for switching the shift direction is newly added to the shift registers 60 and 61 and used as a bidirectional shift register, the wiring to the input/output section switching device can be reduced.

Furthermore, by providing the bidirectional gate 5 with an information switching function and deciding which of the two sets of shift registers 60 and 61 to exchange information with, the control of the shift registers 60 and 61 can be made easier. You can also do it.

As described above, the present invention enables efficient, smooth, and high-speed operation for accessing several columns of consecutive addresses by simply adding a few circuits and control means to a conventional semiconductor memory device. It has a tremendous effect in that the speed at which one bit or one column of information can be read is no different from that of the conventional method.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of a conventional semiconductor memory device, and FIG. 2 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention. In the figure, 1 is a column decoder, 2 is a memory cell matrix, 3 is a row decoder, 4 is a sense amplifier and digital driver, 5 is a bidirectional gate, 6, 60, and 61 are shift registers, and 7 is an input/output section. The switching device 8 is an input/output buffer.

Claims (1)

[Claims] 1. At least a memory cell matrix, a column selection drive device for the memory cell matrix, a row selection drive device for the memory cell matrix, and a sense amplifier provided corresponding to each row of the memory cell matrix. and a digit driver, two sets of shift registers that are shiftable in the column direction and are provided in parallel with one bit each corresponding to each row of the memory cell matrix, and the sense amplifier and the digit driver, or the two sets of shift registers. and an input/output section switching device for selectively connecting input/output sections to a shift register, and when the two sets of shift registers are used to continuously read out information stored in the memory cell matrix, During continuous reading from the first shift register (second shift register), information is transferred from the memory cell matrix to the second shift register (first shift register), and the first shift register Register (second shift register)
As soon as the information reading from the second
1. A semiconductor memory device comprising a drive means for reading information from a shift register (first shift register).