JP3183167B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a block write function.

[0002]

2. Description of the Related Art In general, a block write function applied to a semiconductor memory device having a block write function is defined as a mask register using data of a mask register and data of a color register set in advance. When the data is all set to the write operation state, it means that the data of the color register can be simultaneously written to a plurality of column addresses. The block write operation of the conventional semiconductor memory device having the block write function will be described.

FIG. 7 is a block diagram showing a configuration of a conventional semiconductor memory device having a block write function. FIG.
As shown in FIG. 1, in this conventional example, a row address strobe signal 101, a column address strobe signal 102,
Write enable signal 103, special function enable signal 104, and addresses A ₀ and A
_1, ..., a control circuit 20 which receives the A _7, control the row address select control signals 107 and the row address is output from the circuit 20 XA _0, XA _1, ..., enter the XA _7, the word line The selection signals 108-0, 108-2, ...
.., Row address selection circuit 2 that outputs 108-255
1, a block write mode determination signal 109 also output from the control circuit 20, and column addresses YA ₀ , Y
A ₁ ,..., YA ₇ and column mask signals MA ₀ , M
A ₀ ,..., MA ₇ are input, and digit line selection signal 1 is input.
Column address selection circuit 24 for outputting 11-0 to 111-255, and input of word line selection signals 108-0, 108-2,..., 108-255 and digit line selection signals 111-0 to 111-255 In response to this, a memory cell array 23 for writing / reading data to / from a corresponding memory cell,
It is connected by a write bus 112 and amplifies and outputs the data input signal 105 at the time of data writing (write).
At the time of data reading (reading), the read / write amplifier 22 amplifies data output from the memory cell array 23 and outputs the amplified data as a data output signal 113. This is an example of a configuration in which color register data is simultaneously written in correspondence with eight column addresses during operation.

In FIG. 7, when writing / reading data during a normal operation, a row address / strobe signal 101, a column address /
Strobe signal 102, write enable signal 103
And special function enable signal 1
04, the address _{A 0, A 1, ......,} A 7 is input to the control circuit 20, from the control circuit 20, a row address selection control signal 107 and the row address XA _0, XA
_1, ..., row address XA ₇ is output selection circuit 2
1 is input. The row address selection circuit 21 receives these signals and addresses and receives word line selection signals 108-0, 108-1, 108-2,...
, 108-255, a word line selection signal corresponding to one row address is selected and output, and input to the corresponding memory cell array 23. On the other hand, the control circuit 2
From 0, the "L" level block write mode determination signal 109, the column addresses YA ₀ , YA ₁ ,.
A ₇ and column mask signal _{MA 0, MA 0, ......,} M
A _{7 is} also output and is input to the corresponding column address selection circuit 24. In the column address selection circuit 24, receiving these signals and addresses,
Digit line selection signals 111-0, 111-1,..., 1
A digit line selection signal corresponding to one column address out of 11-255 is selected and output, and input to the corresponding memory cell array 23.

At the time of writing a data signal, an external data input signal 105 is input to a read / write amplifier 22, and the level is controlled by a data input / output level control signal 106 output from a control circuit 20.
The data is input to the memory cell array 23 via the read / write bus 112 and is written to the memory cells in the memory cell array 23 selected by the row address selection circuit 21 and the column address selection circuit 24. When reading data signals, the row address selection circuit 21 and the column address selection circuit 24 are used.
Is held in the memory cell in the memory cell array 23 selected by the read / write bus 1
And read out via read / write amplifier 22
, And is output as a data output signal 113 to the outside.

In the block write operation, similarly to the normal operation, a row address strobe signal 101,
Column address strobe signal 102, write enable signal 103, special function enable signal 104, and addresses A ₀ , A ₁ ,.
_7, the control circuit 20 outputs a row address selection control signal 107, row addresses XA ₀ , XA
_1, ......, XA _7, active block write mode determination signal 109, a column address YA _0, YA _1, ...
..., YA ₇ and column mask signal MA _0, MA _0, ...
..., and MA ₇ is output, as shown in FIG. 6, is input to a row address selection circuit 21 and the column address selection circuit 24 correspond respectively. However, during the block write operation, as described above, the block write
The mode determination signal 109 is input to the column address selection circuit 24 as an active level signal.

The row address selection circuit 21 outputs word line selection signals 108-0, 108-1, 108-2,.
, And a word line selection signal corresponding to one of the addresses 108-255 is selected and output, and input to the memory cell array 23. In addition, upon receiving the "H" level block write mode determination signal 109 from the column address selection circuit 24, the digit line selection signals corresponding to the eight column addresses are collectively output as digit line selection signals. At the same time, and input to the memory cell array 23. That is, in the column address selection circuit 24, the digit line selection signals 111-0 to 111-255 correspond to eight column addresses in response to the input of the "H" level block write mode determination signal 109. Digit line selection signal “111-0, 1
11-1,..., 111-7 "," 111-8, 111 "
-9, ......, 111-15 ", ......," 111-2 "
48, 111-249,..., 111-256 "are individually output simultaneously and input to the corresponding memory cell array 23. Therefore, at the time of block write write, an external data input signal 105 is input to the read / write amplifier 22 and the control circuit 20
The word line select signal output from the row address select circuit 21 is input to the memory cell array 23 via the read / write bus 112 under the level control of the data input / output level control signal 106 output from the read / write bus 112. ,
And 8 output by the column address selection circuit 24.
Data is simultaneously written to a plurality of memory cells selected by a plurality of digit line selection signals corresponding to a column address. That is, the present as the conventional column address control function corresponding to the memory cell array 23, the address A _0, A ₁ to the control circuit 20 from the outside, ..., in response to the input of A _7, these addresses Out of these, only one address input is selected, whereas in the block write cycle, eight address inputs are selected at a time, and the memory cell array corresponding to these addresses is selected. Eight data from 23 are written simultaneously. Therefore, the time required for writing data is only 1/8 the time required for the normal operation. That is, the data writing speed to the memory cell array 23 is increased as compared with the normal operation.

In a case where data in a certain memory area in the memory cell array 23 is held as it is and all data in the other memory areas are deleted, a so-called mask function is used. Mask data exists for each of the eight column addresses, and the correspondence between the mask data and the column addresses is as shown in the correspondence table of FIG. In other words, the column address [8 _j +0,8 _j +1,8 _j +2,
_{8 j +3,8 j +4,8 j +5,8 j} +6,8 j +7
(J = 0, 1, 2,..., 31)], the mask data is [0, 1, 2, 3, 4, 5, 6, 7, 7] ] Is used. That is, use "0" as the mask data to the column address 8 _j, until the mask data "7" to the column address 8 _j +7 is used, corresponding to each column address, respectively Figure As shown in the correspondence table of FIG. 8, one bit of mask data is used.

In FIG. 7, a column address selection circuit 2
4, upon receiving the “H” level block write mode determination signal 109, as in the case of the above-described block write operation, the digit line selection signals 111-0 to 111-255 include Digit line selection signals “111-0, 111-1,
......, 111-7 "," 111-8, 111-9, ... "
…, 111-15 ”, ………,“ 111-248, 1
11-249,..., 111-256 "are individually output simultaneously corresponding to the respective mask areas.
Input to array 23. Therefore, as in the case of the block write operation, the row address selection circuit 21
The data held in a plurality of memory cells selected by a plurality of digit line selection signals corresponding to the word line selection signal output from the memory device and the eight column addresses output from the column address selection circuit 24 are stored in the mask.・ Erased by data. Also in this case, the mask processing speed is improved by collectively inputting a plurality of digit line selection signals corresponding to the eight column addresses.

[0010]

In the above-described conventional semiconductor memory device having a block write function, the number of digit line selection signals simultaneously output from the column address selection circuit during the block write operation is determined in advance. It is defined by the set number of column address divisions. In the case of the above-mentioned conventional example, the number of digit line selection signals simultaneously selected for eight column addresses is eight.
One bit of the mask data corresponds to each column address specified in the book. As a result, at the time of block write operation, batch data write is performed in units of eight column addresses, and the degree of improvement in the block write operation speed and the operation speed of mask processing is 8 in the case of the conventional example. There is a drawback that it is limited by the digit line selection signal of the book, and no further improvement is possible.

[0011]

According to the semiconductor memory device of the present invention, a row address strobe signal, a column address strobe signal, a write enable signal,
Outputs row address signal, column address signal, column mask signal, row address selection control signal, block write mode determination signal, segment mode determination signal, etc., in response to input of special function enable signal and address signal A row address selection circuit for receiving and receiving the row address signal and the row address selection control signal to generate and output a word line selection signal; a column address signal, a column mask signal, a block write A column address selection circuit for generating and outputting a digit line selection signal in response to the input of a mode determination signal and a segment mode determination signal; and a word line selection signal and a digit line selection signal for writing or reading data. Multiple specified by signal And a memory cell array formed with memory cells. In normal operation, the block write mode determination signal and the segment mode determination signal are deactivated to thereby enable the word The memory cell specified by the line select signal and the digit line select signal functions as a single memory cell, and when a column address is specified by a column address division during a block write operation, A word line selection signal and a digit line selection signal for simultaneously selecting a plurality of digit lines set at the time of block write operation by activating a write mode determination signal and deactivating the segment mode determination signal Set the memory cell specified by the block write When a column address is designated by a segment division while activating the function of the block write mode determination signal and the segment mode determination signal, It is characterized in that a memory cell specified by a line selection signal and a digit line selection signal for simultaneously selecting a plurality of digit lines set as one segment is defined as a plurality of memory cells set in one segment. And

[0012] The column address selection circuit comprises N
(= 2 ⁿ ) column address block write operation and N
^In response to ^2- column address segment write operation,
The column address selection circuit outputs a column address signal Y
The least significant n bits (YA ₀ , YA ₁ ,..., YA) corresponding to the input of A _i (i = 0, 1, 2,...
_n-1 ) and (YA _n, YA _{n + 1} ,..., Y
A _2n-1), ............, (............, a plurality of column pre-decoder for decoding outputs a column address signal is divided into YA _m) as inputs, respectively, the segment mode decision signal input and The column mask signal MA
_i (i = 0, 1, 2,..., N−1) in response to the input of jN
(J = 0, 1, 2,..., 2 ^m / N) A first group of selectors (A) for outputting a column mask signal MA ₀ corresponding to a digit line of a column address, and a (jN + 1) column address Column mask signal MA ₁ corresponding to the digit line of
, A second group of selectors (A) that output
[(J + 1) N-1] (N- ₎ which outputs a column mask signal MA _(N-1) corresponding to the digit line of the column address.
1) and a selector (A) group. When a segment / block write operation is performed, a predetermined segment / group is selected.
A first selector (B) group for outputting a column mask signal MA ₀ corresponding to a digit line of an N-bit column address starting from the value of j, which is an integral multiple of N, via a mode determination signal; A second group of selectors (B) that output a column mask signal MA1 corresponding to a digit line of an N-bit column address starting from the value of j, which is an integer multiple of N + ₁ ,. _(N-1) -th selector (B) which outputs a column mask signal MA _(N-1) corresponding to a digit line of an N-bit column address starting from the value of j which is an integer multiple of N-1. First, second,..., Divided into groups
At the time of the (2 ⁿ -1) ^th selector and the block write operation, all the outputs of the column predecoder of the n least significant bits of the column address input are set to the selected state, and the N-bit column mask signal corresponding to each digit line is set. An enabled signal, a plurality of column decoders for decoding a column predecoder output for an address higher than the output of the least significant n bit column predecoder, and a column address input during a segment block write operation And a signal that enables a column mass signal corresponding to each digit line, and a column pre-tecoder output for an address higher than the least significant 2n bits. And a column decoder.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a row address strobe signal 101, a column address strobe signal 102, a write enable signal 103,
The control circuit 1 receives the special function enable signal 104 and the addresses A ₀ , A ₁ ,..., A ₇ , the row address selection control signal 107 output from the control circuit 1 and the row addresses XA ₀ , XA _1. …
.., XA ₇ are input, and word line selection signals 108-0,
, 108-255, a block write mode determination signal 109, a segment mode determination signal 110, and column addresses YA ₀ , YA1, which are also output from the control circuit 1.
..., YA ₇ and column mask signals MA ₀ , M
A ₀ ,..., MA ₇ are input, and digit line selection signal 1 is input.
Column address selection circuit 5 for outputting 11-0 to 111-255, and input of word line selection signals 108-0, 108-2,..., 108-255, and digit line selection signals 111-0 to 111-255 In response to this, the memory cell array 4 for writing / reading data to / from a corresponding memory cell is connected to the memory cell 4 by a read / write bus 112, and the data input signal 105 is amplified during data writing (writing). At the time of data reading (reading), the read / write amplifier 3 amplifies the data output from the memory cell array 4 and outputs it as a data output signal 113.
This is an example of a configuration in which color register data is simultaneously written corresponding to eight column addresses during a block write operation. The difference of the present embodiment from the above-described conventional example is that, in the present embodiment, the segment mode determination signal 110 is newly output from the control circuit 1 and input to the column address selection circuit 5.

In FIG. 1, when writing / reading data during normal operation, a row address strobe signal 101, a column address strobe signal 102, a write enable signal 103, a special function enable signal 104, an address _{a 0, a 1, ......,} a 7 is input to the control circuit 1, from the control circuit 1, a row address selection control signal 107 and the row address XA _0, XA _1, ......, XA
₇ is input to the row address selection circuit 2 and the "L" level block write mode determination signal 10
9, also "L" level of the segment mode determination signal 110, a column address _{YA 0, YA 1, ......,} YA 7
And column mask signals MA ₀ , MA ₀ ,..., MA ₇
Are also output, and the corresponding column address selection circuit 5
Is input to

In this state, as in the case of the normal operation in the above-described conventional example, the word address selection signals 108-0, 108-1, 108-2,... The word line selection signal corresponding to one of the row addresses is selected and output, and is input to the corresponding memory cell array 4.
In response to the input of the “L” level block write mode determination signal 109 and the “L” level segment mode determination signal 110, the column address selection circuit 5
From the digit line selection signals 111-0, 111-1,
,..., A digit line selection signal corresponding to one column address of 111-255 is selected and output, and input to the corresponding memory cell array 23. Therefore, data writing / writing corresponding to the memory cell selected by the word line selection signal and the digit line selection signal is performed.
A read operation is performed, and the contents of the operation are the same as in the above-described conventional example.

Next, during the block write operation in the present embodiment, the block write mode determination signal 109 output from the control circuit 1 becomes "H" level, and the segment mode determination signal 110 becomes "L". And output to the column address selection circuit 5. The other addresses and signals output from the control circuit 1 are the same as those in the conventional example. A row address strobe signal 101, a column address strobe signal 102,
Write enable signal 103, special function enable signal 104, and addresses A ₀ and A
_1, ..., in response to the input of A _7, from the control circuit 1, a row address selection control signal 107, a row address X
_{A 0, XA 1, ......,} XA 7, "H" level block write mode determination signal 109, "H" level of the segment mode determination signal 110, a column address YA _0,
YA ₁ ,..., YA ₇ and the column mask signal MA ₀ ,
MA ₀ ,..., MA ₇ are output and input to the corresponding row address selection circuit 2 and column address selection circuit 5, respectively. The row address selection circuit 2 outputs word line selection signals 108-0, 108-1, and 108.
,..., 108-255, a word line selection signal corresponding to one address is selected and output, and input to the memory cell array 4.

Next, the internal operation of the column address selection circuit 5 will be described with reference to FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG. FIG. 2 shows one of the column address selection circuits 5.
FIG. 3 is a block diagram showing a configuration of the embodiment, and includes column predecoders 6 to 8 and column decoders 9-0 to 9-25.
5 and selectors 10-1 to 10-255. FIGS. 3 and 4 are circuit diagrams showing the internal configurations of the column decoders 9-0 and 9-1, respectively, and show an inverter 11 and NAND gates 12 and 13 respectively.
, And 14, an OR gate 15, and an AND gate 16. FIG. 5 is a circuit diagram showing the internal configuration of the selector 10-1. The selector 10-1 includes an inverter 17 and transfer gates 18 and 19.
Note that column decoders 9-0, 9-9,..., 9-25
For No. 5, there is no corresponding selector, and therefore no column mask signal is output from the selector. FIG. 6 is a diagram showing a column address / mask data comparison table in the present embodiment.

In FIG. 2, the column addresses YA ₀ , YA ₁ ,..., YA ₇ inputted from the control circuit 1 are divided and inputted to the column predecoders 6, 7 and 8, respectively. For the column predecoder 6,
From the least significant bit of the column address, the number of column addresses that enables selection of digit lines corresponding to the number of column addresses to be written at one time during the block write operation is input. In the present embodiment, since writing of data for 8 column addresses is performed at once,
The column address input to the column predecoder 6 is a 3-bit column address including YA ₀ , YA _1, and YA _2. , Predecode addresses PYA ₀₀ , PYA ₀₁ ,..., PYA ₀₇ . The column addresses input to the column predecoder 7 are YA ₃ , YA ₄ and Y
A column address of 3 bits containing A _5, receives the column address input, a column predecoder 7
, The predated addresses PYA ₁₀ , PYA ₁₁ , ...
..., PYA ₁₇ is output. Further, in the column predecoder 8, the column predecoders 6 and 7
In the above, decoding is performed for an upper column address input that is not decoded. In the present embodiment, since the memory cell array has a 256-digit configuration, a 2-bit column address including the column addresses YA ₆ and YA ₇ is input to the column predecoder 8. From the column predecoder 8, the blow decode addresses PYA ₂₀ , PYA ₂₁ , PY
A ₂₂ and PYA ₂₃ is output.

Next, the column decoder 9 included in FIG.
-0 will be described. FIG. 3 shows the column decoder 9-0.
FIG. 3 is a circuit diagram showing the configuration of FIG. In FIG. 3, the control circuit 1
The input column mask signal MA ₀ is a column mask signal used in both the block write operation and the segment block write operation. In the case of the normal operation, the block write mode determination signal 109 and The segment mode determination signals 110 are both input at the “L” level, the output of the NAND gate 12 is fixed at the “H” level, and the column mask signal MA ₀
Input level becomes “Don't Care” and NAN
The outputs of the D gate 13 and the OR gate 15 have the levels of the predecode addresses PYA ₀₀ and PYA ₁₀ made valid, so that the output of the AND gate 16 has the digit line selection signal 111-which has "Care" all input addresses.
0 is output. Next, in the case of a block write operation, the block write mode determination signal 109 becomes "H" level and the segment mode determination signal 110 becomes "L" level, whereby the output of the NAND gate 12 becomes the column mask signal. When the level of MA ₀ is enabled, the level of the least significant bit of the predecode address PYA ₀₀ becomes “Don't Care”, and the NAND gate 13
Is fixed to the “H” level, and the predecode address PYA ₁₀ input to the OR gate 15 becomes “Care”.
Is ", digit line selection signal 111-0 corresponding to the column mask signals MA ₀ predecode address PYA ₁₀ and PYA ₂₀ is outputted. Further, in the case when the segment block write operation, the block write mode Determination signal 109 and segment mode determination signal 1
10 becomes both "H" level, the output of NAND gate 14, together with the level of the column mask signal MA ₀ is enabled, is fixed to the output also "H" level of the OR gate 15, the predecode address PYA ₀₀ and P
Level YA ₁₀ is "Do not Care", and the digit line selection signal 111-0 corresponding to the column mask signals MA ₀ and predecode address PYA ₂₀ is output.

Further, like the column decoders 9-1 to 9-8, digit lines using different column mask signals are selected corresponding to each of the block write mode / segment block write mode. FIG. 4 shows the internal configuration of the column decoder. The operation of the column decoder in this case is that the column mask signal MS ₁ (〜MS ₈ ) is a column mask signal output from the selectors 10-1 to 10-8 and the like as shown in FIG. For other operations,
This is exactly the same as the case of the column decoder 9-0 in FIG.

Next, the selector 10-1 will be described with reference to FIG. In FIG. 5, the segment mode determination signal 110 input from the control circuit 1 is transmitted to the PMOS side of the transfer gate 18 and the transfer gate 19.
Input to the NMOS side of the
The inverted output of the mode determination signal 110 by the inverter 17 is connected to the NMOS side of the transfer gate 18 and
It is input to the PMOS side of the transfer gate 19. Therefore, if the segment mode determination signal 110 is input at "L" level, the column mask signal MA ₁ is selected and the column mask signal M for block write operation
Is output as S _1, also in the case where the segment mode determination signal 110 is input at "H" level, is selected column mask signal MA ₀ for segment write operation output as a column mask signal MS ₁ Is done. The Karamumasukuu No. MS ₁ is sent to the corresponding column decoder. This is the same for the other selectors. The column mask signal for segment write / block write in this case will be described with reference to FIGS.

FIG. 6 is a comparison table showing a relationship between column mask signals MA _{0 to} MA ₇ and column addresses corresponding to respective digit lines during a segment write operation. In FIG. 6, a column mask signal MA0 is used for 8 bits starting from k = ₀ , 8, 16, and 24. Specific column addresses using the column mask signal MA0 are ₀ to 7 when k = 0, and k =
64 to 71 when 8; 128 to 13 when k = 16
5, 192 to 199 when k = 24. Moreover, the specific column addresses using a column mask signals MA _1, is 8-15 when k = 1, 72-79 at the time of k = 9, 136~143 when the k = 17, k =
In the case of 25, it is 200-207. Thus, for sequential column addresses, MA ₇ is associated a column mask signal MA _0. FIG. 8 is a comparison table showing the relationship between the column mask signals MA _{0 to} MA ₇ during the block write operation and the column addresses corresponding to the respective digit lines. In this case, the column mask signal M
Specific column addresses using A ₀ are 0,8,
16, 24, ............, is 248, also specific column addresses using a column mask signals MA _1,
1, 9, 17, 25,..., 249.

[0024] Thus, the plurality of column decoder shown in FIG. 2, the predecode address PYA ₀₀ to P
_{YA 07, PYA 10 ~PYA 17,} PYA 20 ~PYA 23, and block write mode / column mask signals in the segment write mode is used in common MA ₀ ~
MA _7, block write mode / segment write
If the digit line to use the column mask signal MA ₀ to MA ₇ to be used as a different column mask signals in the mode, the column mask signal M which has passed through the selector
_{S 1, ........., MS 7,} MS 8, ........., MS 15 is input, the digit line selection signal 11 corresponding to the respective digit line
1-0, 111-1,..., 111-7, 111-
8,..., 111-17 are output.

[0025]

As described above, according to the present invention, by switching the level of the segment write mode at the time of the block write operation in the semiconductor memory device, the column address selection circuit can change the lower n bits of the column address input, or By configuring the lower 2n bits of the column address to be "Don't Care", the address length for block writing can be varied simultaneously by the power of 2n or 2n, and the segment write mode can be used. In some cases, there is an effect that the block write operation speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a column address selection circuit according to the embodiment.

FIG. 3 is a circuit diagram (1) showing a column decoder in the present embodiment.

FIG. 4 is a circuit diagram (2) showing a column decoder according to the embodiment;

FIG. 5 is a circuit diagram showing a selector according to the embodiment.

FIG. 6 shows a column address / mask in this embodiment.
It is a figure which shows a data contrast table.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a diagram showing a column address / mask data comparison table in a conventional example.

[Explanation of symbols]

1,20 control circuit 2,21 row address selection circuit 3,22 read / write amplifier 4,23 memory cell array 5,24 column address selection circuit 6-8 column predecoder 9-0-9-255 column Decoder 10-1 to 10-255 11, 17 Inverter 12 to 14 NAND gate 15 OR gate 16 AND gate 18, 19 Transfer gate 101 Row address strobe signal 102 Column address strobe signal 103 Write enable signal 104 Special Function enable signal 105 Data input signal 106 Data input / output level control signal 107 Row address selection control signal 108-0 to 108-255 Word line selection signal 109 Block write mode determination signal 110 Segment Mode decision signal 111 over 0-111 over 255 digit line selection signal 112 read write bus 113 data output signal A ₀ to A ₇ addresses XA ₀ ~XA ₇ row address YA ₀ ~YA ₇ column address PYA ₀₀ ~PYA ₂₃ Pre decode address _{MA 0 ~MA 7, MS 1 ~MS} 9 ~MS 15 ~MS 248 ~
MS ₂₅₄ column mask signal

Claims (2)

(57) [Claims] An external device receives a row address strobe signal, a column address strobe signal, a write enable signal, a special function enable signal, an address signal, and the like, and receives a row address signal, a column address signal, and a column signal. A control circuit for outputting a mask signal, a row address selection control signal, a block write mode determination signal, a segment mode determination signal, and the like; and a word line selection signal receiving the input of the row address signal and the row address selection control signal. Receiving and receiving a column address signal, a column mask signal, a block write mode determination signal, and a segment mode determination signal, and generating and outputting a digit line selection signal. A column address selection circuit; A memory cell array formed with a plurality of memory cells specified by the word line select signal and the digit line select signal when data is written or data is read. In some cases, a memory cell specified by the word line select signal and the digit line select signal is defined as a single memory cell by deactivating the block write mode determination signal and the segment mode determination signal. function to be, at the time of block write operation, the block write mode decision signal activated by deactivating the segment mode decision signal, said word line selection signals and block write operation Digit line selection to select multiple digit lines set at the same time The number of the plurality of memory cells specified by the item, and sets the number of the plurality of memory cells which is set at the block write operation, the segment block write operation
It is designated by the activated functional block write mode decision signal and the segment mode decision signal, digit line selection signals for selecting simultaneously a plurality of digit lines to be set as the word line selection signals and one segment the number of the plurality of memory cells, the segments
Block write operations of a plurality of memory cells to be set
A semiconductor memory device characterized by being set to a number . 2. The method according to claim 1, wherein the column address selection circuit comprises N (=
2 ⁿ ) In response to the column address block write operation and the N ² column address segment write operation, the column address selection circuit sets the column address signal YA _i
The least significant n bits (YA ₀ , YA ₁ ,..., YA _n−1 ) corresponding to the input of (i = 0, 1, 2,..., _M )
And (YA _n, YA _{n + 1} ,..., YA _2n−1 ),.
A plurality of column pre-decoders which receive and decode column address signals divided into..., (..., YA _m ), respectively, the segment mode determination signal input and the column mask signal MA _i (i = 0, 1, 2,..., N−1) during the block write operation, respectively jN (j = 0, 1, 2,..., 2 ^m /
A first selector group (A) for outputting a column mask signal MA ₀ in response to the digit line N) column address,
(JN + 1) second selector for outputting a column mask signals MA ₁ corresponding to the column address of the digit line (A)
,...,..., (N−1) -th selector (A) group that outputs a column mask signal MA _(N−1) corresponding to the digit line of the [(j + 1) N−1] column address. At the time of segment / block write operation, each corresponds to a digit line of an N-bit column address starting from the value of j, which is an integral multiple of N, through a predetermined segment mode determination signal. A first group of selectors (B) for outputting a column mask signal MA ₀ , and a column mask signal MA ₁ corresponding to a digit line of an N-bit column address starting from the value of j which is an integral multiple of N + _1. Output the second
..,..., And a column mask signal MA _(N−1) corresponding to a digit line of an N-bit column address starting from the value of j that is an integer multiple of _N−1. ,..., The (2 ⁿ -1) ^-th selector which is divided into a (N-1) ^-th selector (B) group that outputs A signal in which all outputs of the least significant n-bit column predecoder are selected and an N-bit column mask signal corresponding to each digit line is enabled, and a signal higher than the output of the least significant n-bit column predecoder Column predecoder output for multiple addresses
A decoder, a signal in which a 2n-bit least significant pre-decoder output of a column address input is selected in a segment block write operation, and a column mask signal corresponding to each digit line is enabled; 2. The semiconductor memory device according to claim 1, further comprising: a plurality of column decoders for decoding a column pre-tecoder output for a higher-order address.