JPS61117789A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable data writing/reading at high speed and to make data writing/reading simultaneously and asynchronously by making writing and reading of data through a writing register and a reading register respectively. CONSTITUTION:When a writing pulse is inputted, groups of switches WDS1, WDS2 are made conductive selectively by the decoding signal of a column address signal WCA, and writing data are transferred to a register WR1 or WR2 bit by bit. When a register becomes full, writing is started to another register and data in the filled up register are written on a memory cell 3. On the other hand, at the time of reading, data in the cell 3 are transferred by a reading pulse to registers RR1, RR2. When a register becomes empty, reading of another register is started, and at the same time, data are transferred from the cell 3 to the empty register.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memories.

[Conventional technology]

Conventionally, PIFO (First
In, First 0ut) memory. This P
IFO memory is a memory that outputs data in the order in which it is input, and this operation is similar to normal random access memory (
This can also be realized in a RAM (RAM) by sequentially incrementing or decrementing address input signals to perform writing/reading. That is, if writing is performed sequentially from the first address of the memory cell to the final address, and further reading is performed from the first address of the memory cell to the final address, the memory becomes similar to a FIFO memory.

[Problem that the invention seeks to solve]

However, such FIFO memory cannot be used with normal RA.
If M is implemented by giving a certain rule only to the order in which addresses are applied, the problem is that data is written/read at the write speed or read speed of the RAM, which takes time, and it is not possible to write/read at the same time. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that can be written/read at high speed and that can be written/read simultaneously.

[Means for solving problems]

In order to solve the above problems, the present invention provides a plurality of write data registers arranged between a write data input terminal and a plurality of memory cells and storing write data, and a read data output terminal and a plurality of memory cells. a plurality of read data registers in which read data is stored, a first storage means for storing write data input from the write data input terminal in the plurality of write data registers, and a plurality of write data registers; a first transfer means for collectively transferring the write data stored in the memory cell to each memory cell for each write data register; A second storage means for storing data in each data register at once, a second transfer means for transferring read data stored in a plurality of read data registers to a read data output terminal, and a write data register is full when data is written. When the write data register becomes full, a data write command to another write data register is output to the first storage means, and a data transfer command from the write data register that is full is output to the first transfer means, and the data is read out. When a read data register becomes full, a data read command to another read data register is output to the second storage means, and a data transfer command from the read data register that has become full is output to the second transfer means. It is equipped with a control circuit that outputs to the

That is, in the semiconductor memory of the present invention, data is written to the write data register, and data read is performed from the read data register.As a result, high-speed data writing/reading is possible.
Furthermore, data writing/reading can be performed simultaneously and asynchronously.

In an embodiment of the present invention, the plurality of memory cells are composed of dynamic cells and have a built-in refresh circuit. In another embodiment of the present invention, a plurality of write data registers and a plurality of read data registers are provided in parallel with respect to a plurality of memory cells. In yet another embodiment of the present invention, the plurality of memory cells are divided into a plurality of sub-7 arrays for each of the plurality of columns, and the plurality of write data registers and the plurality of read data registers are arranged, one for each subarray. and the selection of row lines of the plurality of memory cells is controlled for each subarray.

〔Example〕

FIG. NIJ1 shows a configuration diagram of a semiconductor memory according to an embodiment of the present invention. In the same figure, memory cell subarray 1.
2 are memory cells 3 arranged in N rows and N/2 columns, respectively.
Consisted of. Memory cell 3 is connected to word line Wnl (
! 11 = 1xN) bit line Bml (41, 1-N
/2) and the word line tn2 (nz = 1''
N) and beat line 8112 (12=N/2+1
~M) (7) One piece is placed at each intersection point.

Row decoders RO1 and RD2 each receive a block select signal BSI.

BS2 Te Controlled, Word 1iWnl, 111
! ! 2 selectively set to high level. Block select signal SSt.

BS2 is made of, for example, the most significant bit of a column address signal. The word length of write data registers WRI and WR2 is I'l/2, which corresponds to the number of bit lines. The switch groups -051 and WDS2 each connect the input terminal Din and each word of the write data registers WRI and WR2, and are composed of 8M72 switches that are selectively rendered conductive by the decode signal of the write column address signal WCA. Switch groups -Tl and -T2 respectively connect write data registers WR1 and WR2 and memory cell sub-array 1. z
The bit lines B1+B2 are connected to each other, and the switch is made up of 72 switches that are simultaneously turned on by the transfer signals φWTI and φWT2. Read data register RR1
, RR2 has a word length of N/2, which corresponds to the number of bit lines. Switch groups RTI and RT2 are respectively bit line 8 layers in the memory cell subarray 1.2.

8m2 and read data registers RRI and RR2, and is composed of N/24VI switches that are simultaneously turned on by transfer signals φRTI and φRτ2. The switch groups RDSI and RDS2 are connected to the read data registers RRI and RR2 and the output terminal Dout 1, respectively.
1. Consisting of N/2 switches that are selectively rendered conductive by the decode signal of the read column address signal RCA. Refresh address counter RFA generates a refresh address and outputs it to multiplexer IIIUx. The refresh timer RF consists of a ring oscillator, a counter, etc., and transmits the refresh request signal FRQ to the arbitration circuit AR for each refresh cycle.
Output to B. Arbitration circuit [8 is a multiplexer MUX of the detection signal WRQ and RRQ refresh request signal FRQ if they are input separately.
If they are input at the same time, these signals are sent to the multiplexer MUX in order.
Transfer to. Note that the detection signals WRQ and RRQ are output from a detection circuit (not shown) when the logic level of the most significant address signal of the write column address signal WCA and the read column address signal RCA changes, respectively. When multiplexer MUX receives detection signals WRQ, RRQ, and refresh request signal FRQ from arbitration circuit ARB, it outputs write row address signal WRA, read row address signal %RRA, and refresh address to row decoders 8 l and RD2, respectively.

The write operation, read operation, and refresh operation of the two embodiments will be explained in detail below.

(1) First, the write operation will be explained. When performing a write operation, a write pulse is applied to a write terminal (not shown) and write data is applied to an input terminal Din. At this time, write column address signal WCA,
The write row address signal may be applied externally in order (for example, incremented one bit at a time), or an internal write address counter may be provided to increment the address output each time a write pulse is input. It may be configured as follows.

When a write pulse is input, the switch group WOSI or WDS2 is selectively rendered conductive by the decode signal of the write column address signal WCA, and the write data is transferred bit by bit to the write data register WRI or WR2. Now, if writing starts from address 1, the write data register WRI will accumulate data in order from the left, and after writing M/2 times, the write data register wR1 will be full, and if writing continues, the write data will be The data will be stored in write data register WR2. Switching from write data register WRI to write data register WR2 is performed by a change in logic level of the most significant address signal of write column address signal WCA, so a detection circuit (not shown) detects this and outputs a detection signal wRQ (pulse signal). ) is input to the multiplexer υX via the arbitration circuit ARB, and the write row address signal -RA is transmitted from the multiplexer MUX to the row decoders RDI and RD2. At the same time, a row decoder activation signal and a block select signal BSI (not shown) rise, and the word line Wnl(n
I=1) is the selection level.

Immediately thereafter, the transfer signal φenτ1 is activated, and the contents of the write data register WRI are transferred to the selected word line -n.
1 is written into the memory cell 3 connected to 1. Writing to the write data register WR2 is performed in parallel with the data transfer operation from the write data register W old to the memory cell 3, so when writing is performed M times, the write data register WR2 becomes full, and further writing continues. and the write data is transferred to the write data register WRI again.
will be accumulated in This write data register W
Upon switching from R2 to write data register WRI, detection signal WRQ is generated again, and arbitration circuit A
The write row address signal WRA is input to the multiplexer UX through RB, and the write row address signal WRA is input to the row decoder RDI, RΩ.
At the same time, the row decoder activation signal and block select signal BS2 rise, and the word line Wn2 (
+12=1) is the selection level. Immediately after that, transfer signal φWT2 is activated and write data register WR2 is activated.
The contents of are written into the memory cell 3 connected to the selected word line Wn2.

In this way, when one write data register becomes full, writing begins in the other write data register, and at the same time, the operation of transferring the data of the full write data register to memory cell 3 all at once is repeated, and all Writing can be continued until data is transferred to the memory cell 3 of .

(2) Next, the read operation will be explained. A read operation is performed by applying a read pulse to a read terminal (not shown). At this time, the read column address signal RCA and the read row address signal RRA may be configured to be added externally (for example, incremented one bit at a time) by a sequential chamber like the write address signal, or a read address counter may be provided internally. The address signal may be incremented each time a read request pulse is input.However, it is necessary to read in the same order as the write order.

Reading is performed by first reading the data in the memory cell 3 and transferring it to the read data registers RRI and RR2. When 0M/2 or more than M data is accumulated in the memory cell, the data is transferred to the word line Wnl (n!=1). Is the content of the connected memory cell 3 read data register l? To R1,
The contents of the memory cells 3 connected to the word line Wn2 (n2 xl) are respectively transferred to the read data register RR2. These first two read data records R
R.I.

Data transfer to RR2 is performed using write data register WRI.
, can be performed at the same time as transferring the contents of WR2 to memory cell 3. That is, write data register W
When RI becomes full, transfer signal φWTI rises and is transmitted to write data register WRI (7) and data capit line Bml (L = 1 to M/2), and at the same time, read transfer signal φRTI rises and switches When group RTI becomes conductive, write data is transferred to read data register RRI. Data transfer to read data register RR2 is performed in the same manner.

In this way, data transfer to read data register RR2 is performed in the same way. In this way, when data is transferred to read data registers RRI and RR2, it becomes possible to read them. In order to inform the outside that reading is possible, a circuit may be provided that outputs a READY signal (not shown) indicating that reading is possible. Now, when a read pulse is applied, the read column address signal RC
The switch group RDS1 or RDS2 is selectively made conductive by the decode signal A, and the read data is transferred from the read data register RRI or RR2 to the output terminal Dou.
t is transferred one bit at a time. In addition, switch group R port S
A sense amplifier SA for amplifying read data is provided between RDS2 and the output terminal Dout. Now, if reading starts from address 1, the read data register RRI will release data sequentially from the left, and after reading data 72 times, the read data register RRI will release data in order from the left.
I becomes empty of data, and if reading continues, the read data will be released from the read data register RR2. Switching from the read data register RRI to the read data register RR2 is performed by a change in the logic level of the most significant address signal of the read column address signal RCA, so a detection circuit (not shown) detects this and outputs a detection signal RRQ (pulse signal). is input to the multiplexer MUX via the arbitration circuit ARB, and the read row address signal RR is input from the multiplexer) IUX.
A is transmitted to row decoders RDI and RD2. At the same time, a row decoder activation signal and a block select signal BSI (not shown) rise, and the word line Wnl (nl=2
) is the selection level. Immediately after that, transfer signal φR
TI is activated, and the data of the memory cells 3 connected to the selected word li Wn I are transferred all at once to the write data register RRI. This memory cell 3
Since reading from the read data register RR2 is performed in parallel with the data transfer operation from the read data register RRI to the read data register RRI, the read data register RR2 becomes empty after reading has been performed M times. The data will be released from the read data register RRI again. By switching from read data register RR2 to read data register RRI, detection signal 1'iRQ is generated again, and arbitration circuit AR
The read row address signal RRA is input to the multiplexer MUX through B and is transmitted to the row decoders RDI and RD2, and the row decoder activation signal and block select signal BS2 rise, and the word line Wn2 (11
12=2) is the selection level. Immediately thereafter, the transfer signal φRT2 is activated and the selected word line Wn2 is transferred to the selected word line Wn2.
The contents of the memory cells 3 connected to each other are transferred all at once to the read data register RR2.

In this way, when one read data register becomes empty, reading starts from the other read data register, and at the same time, the operation of collectively transferring new read data from memory cells 3 to the empty read data register is repeated. , data in all memory cells 3 can be read. Note that during writing/reading, writing must always precede and reading must follow, so the addresses of the two must be compared to prevent reading from overtaking writing. If the accumulated data is O, or if the write data has not yet been transferred into the memory cell 3, a READY signal or the like may be output to the outside to prohibit reading.

(3) Finally, the refresh operation will be explained. When the refresh request signal FRQ is generated from the refresh timer RFT, this refresh request signal FI'lQ is sent to the multiplexer MUX via the arbitration circuit ARB.
is input. Then, the refresh address output from the refresh address counter RFA is transmitted to the row decoders RDI and RD2 by the multiplexer MUX. At the same time, both the row decoder activation signal and the block select signals BSI and BS2 rise, and the word line '1lnl or' corresponds to the refresh address.
dn2 is selected and refreshed. When refresh is performed, the refresh timer RF is reset and starts counting a new refresh time, and at the same time, the refresh address counter RFA increments its output by one address. All words are refreshed by repeating north.

Note that writing, reading, and refreshing are performed asynchronously, so data transfer from write data registers WRI and WR2 to memory cell 3, data transfer from memory cell 3 to read data registers RRI and RR2, and word line W+xl due to refresh. , Wn2 is selected at any time. Therefore, it is necessary to prevent these transfer operations from overlapping, and for this purpose an arbitration circuit ARB is provided. In other words, the detection signal WRQ requests to transfer the contents of the 5 write data registers R1 and WR2 to the memory cell 3.
, reads the data of memory cell 3 and writes it to data register RR.
I, Detection signal RRQ requesting to be transferred to RR2
and refresh request signal FRQ are generated simultaneously, arbitration circuit ARB performs these operations in order.

With the configuration described above, writing is performed to the write data registers WRI and WR2, and reading is performed from the read data registers RRI and RR2, so that high-speed data transfer can be performed. Furthermore, writing and reading can be performed simultaneously and asynchronously, increasing the efficiency of the memory. Also, if it is constructed using dynamic memory cells, refreshing is required.

By incorporating this, refreshing can be performed without affecting external writing/reading.

Another embodiment according to the present invention is shown in FIG. 2, in which a memory cell array 11 is composed of memory cells 3 arranged in 8 rows and M columns, and a row decoder RD selectively sets word lines Wn to a high level. Write data register WRI',
Each WR2° is M words long.

The word line is arranged in parallel with Wn. Switch group wO5
are input terminal Din and write data register WRI°,
Connect WR2° and write column address signal WCA
It is composed of 2M switches that are selectively rendered conductive by the most significant address signal WRA1 of the row address and the row address. Switch group W is write data register R1°, WR2
The data in the write data register WRY is transferred to the bit line B■ at once by the transfer signal φWTI', and the data in the write data register WR2° is transferred by the transfer signal φWT2° to the bit line Bm. are transferred to bit line B■ at once. These data transfers are performed alternately, and when data in one write data register is being transferred to memory cell 3, writing is performed in the other write data register. Read data register RRI', RR
2' each has a length of M words and is arranged in parallel to the word line Wn. The switch group RDS connects the output terminal Dout and the read data registers RRI' and RR2',
Address signal RCA and lowest row address signal RRA
It is composed of 2M switches that are selectively turned on by +. The switch group RT is composed of 2M switches that connect the bit line Bm and the read data registers RRI' and RR2°, and the data in the memory cell 3 of the word 1lWn selected by the transfer signal φRTI' is read out at once and transferred to the read data register RRI. ' and is transferred to the transfer signal φRT2°. These data transfers are performed alternately, and when data of memory cell 3 is being transferred to one read data register, reading is performed from the other read data register. The other circuit configurations are the same as the embodiment shown in FIG. The embodiment of FIG. 2 differs from the embodiment of FIG. 1 in the write data register WRI'.

R2° and read data register RRI', RR2'
A plurality of (two columns) are provided in parallel to the word line Wn.

Even with this configuration, writing is performed to the write data registers WRI' and WR2°, reading is performed from the read data registers RRI' and RR2', and one data register of each of the write and read data registers is When data is being transferred to the memory cell 3, the other data register inputs and outputs data, so that the same effect as in the embodiment shown in FIG. 1 can be obtained.

〔Effect of the invention〕

As described above in detail, according to the present invention, data is written to the write data register.

Since data reading is performed from the read data register, it is possible to speed up the writing/reading of a memory configured so that the address within the memory cell changes continuously in one direction during writing/reading, and to perform them simultaneously and asynchronously. It becomes possible to do so.

Further, when the semiconductor memory of the present invention is configured with dynamic memory cells in order to increase the capacity, there is an advantage that a refresh circuit can be incorporated without affecting writing/reading.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory according to one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment. 1.2...Memory cell sub-array 3...Memory cell 11...Memory cell array Wnl, Wn4, Wn=word line WDSI
, WDS2, WDS-/Ceat f group WRI
, WR2, WRIo, WR2°...Write data register WTI, WT2. WT'=;Cy Group RD, RDI, RD2...Row decoder RTI
, RT2. RT...Switch group RRI, RR2
, RRI', RR2'...Read data register R
DSI, RDS2. RDS...Switch group RFA
...Refresh address counter MUX...Multiplexer ARB...Arbitration circuit RFT...Refresh timer Din...Input terminal Dout...Output terminal

Claims (4)

[Claims] (1) In a semiconductor memory having a write data input terminal, a plurality of memorials arranged two-dimensionally, and a read data output terminal, the write data input terminal and the plurality of memory cells are arranged between the write data input terminal and the plurality of memory cells. a plurality of write data registers in which data is stored; a plurality of read data registers arranged between the read data output terminal and the plurality of memory cells and in which read data is stored; and input from the write data input terminal. a first storing means for storing written data stored in the plurality of write data registers in the plurality of write data registers; and a first storage means for collectively transferring the write data stored in the plurality of write data registers to each memory cell for each write data register. a second storage means for collectively storing the data transferred to each of the memory cells as read data in the plurality of read data registers for each read data register; and the plurality of read data. a second transfer means for transferring the read data stored in the register to the read data output terminal; and when the write data register becomes full during data writing, the first storing means sends a data write command to another write data register. The data transfer command from the write data register, which has become full, is output to the first
When the read data register becomes full when reading data, a data read command to another read data register is output to the second storage means, and the data from the read data register that has become full is output to the second storage means. A semiconductor memory comprising: a control circuit that outputs a transfer command to the second transfer means. (2) The semiconductor memory according to claim 1, wherein the plurality of memory cells are composed of dynamic cells and have a built-in refresh circuit. (3) The semiconductor memory according to claim 1 or 2, wherein the plurality of write data registers and the plurality of read data registers are provided in parallel with the row lines of the plurality of memory cells. (4) The plurality of memory cells are divided into a plurality of subarrays for each plurality of columns, one of the plurality of write data registers and one of the plurality of read data registers are arranged in each subarray, and the plurality of memory cells 3. A semiconductor memory according to claim 1, wherein selection of row lines is controlled for each subarray.