JPH01133282A - Dynamic memory - Google Patents

Abstract

PURPOSE:To reduce the capacity of a register and to miniaturize a memory by successively switching a bit line group to be selected by a bit line group selector every time the said selector selects and refreshes a word line over all the word lines. CONSTITUTION:A memory cell array 2 composed by grouping a memory cell 1 is divided into two bit line groups 21 and 22. First, a carrying signal outputted from a counter 6 becomes '0', a bit line group selector 7 selects the bit line group 21, and the signals from a bit line 1 to a bit line 128 are transferred to a register 5. Next, the carrying signal outputted from the counter 6 switches to '1', and the selector 7 selects the signals from a bit line 129 to a bit line 256 and sent them to the register 5. In this manner, all the word lines are selected twice while the action to read all the contents stored in the array 2 is executed once. Consequently, a signal holding time which is requested for respective memory cells can be shortened to 1/2, and the memory can be miniaturized.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Field of industrial application B9 Summary of the invention C9 Prior art [Figure 4] 00 Problems to be solved by the invention E9 Means for solving the problems F1 Effects G. Examples [Figures 1 to 3 Figure H1 Effects of the Invention (A, Industrial Application Field) The present invention is designed to input and output data to a dynamic memory, particularly a memory cell array, through a register that converts signals from parallel to serial or from serial to parallel. Regarding dynamic memory.

(B. Summary of the Invention) In the dynamic memory described above, the present invention divides the memory cell array into a plurality of column groups in order to shorten the information retention time of the memory cells, and for example, when reading a signal, the bit The signal of the bit line group selected by the line group selector is converted into a serial signal by a register, and the bit line group selector switches the bit line group to be selected every time the refresh operation for all word lines is completed. It was designed to do this.

(C, Prior Art) [Fig. 4] There is an image memory shown in Fig. 4. In the figure, 1, 1... are memory cells, and 2 is a memory cell array (64 bits) consisting of memory cells 1 or grouped together.
, 3 is a sense amplifier, 4 is a rope coater, and 5 converts the 256-bit video signal for one horizontal period (H) read out in parallel from the memory cell array 2 into a serial signal, or converts the serial video signal from the outside. This is a register that converts signals into parallel signals.

This image memory transfers, for example, a 256-bit signal read out by one word line selected by the row decoder 4 to a register 5, which has the same number of bit lines as the total number of bit lines, and serially transfers the signal from the register 5. The data is sent to the outside of the memory. By repeating this operation while switching the selected word line, serial data can be read out at high speed. As the image memory, a dynamic type is often used because it is superior in terms of high speed, degree of integration, and low power consumption.

(D. Invention or problem to be solved) By the way, the fourth
If the image memory shown in the figure is configured with a dynamic memory, each memory cell must
．． 1, . . . - Retaining ability to retain stationary time information is required. In addition, as the capacity of memory increases due to higher image quality, the retention capacity required of memory cells increases, and it becomes difficult to meet this requirement. This point will be explained in detail as follows.

That is, in the image memory as shown in FIG.
The selection is made in the order of the 256th word line and the 2nd word line, and when the reading by the 256th word line is completed, it returns to the 1st word line, and each memory cell accesses itself. After the word line is selected,
The time storage signal must continue to be held until the same word line is selected next time. The time required to hold the signal is the product of the serial data cycle time, the number of bit lines, and the word line. To give a specific example, in the case of a 64-bit image memory, assuming a cycle time of 7 ONS (nanoseconds), 4.
It can be as much as 6mS (milliseconds). Furthermore, in the case of an image memory having four times the capacity of 256 bits, the capacity would be 18 m5. It is not easy to make all memory cells hold signals for such a long time, which is one of the factors that deteriorates the yield of memory.

Therefore, one major problem was that the memory cell was required to have a high information retention ability.

Furthermore, in the image memory shown in FIG. 4, the capacity of the register 5 that converts parallel video signals into serial data must be set to 256 bits for one line (IH), so the area occupied by the register 5 is very large. There is also the problem that the size of the chip becomes large, and as a result, the chip area has to be increased.

The present invention has been made to solve these problems, and is a dynamic system that outputs data to a memory cell array via a register that converts signals from parallel to serial or from serial to parallel. It is an object of the present invention to shorten the signal holding time required of a memory cell in a memory, and to reduce the capacity 11t of a register for parallel-to-serial conversion.

(E. Means for Solving the Problems) In order to solve the above problems, the dynamic memory of the present invention divides the memory cell array into a plurality of column groups, and connects the bit line group and register selected by the bit line group selector. The bit line group selector is characterized in that the bit line group selector switches the bit line group to be selected every time the refresh operation for all word lines is completed.

(F. Effect) According to the dynamic memory of the present invention, the bit line group selector does not perform a parallel/serial conversion operation using all the bit lines of the memory cell array as a unit, but instead performs a parallel/serial conversion operation using all the bit lines of the memory cell array as a unit. Parallel/serial or serial
Since the parallel conversion operation is performed, the register only needs to have a capacity equal to the number of bit lines in one bit line group, and therefore the register capacity can be reduced to 1/the number of bit line groups compared to conventional methods. .

Then, when one word line is selected, the parallel signal of one bit line group is transferred to the register via the bit line group selector, which is repeated for all word lines. Since the group selector sequentially switches the selected bit line groups, the word line selection cycle can be multiplied by the number of bit line groups while keeping the amount of information per time the same when reading or writing from the memory array. Therefore, the frequency of refresh operations for memory cells on each word line can be multiplied by the number of bit line groups, and in turn, the signal retention time required for memory cells can be reduced to one times the number of bit line groups. can.

(G. Embodiment) [FIGS. 1 to 3] The dynamic memory of the present invention will be described in detail below according to the illustrated embodiment.

FIG. 1 is a circuit block diagram showing one embodiment of the dynamic memory of the present invention. In the same figure, 1.1,...
2 is a memory cell array formed by grouping memory cells 1, and two bit line groups 2. ．． 22
It is divided into.

That is, in this embodiment, the first to 128th bit lines form the first bit line group 2. is configured, 1
The 29th to 256th bit lines constitute a second bit line group 2□. 3 is a sense amplifier,
4 is a row decoder that sequentially selects 256 word lines one by one, and 5 is a parallel/serial conversion and serial
Shift register for parallel conversion, the number of bits is 1
It is 28. Reference numeral 6 denotes an 8-bit counter that counts transfer clock pulses and causes the row decoder 4 to sequentially switch the word line to be selected.

A bit line group selector 7 is interposed between the memory cell array 2 and the register 5, and is composed of the same number of switching units as the number of bit lines in one bit line group (128 in this embodiment). Each switching section has two switching terminals and one common terminal, and the common terminal is connected to the bit of the register 5 that corresponds to the switching section to which it belongs. Further, one of the two switching terminals of each switching section is a terminal for selecting the first bit line group 11, the other is a terminal for selecting the second bit line group 12, and the first bit line Group 1. The switching terminal for selecting is the first bit line group 1. The switching terminal for selecting the second bit line group 1□ is connected to the bit line corresponding to the switching unit to which the self belongs, and the switching terminal for selecting the second bit line group 1□ is connected to the bit line corresponding to the switching unit to which the second bit line group 1□ belongs. It is connected to the.

The bit line group selector 7 is controlled by the carry signal of the counter 6. For example, when the carry signal is "0", all the switching sections are in a state of selecting the first bit line group 21, and when the carry signal is "1" At this time, all the switching units are in a state where they select the second bit line group 2°.

Next, a read operation among the operations of the image memory shown in FIG. 1 will be explained.

Focusing on the operation in which word lines are selected in order from the first word line by the movement of the row decoder 4 that decodes the output of the counter 6 that counts transfer lock pulses, the 256 word lines selected by the first word line are The signals of the memory cells are read out to the bit lines all at the same time, and then rewritten to each memory cell by the sense amplifier 3.By the way, the carry signal output from the counter 6 is "0". , the bit line group selector 7 is currently in a switching state (indicated by a solid line) to select the first bit line group 2. Therefore, the bit line signal or the bit line group only for the first bit line group 21 is selected. The signal is transferred to the register 5 via the selector 7.The register 5 receives the 128-bit signal transferred in parallel, shifts the signal sequentially, and outputs the signal one bit at a time.Then, the 128-bit signal When outputting is finished, the selected word line is switched from the first to the second word line based on the next transfer lock pulse.Then, the same operation as when the first word line was selected is repeated. In this way, each time a transfer lock pulse arrives, the word lines related to reading are switched one by one, and the 256th word line is selected. When the operation ends, the operation ends with the first bit line group 2I selected by the bit line group selector 7.The operation ends with the first bit line group 2I selected. The time required for the image memory to be stored is, for example, approximately 2.8 mS (milliseconds), which is half of that in the case of the image memory shown in FIG. was 256 bits, but it was only half that, 128 bits, and parallel
This is because the time required for serial conversion can be reduced to 1/2.

Next, the operation in a state where the second bit line group 22 is selected by the bit line group selector 7 (indicated by a broken line) will be described. When the first transfer lock pulse arrives after the operation with the first bit line group 21 being selected, the row decoder 4 selects the first bit line and the counter 6 The carry signal sent from the bit line group selector 7 to the bit line group selector 7 switches from "0" to "1". Then, the bit line group selector 7 switches to the switching state to select the second bit line group 22, and the 256-bit signals selected by the first word line are read out to the bit lines all at once and rewritten. Among them, the bit lines belonging to the second bit line group 2□, that is, the 129th to 256th bit lines, are transferred in parallel to the register 5 via the bit line group selector 7, and is converted into a serial signal and output.

Thereafter, similar operations are performed while switching the selected word line, and when the 256th word line is selected, all the contents stored in the memory cell array are output from the register 5.

As is clear from the above description, in this image memory, all the word lines are selected twice during one readout operation of all the contents of No. 13 stored in the memory cell array 2. That is, each memory cell is refreshed twice while reading out the entire memory cell array 2, and the refresh period is halved. Therefore,
The signal retention time required for each memory cell can be reduced to one-half, the severity of the requirements regarding retention characteristics can be reduced, and the yield can be improved.

In the above embodiment, the memory cell array is divided into two to reduce the minimum signal holding time required for each memory cell to one half.

However, the present invention is not limited thereto. For example, the memory cell array may be divided into four parts so that the minimum signal holding time required for the memory cell array can be reduced to one quarter. FIG. 2 shows a second embodiment of the present invention. In this embodiment, the memory cell array 2 has four bit line groups 23.2□, 23.
．． The bit line group selector 7 consists of a 1/4 selector that selects one bit line group designated by a 2-bit control signal. A 2-bit counter 8 counts the carry signal of the counter 6, and generates the 2-bit control signal for controlling the bit line group selector 7. In the figure, the numbers inside circles indicate the access order of data in units of 64 bits.

In such an image memory, each memory cell is refreshed four times while accessing the entire memory cell array, reducing the minimum signal retention time required for each memory cell by a factor of four. It turns out. Further, the number of bits (capacity) of the register 5 for parallel-to-serial conversion can be reduced to one fourth, and the area occupied by the register can be reduced.

FIG. 3 is a circuit block diagram showing variations in the access order in the image memory shown in FIG. 2.

The data access order in units of 64 bits in an operation cycle in which one memory cell array is accessed is not necessarily from the first word line to the second word line, or from the first bit line group to the first bit line group. It is not necessary to arrange them in a positional order such as the second bit line group, but they may be accessed in a so-called irregular order as shown by the numbers in circles. However, even in this case, the fact remains that the bit line group to be selected is switched only after the operation of accessing all word lines in a predetermined order with one bit line group selected is completed.

(H, Effects of the Invention) As described above, the dynamic memory of the present invention includes a dynamic memory cell array divided into a plurality of bit line groups, and a bit line of the same number as the number of bit lines of one bit line group. interposed between the memory cell array and the register and between each bit line of one selected bit line group and each bit of the register. and a bit line group selector for transferring signals, and the bit line group selector sequentially selects bit line groups each time an operation of selecting and refreshing a word line is performed across all word lines. It is characterized in that it can be switched.

Therefore, according to the dynamic memory of the present invention, the register is configured in parallel in units of bit lines of one bit line group.
Since the serial conversion operation is performed, the capacitance for one bit line group is sufficient, and the capacitance can be reduced to 1/the number of bit line groups, which in turn facilitates miniaturization of the dynamic memory.

When one word line is selected, the parallel signals for one bit line group are transferred to the register via the bit line group selector. Each time the operation is repeated for all word lines, Since the bit line groups selected by the selector are sequentially switched, the word line selection cycle can be multiplied by the number of bit line groups while keeping the amount of information read from the memory array the same per unit time. Therefore, the frequency of refresh operations for memory cells on each word line can be doubled by the number of bit line groups, and the signal retention time required for memory cells can be reduced to one-fold by the number of bit line groups. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a first embodiment of the dynamic memory of the present invention, FIG. 2 is a circuit block diagram showing a second embodiment of the dynamic memory of the present invention, and FIG. 3 is a circuit block diagram showing the second embodiment of the dynamic memory of the present invention. FIG. 4 is a circuit block diagram showing variations in the access order of a dynamic memory. FIG. 4 is a circuit block diagram showing a conventional example. Explanation of symbols 2...Memory cell array, 21.2□, 21.24...Bit line group, 5...
Register, 7...Bit line group selector.

Claims (1)

[Claims] (1) A dynamic memory cell array divided into a plurality of bit line groups, a register having the same number of bits as the number of bit lines in one bit line group and performing parallel-to-serial conversion or serial-to-parallel conversion; The selected one is interposed between the memory cell array and the above register.
and a bit line group selector that transfers signals between each bit line of the two bit line groups and each bit of the register, and the bit line group selector is fully capable of selecting and refreshing word lines. A dynamic memory characterized in that a group of selected bit lines is sequentially switched each time a word line is crossed.