JP2567177B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) having an array of cascaded dynamic memory cells capable of storing a plurality of bits of information in bit units.
Regarding

[0002]

2. Description of the Related Art DRAM cells currently in practical use are
One MOS (insulated gate) transistor for a transfer gate connected to the word line and the bit line,
It is composed of one capacitor for information storage connected to this.

On the other hand, in order to make the DRAM cell more highly integrated and reduce the unit price of bits, the present inventor has, for example, shown in FIG.
Alternatively, a cascade gate type semiconductor memory cell as shown in FIG. 16 has been proposed (Japanese Patent Application No. 2-104576).
issue).

The DRAM cell shown in FIG. 15 has MOS transistors Q1 to Q4 connected in cascade, and capacitors C1 to C4 for information storage, one end of each of which is connected to one end of each of the transistors Q1 to Q4. By turning on / off the transistors Q1 to Q4 in a predetermined order, one side of the cascade connection (read / read
The stored information of the capacitors C1 to C4 is read to the node N1 in order from the capacitor C1 on the side closer to the writing node N1), and further, the capacitors C4 to C1 are connected to the node N1 from the capacitor C4 on the side far from the node N1.
It becomes possible to write 1 information.

The DRAM cell of FIG. 16 is the same as the DRA of FIG.
A MOS transistor Q5 is further connected between one end of the transistor Q4 of the M cell and the second node N2. By turning on / off the transistors Q1 to Q5 in a predetermined order, the stored information of the capacitors C1 to C4 is read to the node N1 in order from the capacitor C1 on the side closer to the node N1, and further on the side closer to the node N1. Capacitors C1 to C4 in order from the capacitor C1
It becomes possible to write the information of the second node N2 to.

The cascade gate type memory cells as shown in FIGS. 15 and 16 described above are capable of storing a plurality of bits of information on a bit-by-bit basis. Since only one contact with a bit line is required for each bit, it is possible to achieve a much higher degree of integration than a conventional DRAM using an array of 1-transistor / 1-capacitor type cells, and significantly reduce the bit unit price. be able to.

By the way, when a DRAM is constructed by using the above-mentioned cascade gate type memory cell, the stored information in the cell is destructed and read, so that it is always necessary to rewrite. However, in the above-mentioned cascade gate type memory cell, the order of reading and writing of the capacitors in one memory cell is defined. Therefore, regarding any capacitor, it is not possible to rewrite immediately after reading the stored information. Unacceptable. That is, rewriting cannot be performed without waiting for reading from another capacitor in the same cell following reading from an arbitrary capacitor.

Therefore, when a DRAM is constructed by using the array of the cascade gate type memory cells as described above, rewriting (or writing) is sequentially performed after the reading of a plurality of bits from the memory cells is completed in time series. We need a way to do it.

In view of the above situation, the present inventor has used a cascade gate type memory cell array for DR.
When configuring the AM, it has a storage means for temporarily storing a plurality of bits of information read out in time series from the memory cells, and rewrites (or writes) the plurality of bits of information in sequence after the reading is completed. Has proposed a semiconductor memory device capable of realizing the above (Japanese Patent Application No. 3-41316).
issue).

On the other hand, by utilizing the serial accessibility of the cascade-type memory cell as it is, a DRAM of a system for serially (sequentially) accessing the memory cell group in the column of the array of the cascade-type memory cell is constructed. Can be considered. In this case, there is room for improvement in the method of rewriting the information read out in time series from the cascade type memory cell.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a method of serially accessing a plurality of memory cells in an arbitrary column in an array of cascaded memory cells. However, at the time of serial access, it is possible to omit the register that temporarily stores the information that is sequentially read in time series from the memory cell that stores the stored information for rewriting, which enables high integration. It is an object of the present invention to provide a semiconductor memory device having the following.

[0012]

A semiconductor memory device according to the present invention comprises a plurality of cascade-connected MOS transistors.
Cascade gate with both ends connected to the same bit line
And each of the gates of the plurality of MOS transistors described above.
Connected word lines and the above-mentioned MOS transistors
Each end is connected corresponding to the connection node between
Cascade type dynamic memory cells each having a plurality of information storage capacitors are arranged in a matrix, and the word lines of the memory cells in the same row are commonly connected.
Are continued, the bit line is commonly connected memory cells in the same column
A memory cell array, in chronological any access to the serial to each plurality of the memory cells in the column, one from the plurality of bits information of the memory cell storing the storage information of the memory cell array And a serial access control means for controlling such that the information of a plurality of bits is sequentially rewritten to another memory cell in the same column as the memory cell, in which another memory information is not stored. And Furthermore, the semiconductor memory of the present invention
The storage device is a plurality of MOS transistors connected in cascade.
A cascaded gate with one end of the star connected to the bit line.
And the gate of each of the above MOS transistors.
Each connected word line and each of the above MOS transistors
Corresponding to the other end on the side far from the bit line of the transistor
It has a plurality of capacitors for information storage connected at one end.
Cascade type dynamic memory cell having each
Are arranged in a matrix, and the word lines of the memory cells in the same row are
Bit lines of memory cells in the same column that are commonly connected
Memory cell array connected to the
A for each memory cell in any column of
To access the serial and store the stored information.
Read multiple bits of information from one memory cell in time series
However, this multi-bit information is stored in the same color as the above memory cell.
Memory cell that does not store another stored information in the memory
Serial access control that controls to rewrite sequentially
And means for controlling.

[0013]

This semiconductor memory device has, in addition to memory cells for data storage, one extra memory cell per column, and when a certain cell is read during serial access to a plurality of memory cells in an arbitrary column, By using a procedure of storing (rewriting) in a cell which has been accessed before and is now in an empty state, serial access can be performed in column units. This makes it possible to omit the means for temporarily storing the information that is sequentially read out in time series from the memory cells that store data for rewriting, enabling high integration, and realizing with a very small chip size. it can.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a DRAM according to a first embodiment of the present invention.
3 is a circuit diagram showing a part of FIG.

In FIG. 1, 30 is a memory cell array in which cascade gate type memory cells capable of storing a plurality of bits of information in bit units are arranged in a matrix, 31
Is a row address designating circuit for outputting a row address designating signal for serially designating the row address of the memory cell array 30, and 32 is the row address designating circuit 3
1 is a first clock generation circuit for supplying a first clock signal to 1; 33 is a word line drive circuit for selectively driving a word line connected to a memory cell of an address designated by the address designation circuit 31; Reference numeral 34 is a second clock generation circuit for supplying a second clock signal to the word line drive circuit 33.

Reference numeral 35 is a bit line sense amplifier (hereinafter referred to as a sense amplifier) for sensing the potential of the bit line of the memory cell array 30. 36 is a column decoder for decoding a column address, 37 is an input / output gate (column selection circuit) selectively driven by the output of the column decoder 36, 38 is an input / output line pair (I / O) to the input / output gate 37, It is a buffer circuit connected via / (I / O). The control circuit 41 controls the operation timing of the first clock generation circuit 32, the second clock generation circuit 34, the sense amplifier 35, and the like.

The control circuit 41, the first clock generating circuit 32, the second clock generating circuit 34, and the sense amplifier 3
5. The row address designating circuit 31 and the word line driving circuit 33 serially access a plurality of memory cells in an arbitrary column of the memory cell array 30 to store a plurality of bits from one memory cell storing memory information. Information is read in time series, and a serial access control function is provided to control so as to sequentially rewrite the information of a plurality of bits to another one unused memory cell in the same column as the memory cell. FIG. 2 shows the memory cell array 3
FIG. 3 is a circuit diagram showing an example in which one column of 0, sense amplifier 35, and input / output gate 37 is representatively taken out.

MC0 to MCn are n (integer) +1 memory cells in the same column. Of the (n + 1) memory cells, n cells are used to store 4n-bit block data, and one cell is additionally provided. BL is the memory cells MC0 to MCn in the same column.
VBL is a bit line precharge power supply, PR is a bit line precharge circuit for precharging the bit line BL to a predetermined potential VBL, and it is turned on at a predetermined timing by a bit line precharge signal φBL. Driven.

SA is, for example, a latch type amplifier, which is provided for each column, and one of a pair of input / output nodes is connected to the bit line BL. The transfer gate CS for the input / output gate is a sense amplifier SA.
Pair of input / output nodes and the input / output line pair (I / O), /
It is connected to (I / O) and is controlled by a column selection line CSL (column decoder output line).

As shown in FIG. 16, each of the memory cells MC0 to MCn has three or more (five in this example) cascaded between the first node N1 and the second node N2. Cascade gate having MOS transistors Q1 to Q5, and the cascade-connected MOS
There are provided a plurality of capacitors C1 to C4 for information storage, one ends of which are connected to each other corresponding to connection nodes between the transistors. The first node N1 and the second node (N
2) and are commonly connected to the bit line BL. The gates of the transistors Q1 to Q5 of the memory cells MC0 to MCn are word lines (WL0a to WL0).
e), ..., (WLna to WLne) are connected. These word lines (WL0a to WL0e), ... (WLna to
WLne) is commonly connected to the gates of the corresponding transistors Q1 to Q5 of the memory cell group (not shown) in the same row of the memory cell array 30. Capacitor C1 ~
The other ends of C4 are commonly connected to the capacitor wiring 42. In this example, the plate electrodes of the capacitors C1 to C4 are commonly connected, and a predetermined capacitor plate potential VPL is applied to the plate electrodes in common with other memory cells. FIG. 3 shows a row address designating circuit 31 in FIG.
3 is a circuit diagram showing a part of an example of a word line drive circuit 33. FIG. FIG. 4 is a timing waveform chart showing an example of the operations of the row address designating circuit 31 and the word line driving circuit 33 of FIG.

In FIG. 3, the row address designating circuit 31 is provided.
Uses a shift register SR. This shift register SR has a capacity of 5 in the memory cell array 30.
(N + 1) sets of word lines (WL0a to WL)
0e) to (WLna to WLne) have (n + 1) stages, in other words, the number of rows (n +) of the memory cell array 30.
1) × k (integer, 5 in this example) has a number of stages corresponding to 1 / k. The (n + 1) th stage shift circuit is serially connected and the ring circuit is formed so that the final stage output becomes the first stage input. Then, the shift register SR is controlled so that the output of the address designation signal is started from the shift register stage (for example, the last stage) for designating the start address at the start of the first serial access operation after the DRAM is powered on. To be done.

As the word line drive circuit 33, a number of word line drive circuits corresponding to the number of rows of the memory cell array 30, in other words, (n + 1) sets of word line drive circuits which form one set are used. . Then, each set of five word line drive circuits 431 corresponding to each stage output of the shift register SR.
To 435, that is, the output of each stage of the shift register SR selectively controls the corresponding five word line drive circuits 431 to 435.

The word line drive circuits 431 to 435 are
The power supply potential node for driving the word line and the ground potential (V
(SS) node and operation control PMOS transistor 4
4. A word line driving PMOS transistor 45 and a word line pull-down NMOS transistor 46 are cascade-connected. Corresponding shift register stage outputs are commonly supplied to the gates of the transistors 44, and the pull-up control signals / WLa to / WL from the second clock generating circuit 34 are supplied to the gates of the transistors 45.
e are sequentially supplied correspondingly, and the NMOS transistor 46
The pull-down control signals WLa to WLe are sequentially supplied from the second clock generating circuit 34 to the respective gates of. As a result, a word line drive signal is output from each output node (connection point of the transistors 45 and 46) of the word line drive circuits 431 to 435, and five words of each group are set in one serial access as described later. Line (W Lia ~
WLie) (i = 0, 1, ..., N) can be sequentially turned on for a fixed period of time. Figure 5
3 is a timing chart shown for explaining an example of a serial access operation for a plurality of memory cells in an arbitrary column of the DRAM of FIG. 1. FIG.

In the DRAM of FIG. 1, in the initial state, a series of data (block data) is stored in cells MC0 to MC (n-1) of a certain column, and the cell MCn is in a non-use state (non-storage state). Now, an outline of a serial access operation in which the block data is sequentially read and rewritten simultaneously by serial access will be described with reference to FIG.

In the first serial access, at time t0, the word lines WL0a to WL0e are sequentially turned on to read the 4-bit storage information of the capacitors C1 to C4 of the cell MC0 to the bit line BL in order to read the word data. Line W
L1a to WL1e are sequentially turned off to store the 4-bit information in the non-used one cell (MCn corresponds to MCn) of the same column as the cell MC0.
The operation of rewriting C4 in sequence is started.

In a manner similar to the above operation, at time t1,
The 4-bit information of the cell MC1 is sequentially read to the bit line BL and one cell in the unused state in the same column (in this case, M
The operation of rewriting C0) is started.

Thereafter, in the same manner as the above-mentioned operation, the read / rewrite operation is sequentially performed in units of two cells in the same column with different combinations of read and write, so that the time tn is finally reached. In the state, the 4-bit information of the cell MC (n-1) has been rewritten in the cell MC (n-2). By such one-time serial access, the block data is transferred to the cells MCn, MC0 to MC (n-2).
Will be stored in.

(N + 1) in the same column as described above
By the first serial access to the cells,
At the same time that continuous block data stored in n cells were sequentially read, the block data was rewritten to n memory cells including one cell that was in an unused state before this read. It will be.

In the second serial access,
It starts from the operation of returning the start address (word line address) of the previous serial access by one cell and rewriting the read data of the cell MCn to the cell MC (n-1), and finally to the cell MC (n- 2) Read data from cell MC (n
-3) Rewrite to. By such serial access, the block data is transferred to the cells MC (n-1), MCn, M.
It is stored in C0 to MC (n-3).

The operation for returning the start address (word line address) of the previous serial access by one cell is
This can be easily realized by utilizing that the shift register SR is composed of (n + 1) -stage shift circuits. That is, the state of the shift register SR at the end of the previous serial access is retained, and the shift register S is held after the end of the previous serial access (or before the start of the current serial access).
A dummy cycle period in which R is shifted by one stage may be provided. Next, the operation from time t0 to t1 in the above operation will be representatively taken out and described in detail with reference to FIG. Figure 6
FIG. 3 is a timing waveform chart showing an example of the operation of the DRAM of FIG.

The word lines (WLna to WLne) are controlled so that the transistors of the cell MCn are turned off in the order of Q1 to Q5, and the transistors of the cell MC0 are turned on in the order of Q1 to Q5 in a fixed timing relationship with this. To control the word lines (WL0a to WL0e). Then, the cell MCn
Transistor Q1 is off, transistors Q2 to Q
5 is on and the transistors Q1 to Q5 of the other cells MC0 to MC (n-1) are off (time t0), the bit line precharge circuit PR keeps the bit line BL at a predetermined potential for a certain period. Precharge. In this state, when the transistor Q1 of the cell MC0 is turned on, the cell MC0
The stored information in the capacitor C1 of 0 is read to the bit line BL via the transistor Q1, and the sense amplifier SA operates at the timing of ts to output the read information. After the rewrite potential is set to the bit line BL by this sense output, when the transistor Q2 of the cell MCn is turned off, the potential of the bit line BL (the stored information of the capacitor C1 of the cell MC0) is stored in the capacitor C1 of the cell MCn. Is stored. Next, after precharging the bit line BL again, the transistor Q2 of the cell MC0 is turned on, and the stored information of the capacitor C2 of the cell MC0 is transferred to the transistor Q2.
It is read out to the bit line BL via 2 and Q1, and is sensed and output by the sense amplifier SA at the timing of ts. After the rewrite potential is set to the bit line BL by this sense output, when the transistor Q3 of the cell MCn is turned off, the potential of the bit line BL is stored in the capacitor C2 of the cell MCn (information stored in the capacitor C2 of the cell MC0).
Is stored. Next, after precharging the bit line BL again, when the transistor Q3 of the cell MC0 is turned on, the stored information of the capacitor C3 of the cell MC0 is read out to the bit line BL via the transistors Q3 to Q1 and ts
Is sensed and output by the sense amplifier SA at the timing. After the rewrite potential is set to the bit line BL by this sense output, the transistor Q4 of the cell MCn is set.
When turned off, the potential of the bit line BL (stored information of the capacitor C3 of the cell MC0) is stored in the capacitor C3 of the cell MCn. Next, after precharging the bit line BL again, when the transistor Q4 of the cell MC0 is turned on, the stored information of the capacitor C4 of the cell MC0 is read out to the bit line BL via the transistors Q4 to Q1.
It is sensed and output by the sense amplifier SA at the timing of ts. When the transistor Q5 of the cell MCn is turned off after the rewriting potential is set on the bit line BL by this sense output, the potential of the bit line BL (the information stored in the capacitor C4 of the cell MC0) is stored in the capacitor C4 of the cell MCn. Is stored. After that, the transistor Q5 of the cell MC0 is turned on and then the transistor Q1 is turned off (This operation order may be reversed, and by the time t1 when the operation of reading the stored information of the next cell MC1 and rewriting it to the cell MC0 is started. Just go). As a result, the cell M
Transistor Q1 of C0 is off, transistor Q2
.About.Q5 are turned on, the transistors Q1 to Q5 of the other cells MC1 to MCn are turned off, and the state of waiting for the next reading of the cell MC1 and rewriting to the cell MC0 is set.

In this state, the transistors of the cell MC0 are turned off in the order of Q2 to Q5, and the transistors of the cell MC1 are turned on in the order of Q1 to Q5 in a certain timing relationship with the word lines (WL0a to WL0e). And (W
L1a to WL1e) are turned on / off to read the stored information of the cell MC0 and rewrite it to the cell MCn according to the above-described operation of reading the stored information of the cell MC0 and rewriting the cell MCn. It will be possible.

According to the DRAM of FIG. 1, by turning on the transistors of the cells to be read in the order of Q1 to Q5, the storage information of the capacitors C1 to C4 is sequentially read to the bit line BL, and Correspondingly sense amplifier S
Column selection line C of the column to be selected when A operates
By activating SL and turning on the transfer gate CS, it becomes possible to read out to the outside of the DRAM chip, that is, four digital information (4 bits) can be read out in a determined order. Then, since such a read operation is sequentially performed on n (for example, n = 128) memory cells used for storing information in the column, 4 bits × 128 cells = 512 bits from one column. (64 bytes) can be sequentially read.

Further, according to the DRAM of FIG. 1, since the information read out in time series from the cell is rewritten in another cell in the same column, the information read out in time series from the cell is temporarily written for rewriting. A storage means for storing is unnecessary, high integration is possible, and it can be realized with a very small chip size.

Further, according to the DRAM of FIG. 1, since the information read out in time series from the cell is rewritten immediately after the reading, the operation of the sense amplifier required for reading / rewriting is only once for each bit. , Low power consumption becomes possible.

Writing in the DRAM of FIG.
The necessary data may be set in the bit line BL at the rewriting timing ts as described above. Input / output lines (I / O), / (I / I) are provided between each column and the data input / output circuit.
By selectively connecting by O), writing of input data and transfer of read data to the output side are performed. The input / output lines (I / O) and / (I / O) may be separated for input and output.

The refresh operation in the DRAM of FIG. 1 can be performed by performing the serial access as described above with the transfer gate CS turned off. In this case, a refresh timer circuit may be incorporated in response to an external refresh signal, and the refresh operation may be performed in a fixed cycle in accordance with the timer output.

As shown by a broken line in FIG. 2, a transfer gate TG is inserted between the bit line BL and the input / output node of the sense amplifier SA, and the memory cell M is inserted.
When reading information from Ci, after the signal from the memory cell MCi reaches the sense amplifier SA via the bit line BL, the transfer gate TG is controlled to the off state, and thereafter the sense amplifier SA is activated. For example, since the sense amplifier SA does not have to charge and discharge a large parasitic capacitance of the bit line BL, it is possible to achieve high speed and low power consumption at the same time. In other words, if the transfer gate TG is selectively turned on / off so that the sense amplifier SA charges and discharges the bit line BL only when rewriting (or writing), read data and write data are generated. When different, power consumption can be reduced.

Further, instead of the latch type sense amplifier SA, a differential type amplifier (not shown) for comparing a bit line potential with a reference potential is used, and a write circuit (not shown) is based on the sense output. Alternatively, the rewriting potential may be set to the bit line BL.

As another example of the memory cell MCi,
It is possible to use the cascade gate type memory cell proposed by Japanese Patent Application No. 2-104576.
As still another example of the memory cell MCi, as in Japanese Patent Application No. 3-43121 proposed by the present inventors, the relationship between the capacitance values of the capacitors C1 to C4 is as follows.
For example, if the capacitance value is set to increase in the reading order of information, it is possible to alleviate or prevent the amount of change in the voltage of the bit line BL in the case of sequentially reading the storage information of each capacitor, and reduce or prevent the change in each voltage. It becomes possible to make the minutes substantially equal, and it is possible to prevent an error in reading information.

In the DRAM of FIG. 1, the random accessibility and the access time are limited to some extent, but as shown by the broken line in FIG. 1, the I / O gate 3
7 and an input / output terminal (not shown) are provided with a serial / parallel conversion circuit 39, and the read 4 bits are serial / parallel converted into bit data to realize a DARM of x4 bit configuration. By designing as above, it is possible to maintain completely random accessibility.

In addition, when the memory cell array is divided into a plurality of sub-arrays and only a part (eg, two or four) of the plurality of sub-arrays is activated at the same time for power saving. In this case, a DRAM having a x8 bit configuration or a x16 bit configuration can be realized by serial / parallel conversion. FIG. 7 is a sequential sequence diagram which can be used in place of the shift register SR shown in FIG.
FIG. 3 is a circuit diagram showing an example of a decoder. FIG. 8 is a timing diagram showing an example of the operation of the sequential decoder of FIG.

The sequential decoder shown in FIG. 7 is provided with a synchronization signal (count-up signal) and performs (j + 1) -th stage address counter 51, which performs a count-up operation.
The outputs a0 to a (j-1) of the A0 to A (j-1) stages of the address counter 51 are decoded to output n outputs 0 to (n-
1) are sequentially generated and a logical product of the decoder circuit 52 for supplying as an operation control signal corresponding to the n sets of word line drive circuits (not shown), the final stage output aj of the address counter 51 and the serial access start signal And an AND circuit 53 for supplying the output as a reset signal of the address counter 51.

According to this sequential decoder,
When the final stage output aj of the address counter 51 is generated (activated) after the end of the serial access, the final stage output aj sets the start address of the next serial access to 1
The operation of shifting by the amount of cells is performed. Then, when the serial access start signal is input after the end of this operation,
The address counter 51 is reset, the address counter 51 performs the count-up operation again, and the next serial access is performed. Further, instead of the shift register SR and the word line drive circuit 33 shown in FIG. 3, it is possible to use a circuit as shown in FIG. 9 or 10.

In the circuit shown in FIG. 9, a 5 (n + 1) -bit delay gate circuit 61 is connected in a ring shape, and the output between stages of the delay gate circuit 61 is a word line for 5 (n + 1) bits. It is input to the drive circuit 62. Then, at the start of serial access, a pulse signal (word line selection signal) having a constant width is input to the input end of the delay gate circuit stage corresponding to a predetermined address (address one cell before the start address), and serial access is performed. The input end of the delay gate circuit stage may be reset at the end of the above step.

The circuit shown in FIG. 10 has a sequential decoder 71 for (n + 1) bits connected in a ring.
And (n + 1) decoded outputs of the sequential decoder 71 are (n + 1) 5-bit delay gate circuits 7
2 and the interstage output of each delay gate circuit 72 is input to the word line drive circuit 62 for 5 (n + 1) bits. Then, at the start of serial access, the decode output is sequentially generated from the circuit stage corresponding to the predetermined address of the sequential decoder 71 (the address one cell before the start address), and the decode output is scanned so that the address goes round. Let In this case, the word line selection signal is output from each stage of the delay gate circuit 72 to which the decode output is input in a scanning manner, and the word line drive circuit 62 sequentially drives the word lines (WL0a to WL0e) to (WLna to WLne). To be done.

When the circuits of FIGS. 9 and 10 are used, the control is performed so that the head address of the word line to be accessed next time is returned by one cell each time the serial access is performed. Can be realized, for example, by using the configuration described below.

As a specific example, an n-bit bit rotator circuit is prepared, one bit is set to the "1" state by initialization, and one bit is set for each serial access.
Rotate bit by bit, and use the output of this bit rotator circuit to specify the start address.

As another specific example, a register or counter for an address pointer is prepared, and the contents of the address pointer (start address) are set for each serial access.
Is updated, and the head address may be designated by using the output of this address pointer. Furthermore, instead of the shift register SR shown in FIG. 3, (n + 1) row decoders (word line selection circuits) and (n + 1) delay gate circuits may be used. In this case, the outputs of the (n + 1) row decoders are connected to the input terminals of the word line drive circuits corresponding to the word lines WL0a, ..., WLna, and the (n + 1) number of 4 bits are connected. It is connected to the input terminal of the delay gate circuit, and the output of each stage of this delay gate circuit is connected to the word line WL0b.
-WL0e, ..., WLnb-WLne are connected to the input ends of the word line drive circuits. Then, at the time of serial access, a row address signal may be input to the row decoder so that the address makes one round. In this case, a word line selection signal is output in a scanning manner between the stages of the row decoder corresponding to the specified address and the delay gate circuits provided corresponding to the row decoder, and the word line drive circuit outputs word lines (WL0a to WL0e). )-(WLna-WLne) are sequentially driven.

As described above, when the row address signal is input to the row decoder during serial access, the start address of the word line to be accessed is returned by one cell for each serial access as described above. As described above, the row address signal can be controlled outside the chip. FIG. 11 shows a DRAM according to the second embodiment of the present invention.
3 is a circuit diagram showing a part (for one column of a memory cell) of FIG. Compared to the DRAM shown in FIG. 1, this DRAM has
The memory cells MC0 to MCn and the structure related thereto are different.

As shown in FIG. 15, each of the memory cells MC0 to MCn has a plurality of MO cells (four cells in this example).
S transistors Q1 to Q4 are connected in cascade, and one end side (Q1 side in this example) is a read / write node N.
Cascade gate connected to 1 and the above multiple MO
Each of the S transistors Q1 to Q4 has a plurality of capacitors C1 to C4 for information storage, one end of which is connected to one end corresponding to one end farther from the node N1. The node N1 is connected to the bit line BL. The gates of the MOS transistors Q1 to Q4 of the DRAM cells MC0 to MCn are connected to the word line (WL0a
-WL0e), ..., (WLna-WLne) are connected. The other ends of the capacitors C1 to C4 are commonly connected to the capacitor wiring 42. In this example, the plate electrodes of the capacitors C1 to C4 are commonly connected, and a predetermined capacitor plate potential VPL is applied to the plate electrodes in common with other DRAM cells.
FIG. 12 is a timing chart showing an example of a serial access operation for a plurality of memory cells in the column shown in FIG.

Next, in the DRAM of FIG. 11, in the initial state, it is assumed that the block data is stored in the cells MC0 to MC (n-1) of a certain column and the cell MCn is in the unused state. Outline of serial access in which data is sequentially read and rewritten simultaneously is shown in FIG.
Will be described with reference to.

In the first serial access, at time t0, the stored information of the capacitors C1 to C4 of the cell MC0 is read in order, and this 4-bit information is read in another unused cell (in this case, MCn is The operation of rewriting the capacitors C4 to C1 (corresponding) is sequentially started. Next, at time t1, the 4-bit information of the cell MC1 is sequentially read and the operation of rewriting to another cell in the unused state of the same column (MC0 corresponds at this time) is started. Then, the operation of sequentially reading the 4-bit information of the cell MCi and rewriting to the cell MC (i-1) is repeated, and finally, at time tn, 4 bits of the cell MC (n-1) are read.
The bit information is in a state of being rewritten in the cell MC (n-2).

By such one-time serial access, the block data is transferred to the cells MCn, MC0 to MC (n-2).
Will be stored in. However, the order of the 4-bit data stored in each cell MCn, MC0 to MC (n-2) after this serial access is stored in each cell MC0 to MC (n-1) before this serial access. It is necessary to note that the order of the 4-bit data is reversed and the order of the data in the block data to be read is reversed in units of 4 bits.

At the next serial access, the operation starts from the operation of reading the data from the cell MCn in which the head address (word line address) of the previous serial access is returned by one cell and rewriting to the cell MC (n-1). Then
Finally, the read data of the cell MC (n-2) is transferred to the cell MC
Rewrite to (n-3). By such serial access, the block data is transferred to the cells MC (n-1), MCn,
It is stored in MC0 to MC (n-3). Each cell MC (n-1), MCn, M after this serial access
The order of the 4-bit data stored in C0 to MC (n-3) is the order of cells MC0 to M before this serial access.
The order of the 4-bit data stored in C (n-1) is reversed, that is, the original order is restored.

In other words, depending on whether it is the even-numbered serial access or the odd-numbered serial access, the order of the data in the block data to be read is the original order, or it is reversed in units of 4 bits. Has become. As a countermeasure against this, as indicated by a broken line in FIG. 1, an even / odd determination circuit 40 including, for example, flag means (for example, a flip-flop circuit) for indicating whether the serial access is an even number or an odd number, and a block If the data is read at an even number of times (in the case where the data is reversed in units of 4 bits), a means for correcting the order of the read data by the even / odd determination output of the even / odd determination circuit 40 may be provided. As an example of this correction means,
A serial / parallel conversion circuit 39 for converting the read 4-bit data into serial / parallel, or a serial / parallel conversion of the read 4-bit data in units of 2 cells (8 bits) or 4 cells (16 bits). It is possible to use a means for converting. Next, the operation from time t0 to t1 in the above operation will be taken out as a representative example, as shown in FIG.
It will be described in detail with reference to FIG. FIG. 13 shows the DRA of FIG.
FIG. 6 is a timing waveform chart showing an example of the operation of M.

The word lines (WL0a to WL0d) are controlled so that the transistors of the cell MC0 are turned on in the order of Q1 to Q4, and the transistors of the cell MCn are turned off in the order of Q4 to Q1 in a constant timing relation with this. The word lines (WLna to WLnd) are controlled. Then, the cell MCn
All the transistors Q1 to Q4 are on, and other cells M
When all the transistors Q1 to Q4 of C0 to MC (n-1) are in the off state (time t0), the bit line precharge circuit PR precharges the bit line BL to a predetermined potential for a certain period. When the transistor Q1 of the cell MC0 is turned on in this state, the stored information of the capacitor C1 of the cell MC0 is read to the bit line BL via the transistor Q1 and the sense amplifier SA operates at the timing of ts to output the read information. To be done. After the rewrite potential is set to the bit line BL by this sense output, the cell MCn
When the transistor Q4 of the cell MCn is turned off, the potential of the bit line BL (information stored in the capacitor C1 of the cell MC0) is stored in the capacitor C4 of the cell MCn. Next, after the bit line BL is precharged again, the transistor Q2 of the cell MC0 is turned on, and the capacitor C of the cell MC0 is turned on.
The stored information of 2 is read out to the bit line BL via the transistors Q2 and Q1, and the sense amplifier S is read at the timing of ts.
It is sensed by A and output. After the rewrite potential is set to the bit line BL by this sense output, the cell M
When the transistor Q3 of Cn is turned off, the potential of the bit line BL is stored in the capacitor C3 of the cell MCn (the cell MC0
The storage information of the capacitor C2) is stored. Next, after precharging the bit line BL again, when the transistor Q3 of the cell MC0 is turned on, the stored information of the capacitor C3 of the cell MC0 is read out to the bit line BL via the transistors Q3 to Q1 and at the timing of ts. The sense amplifier SA senses and outputs. After the rewrite potential is set to the bit line BL by this sense output, when the transistor Q2 of the cell MCn is turned off, the cell MCn
Of the bit line BL to the capacitor C2 of
Information stored in the capacitor C3 of C0) is stored. Next, after precharging the bit line BL again, the cell MC
When the 0 transistor Q4 is turned on, the stored information in the capacitor C4 of the cell MC0 is read to the bit line BL via the transistors Q4 to Q1 and sensed and output by the sense amplifier SA at the timing of ts. When the transistor Q1 of the cell MCn is turned off after the rewrite potential is set to the bit line BL by this sense output, the potential of the bit line BL (the information stored in the capacitor C4 of the cell MC0) is stored in the capacitor C1 of the cell MCn. Is stored. As a result, the transistors Q1 to Q4 of the cell MC0 are
Are all in the on state, the transistors Q1 to Q4 of the other cells MC1 to MCn are all in the off state, and are in a state of waiting for the reading of the next cell MC1 and the rewriting of the cell MC0.

In this state, the transistors of the cell MC1 are turned on in the order of Q1 to Q4, and the transistors of the cell MC0 are turned off in the order of Q4 to Q1 in a certain timing relationship with the word lines (WL1a to WL1d). And (W
L0a to WL0d) are turned on / off to read the stored information of the cell MC0 and rewrite it to the cell MCn according to the above-described operation of reading the stored information of the cell MC0 and rewriting the cell MCn. It will be possible.

In the DRAM of FIG. 11 as well, as in the DRAM of FIG. 1, 4 bits × 128 = 512 bits (64 bytes) can be sequentially read from one column, and the cells can be read in time series. A storage means for temporarily storing the read information for rewriting is not required, high integration is possible, and it can be realized with a very small chip size.

In the DRAM of FIG. 11, if the arrangement directions of the transistors Q1 to Q4 in the odd-numbered cells and the even-numbered cells in the column are reversed, the transistors in the odd-numbered cells and the even-numbered cells become the same. Since Q1's are adjacent to each other, bit line contacts can be commonly provided for adjacent odd-numbered cells and even-numbered cells, as in the DRAM of FIG. As a result, there is one bit line contact per 8 bits (1/2 bit line contact per 4 bits), and the bit line capacitance can be reduced.

In most actual DRAMs, the arrangement pitch of the sense amplifiers SA is larger than the arrangement pitch of the bit lines BL, and the bit lines BL and the sense amplifiers S are arranged.
A system in which a switching circuit such as a transfer gate TG is provided between A and A, and one sense amplifier SA is switched by switching means and shared by a plurality of (usually 2, 4, 8, ...) Columns in a time division manner (so-called). , Shared sense amplifier method) is desirable.

FIG. 14 shows a DR according to the third embodiment of the present invention.
It is a circuit diagram which shows a part of AM. In this DRAM, for example, the shared sense amplifier system is applied to the DRAM shown in FIG. That is, multiple (for example, 4)
Bit lines BLa, BLb ... And transfer gate TG
a, TGb ... Share one sense amplifier SA, and the transfer gates TG are controlled by the control signals φa, φb.
a, TGb ... By controlling a plurality of bit lines BLa, BL
Only one of b ... Is selectively connected to the sense amplifier SA.

The DRAM of FIG. 14 has a cell capacitor C.
The 4-bit memory information of 1 to C4 is read in order, and
When rewriting the bit information to the capacitors C1 to C4 of another unused cell in the same column in order, the stored information of the cells of the same row in the four columns is simultaneously corresponded to each bit of the above 4-bit information. Bit line BL
... and sense-amplified by the sense amplifier SA in a time-sharing manner.
Rewrite cells.

As described above, by performing the cell read / rewrite operation while sequentially selecting four columns,
It is possible to read / rewrite 16 bits (= 4 bits × 4 columns) in a predetermined order.

According to the DRAM of FIG. 14, the shared
Since the sense amplifier system is adopted, the pattern area of the sense amplifier SA on the memory chip can be suppressed, and higher integration and larger capacity can be realized.

In the array of DRAM cells of the method of reading out a plurality of bits of information in time series, the shared
The technology that uses the sense amplifier method is 1991 IEEE ISSCC D
IGEST OF TECHNICAL PAPERS pp.107 "A Block-Oriente
d RAM with Half-Sized DRAM Cell and Quasi-Folded Da
Although it is disclosed in "ta-Line Architecture" K. Kimura et al., this document does not disclose the serial access method like the present invention.

In the DRAM of each of the above embodiments,
Further, a plurality of columns are sequentially selected, and the leading address is set to 1 each time the column selection is advanced by, for example, 1 column.
If the access is performed so as to return only the cells, the read bits of a plurality of columns can be sequentially read. The structure of the cell array in the DRAM of the present invention can be applied to either a folded bit line structure or an open bit line structure.

Further, the bit line sense amplifier SA in the DRAM of the present invention has the bit line BL at one input node.
The present invention can be applied to both a configuration in which only a pair is connected (so-called single-end type sense amplifier configuration) and a configuration in which a pair of input nodes are connected to complementary bit line pairs.

Further, the DRAM of the present invention adopts a folded bit line structure or an open bit line structure. When a transfer gate is provided between the bit line and the sense amplifier, a plurality of pairs of bit lines are formed. The transfer gate may share one sense amplifier, and only one pair of the plurality of pairs of bit lines may be selectively connected to the sense amplifier by controlling the transfer gate.

[0070]

As described above, according to the present invention, there is a method of serially accessing a plurality of memory cells in an arbitrary column in an array of cascaded memory cells, and stored information is stored in serial access. It is possible to omit the register that temporarily stores the information that is sequentially read in time series from the stored memory cells for rewriting, which enables high integration and is realized with a very small chip size. It is possible to provide a semiconductor memory device which can be realized.

Therefore, the external storage device can be operated at high speed by substituting the semiconductor storage device of the present invention for a storage device (such as a magnetic disk used as an external storage device of a computer system) for serially reading / writing data in block units. Can be converted.

Looking at the applications of DRAMs in recent years, the fields that can be handled by serial access such as block transfer to and from cache memory, processing and holding of image data are rapidly expanding. The semiconductor memory device of the present invention has various uses.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example in which one column of a memory cell array, a sense amplifier, and an input / output gate in FIG. 1 is representatively taken out.

FIG. 3 is a circuit diagram showing a part of an example of an addressing circuit and a word line driving circuit in FIG.

FIG. 4 is a timing waveform chart showing an example of operations of the addressing circuit and the word line driving circuit of FIG.

5 is a timing chart showing an example of a serial access operation to a memory cell in an arbitrary column of the DRAM of FIG.

FIG. 6 is a timing waveform chart showing an example of the operation of the DRAM of FIG.

FIG. 7 is a circuit diagram showing another example of the addressing circuit in FIG.

8 is a timing chart showing an example of the operation of the sequential decoder of FIG.

9 is a block diagram showing another example of the addressing circuit and the word line driving circuit in FIG.

10 is a block diagram showing still another example of the addressing circuit and the word line driving circuit in FIG.

FIG. 11 is a circuit diagram showing a part of a DRAM according to a second embodiment of the present invention.

FIG. 12 is a timing chart showing an example of a serial access operation to a memory cell in an arbitrary column of the DRAM of FIG.

13 is a timing waveform chart showing an example of the operation of the DRAM of FIG.

FIG. 14 is a circuit diagram showing part of a DRAM according to a third embodiment of the present invention.

FIG. 15 is an equivalent circuit diagram showing an example of a currently proposed cascade gate type memory cell.

FIG. 16 is an equivalent circuit diagram showing another example of a currently proposed cascade gate type memory cell.

[Explanation of symbols]

30 ... Memory cell array, 31 ... Row address designation circuit, 32, 34 ... Clock generation circuit, 33, 431-4
35 ... Word line drive circuit, 35 ... Sense amplifier, 39 ...
Serial / parallel conversion circuit, 40 ... Even / odd discrimination circuit, 5
1 ... Address counter, 52 ... Decoder, Q1-Q5 ...
MOS transistors, C1 to C4 ... Capacitors, BL,
BLa-BLd ... Bit line, WL0a-WL0e, WLna-
WLne ... Word line, PR ... Precharge circuit, TG, T
Ga to TGd ... Transfer gate, SA ... Sense amplifier, CS ... Column selection switch, I / O, / (I / O)
Input / output line, SR ... Shift register.

Claims (12)

(57) [Claims] 1. A plurality of MOS transistors connected in cascade.
Cascade with both ends of the transistor connected to the same bit line
.Gate and each gate of the plurality of MOS transistors
Connected to the word line and each of the plurality of MOSs
Each end is connected to correspond to the connection node between transistors.
Each has a plurality of connected capacitors for information storage.
Cascaded dynamic memory cells are arranged in a matrix of word lines of the memory cells in the same row, respectively
Commonly connected to the bit lines of the memory cells in the same column in common
The memory cell array connected to the memory cell array and each of the plurality of memory cells in an arbitrary column of the memory cell array are serially accessed, and one to a plurality of bits of the memory cell storing the storage information. Information is read in time series, and this multi-bit information is stored as another piece of stored information in the same column as the above memory cell.
And a serial access control unit that controls so as to sequentially rewrite the memory cells that are not stored. (2)Multiple MOS transistors connected in cascade
A cascade with one end of the transistor connected to the bit line.
The gate and each gate of the MOS transistors
Each connected word line and each of the above-mentioned MOS transistors
It corresponds to the other end of the transistor that is far from the bit line.
And a plurality of capacitors for information storage with each end connected
Cascade type dynamic memory
Words of memory cells in the same row, with cells arranged in a matrix
Lines are connected in common and bit lines of memory cells in the same column are
A memory cell array connected in common, Multiple memos in any column of this memory cell array
Access each memory serially to store
Information from one memory cell that stores the information
Information is read in time series, and this multi-bit information is
Stores another memory information in the same column as the memory cell
Controls to sequentially rewrite to memory cells that are not
Serial access control means And comprising
Semiconductor memory device. 3. The semiconductor memory device according to claim 1 , wherein the plurality of memory cells in the column have n (integer) memory cells for storing continuous block data, and serial access memory cells. A semiconductor memory device having one memory cell for initially writing the block data first. 4. The semiconductor memory device according to claim 3 , wherein the serial access control means includes a sense amplifier provided for each column in the memory cell array and a plurality of memory cells in an arbitrary column in the memory cell array. And a word line drive circuit for selectively driving a word line connected to a memory cell of an address specified by the row address specification circuit. A characteristic semiconductor memory device. 5. The semiconductor memory device according to claim 4 , wherein said serial access control means combines read / rewrite of a plurality of bits of information with respect to two memory cells in said column by a combination of read and rewrite. Of two different memory cells are sequentially performed as a unit, and the serial blocks stored in the n memory cells are serially accessed once for the (n + 1) memory cells in the column. At the same time as reading data sequentially, the stored information is read before this reading.
A semiconductor memory device having a function of controlling to rewrite the block data in n memory cells including one memory cell which is not stored. 6. The semiconductor memory device according to claim 4 , further comprising a transfer gate inserted between the bit line of said column and a sense amplifier and turned on / off at a predetermined timing. The semiconductor memory device characterized in that the gate is controlled to be in an off state immediately after transferring the signal read from the memory cell to the sense amplifier. 7. The semiconductor memory device according to claim 3 , wherein the serial access control means selects one sense amplifier for each of a plurality of columns in the memory cell array, and selects the sense amplifier for the plurality of columns. A switching circuit for electrically electrically connecting the memory cell array, a row addressing circuit for serially addressing a plurality of memory cells in an arbitrary column in the memory cell array, and the row addressing circuit A word line driving circuit for selectively driving a word line connected to a memory cell of an address, and when serially accessing each of the plurality of memory cells in the plurality of columns, sequentially selecting the plurality of columns. The sense amplifier is controlled so as to be shared by the plurality of columns in a time division manner. The semiconductor memory device characterized by having an ability. 8. The semiconductor memory device according to claim 7 , wherein the serial access control means combines read / rewrite of read / rewrite of a plurality of bits of information with respect to two memory cells in the column. Of two different memory cells are sequentially performed as a unit, and the serial blocks stored in the n memory cells are serially accessed once for the (n + 1) memory cells in the column. At the same time as reading data sequentially, the stored information is read before this reading.
A semiconductor memory device having a function of controlling to rewrite the block data in n memory cells including one memory cell which is not stored. 9. The semiconductor memory device according to claim 5 , wherein the serial access control means shifts the start address of a memory cell to be accessed next time by one memory cell for each serial access. A semiconductor memory device having a function of controlling as described above. 10. The semiconductor memory device according to claim 1 , wherein said serial access control means is 1 / k (integer) of the number of word lines of said memory cell array.
A word line connected to a memory cell at an address designated by the output of each stage, and correspondingly controlled by the output of each stage of the shift register or sequential decoder and the shift register or sequential decoder having the number of stages corresponding to Let k be one set that selectively drives (n +
1) A semiconductor memory device comprising a set of word line drive circuits. 11. The semiconductor memory device according to claim 2 , wherein the serial access control means further includes an even / odd determination circuit for determining whether the serial access is an even-numbered serial access or an odd-numbered serial access, and a memory cell. In serial access in which the information of a plurality of bits read from is in the order opposite to the original order, there is provided a correction means for correcting the order of the plurality of bits based on the discrimination output of the even-odd discrimination circuit. A semiconductor memory device comprising: 12. The semiconductor memory device according to claim 11 , wherein the correction means is means for converting serial / parallel information of a plurality of bits read from a memory cell.