JPH0792997B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access and serial access semiconductor memory device useful as an image processing memory.

[Technical background of the invention and its problems]

With the increase in capacity of semiconductor memory devices, the range of purposes for which they have been used has been expanding in recent years. In the era of 16K bits, the demand for frame memory of large computers dominated most, but as the capacity increased to 64K bits and 256K bits, the supply to minicomputers such as minicomputers and microcomputers increased. There is. At the present time of 1 Mbit and 4 Mbit, semiconductor memory devices are beginning to be used as image processing memories. For example, a still image memory of a television is a typical example.

However, when a conventional dynamic RAM (dRAM) is used as a memory for image processing, there are the following problems. First, the access time is 100 nS even if it is short, and it is still long for image processing. page·
When operated in the mode, the access time is shortened to 50 nS, but even in that case, as a second problem for using as an image processing memory, an address counter is required outside the chip. This is to input consecutive addresses from outside the chip. That is, in order to use the conventional dRAM for image processing, an extra external mechanism is required, and as a result, signal exchange between the CPU managing the address and the memory becomes complicated.

Recently, a dual port memory in which a shift register is built in and a normal dRAM is used as a memory for image processing has been proposed. However, in order to realize the serial access mode in which all bits of the memory cell are continuously read or written, a large number of shift registers are required. For example, 1024 in the row direction,
In order to enable serial access by incorporating a shift register in a 1Mbit dRAM that has 1024 addresses in the column direction, 1024 shift registers in the column direction are required. Therefore, in this method, the chip area is significantly increased, resulting in a decrease in yield and an increase in cost.

[Object of the Invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device capable of switching between a serial access mode and a random access mode while minimizing an increase in chip area.

[Outline of Invention]

According to the present invention, a circuit for generating an internal address for a serial access mode is built in a substrate chip of a semiconductor memory device capable of random access. The circuit for generating this internal address is configured by combining an address counter and a shift register. For example, the upper bit of the internal address composed of a plurality of address bits is selected by the address counter, and the lower bit is selected by the shift register.

〔The invention's effect〕

According to the present invention, it is possible to operate the dRAM in a high speed serial access mode by providing a circuit for generating an internal address inside the chip. Moreover, in the present invention, since the circuit for generating the internal address is configured by the combination of the shift register and the address counter, the chip area is not significantly increased unlike the case where only the shift register is used. Therefore, for example, when the dRAM has the function of the image processing memory, it is possible to realize a high-yield and low-cost product without increasing the chip area so much.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block of a memory of one embodiment. In the figure, reference numeral 1 is a semiconductor chip, on which a core circuit 2 and peripheral circuits are integrally formed. The core circuit 2 includes a randomly accessible memory cell array in which memory cells composed of one MOSFET and one MOS capacitor are arranged, a row decoder, a column decoder, a sense amplifier, an I / O circuit, and the like. Peripheral circuit consists of column address buffer 3,
In addition to row address buffer 4, CAS-related clock generator 5, RAS-related clock generator 6, write-related clock generator 7, data input buffer 8 and data output buffer 9, column address counter 10, row address counter 11 And a parallel-serial conversion circuit 12. Parallel - serial converting circuit 12 is composed of second data rat circuit 12 _1, as shown, the shift register for transferring the data latch circuit 12 ₁ of the data to the serial 12 _2. The column address counter 10, the row address counter 11, and the parallel-serial conversion circuit 12 are portions that function for the serial access mode.

That is, random access is performed by the external address EXT.A _O ~ A _N , and the mode switching control signal ▲ from the external terminal.
Input ▼ to control the clock generators 5 and 6, which causes the column address counter 10 to generate the internal address INT.A _O
~ A _NM , internal address IN from row address counter 11
The internal addresses A _{N-M + 1 to} A _N are generated from the TA _{O to} A _N and the shift register in the parallel-serial conversion circuit 12 to perform the serial access mode operation. At this time, the number of stages of shift registers required is 2 ⁿ .

The operation of this memory will be described in detail below.

When the control signal ▲ ▼ is, for example, "H" level, the random access mode is set. That is, when ▲ ▼ is at "H" level, the row address strobe signal (▲ ▼), the column address strobe signal (▲ ▼), the write enable signal (▲
The RAS system clock generator 6, the CAS system clock generator 5 and the write system clock generator 7 are activated according to the timing of ▼), and each operation cycle system such as a read cycle and a write cycle is executed. ▲ ▼ Before ▲ ▼
During auto-refresh such as refresh cycle, the RAS system cook generator 6 operates in synchronization with ▲ ▼ to operate the row address buffer and the sense amplifier. At this time, the internal addresses INT.A _{O to} A _N generated from the row address counter 11 are fetched into the row address buffer 4 instead of the external addresses EXT.A _{O to} A _N.
Row address counter 11 in row address buffer 4
There is provided a multiplexer for switching between the output of and the external address. The column address buffer 3 is also provided with a similar multiplexer, but the column address buffer 10 does not operate in the random access mode. Further, all or a part of the circuits of the data latch circuit and the shift register constituting the parallel-serial conversion circuit 12 are in a nibble mode for continuously reading or writing 4-bit data or 8-bit or 16-bit data. It also works when you continuously access and fulfill its function. For example, when the shift register has eight stages, four bits of the shift register are activated in the nibble mode.

Next, when the control signal ▲ ▼ becomes "L" level, this memory enters the serial access mode. That is, the memory cells are continuously selected by the internal address output from the column address counter 10 and the row address counter 11 regardless of the external address, and a plurality of memory cells are sequentially selected by the shift register 12 ₂ through the data latch circuit 12 _1. The memory cells are continuously accessed. This serial access mode will be described in detail.

Referring first control signal ▲ ▼ becomes "L" level, the column address counter 10 by the clock generator 5 and 6, the row address counter 11, shift register 12 ₂ is reset, respectively the minimum column address as an internal address, the minimum Outputs row address. The output internal address is taken into the column address buffer 3 and the row address buffer 4. Row address buffer 4
When at least one or more word lines are selected after the output of the column address buffer 3 is input to the row decoder and the output of the column address buffer 3 is input to the column decoder, at least one line is selected. or more bit lines is selected, this is a plurality of I / O lines and the data latch circuit 12 ₁
Connected to. For example, in the case of 1M bit dRAM, 10 bits in the row direction as the address bits (2 ¹⁰ = 1024), because the address bits in the column direction in 10 bits (2 ¹⁰ = 1024) are present, the shift register 12 ₂ to 4 stages If the column address counter 10 has 8 bits, the column address counter 10 may have 8 bits. When the shift register 12 ₂ to 3 bits in the eight-stage, the column address counter 10 is the 7-stage 7
Just make it a bit.

FIG. 2 shows an example of the order in which memory cells are selected in the serial access mode, and FIG. 3 shows the waveforms of ▲ ▼, ▲ ▼ and ▲ ▼ at that time. is there. That is, ▲ ▼ goes to "L" level, and then ▲ ▼ and ▲ ▼ go to "L" level sequentially, so that the word line WL ₁ is selected, and the first memory cell ~ along this word line WL ₁ is selected. I / O line I
Connected to / O _{1 to} I / O ₄ . I / O _{1 to} I / O ₄ are connected to the data latch circuit 12 ₁ , and the output of the column address counter 10 is supplied to the shift register 12 ₂ as a shift pulse. The reading or writing of the memory cell is performed by the first stage of the output signal of the shift register 12 _2. Then ▲ ▼ is "H" 2-stage shift register 12 ₂ becomes the level is pre-charged, ▲ ▼ is "L" by the output signal second stage that is operated by a level of the memory cell Read or write is performed. Thus ▲ ▼ more "H" level, repeated "L" level, thereby the contents of the shift register 12 ₂ is access to the memory cells is shifted by one step are sequentially performed. That is, the data taken in from the memory cell array to the data latch circuit 12 ₁ at the time of reading is the shift register 12 ₂
Is serially read out and taken out to the data output buffer 9, and at the time of writing, the input data from the data input buffer 8 is taken into the data latch circuit 12 ₁ by the shift register 12 _{2 in} sequence.

Next, when ▲ ▼ becomes "H" level to select the memory cell, the column address buffer 3 and the column decoder are precharged, and the output address of the column address counter 10 advances by 1 bit. And ▲
When ▼ becomes "L" level, the column address buffer and the column decoder operate to connect the memory cell groups ~ on the word line WL ₁ to I / O _{1 to} I / O ₄ , respectively.

After that, ▲ ▼ shows "H" level as shown in Fig. 3,
Repeat "L" level, 2 ^n-th ▲ ▼ column address counter 10 by the falling of the outputs the maximum column address, the last memory cell group 2 ⁿ -3~2 ⁿ with respect to the word line WL ₁ Connected to I / O _{1 to} I / O ₄ , and read or write.

The column address counter 10 is reset to the minimum column address by the ^2n- th rise of ▲ ▼, and the output address of the row address counter 11 is advanced by 1 bit. Along with this, column address buffer 3, column
Not only decoder, but row address buffer 4, row
The decoder and bit line are precharged. And ▲
By the 2 ⁿ + 1st fall of ▼, the first memory cell group 2 ⁿ +1 to 2 ⁿ +4 along the next word line WL ₂ is connected to I / O _{1 to} I / O ₄ for sequential read or write. Is done.

The same operation is repeated thereafter, and when the output of the row address counter 11 reaches the maximum row address, the row address counter 11 and the column address counter 10 are reset.

As described above, according to this embodiment, it is possible to easily switch between the random access mode and the serial access mode, thereby realizing a memory having an expanded application range. Moreover, since the internal address for the serial access mode is generated by the combination of the address counter and the shift register, the chip area does not increase unlike the case where only the shift register is used.

The present invention is not limited to the above embodiments, and various modifications can be carried out without departing from the spirit of the present invention. For example, even if there is no row address counter,
It is possible to realize the serial access mode by combining the column address counter and the shift register, and the present invention is also effective in that case. The present invention can be applied not only to dRAM but also to static RAM.

[Brief description of drawings]

FIG. 1 is a diagram showing a memory configuration of an embodiment of the present invention, and FIG.
FIG. 3 and FIG. 3 are diagrams for explaining the operation of the memory in the serial access mode. 1 ... Semiconductor chip, 2 ... Core circuit, 3 ... Column
Address buffer, 4 ... Row address buffer, 5
...... CAS clock generator, 6 RAS clock generator, 7 write clock generator, 8 data input buffer, 9 data output buffer, 10 column
Address counter, 11 ... Row address counter, 12
...... Parallel-to-series conversion circuit, 12 ₁ …… Data latch circuit, 1
2 ₂ ...... Shift register, ▲ ▼ …… Mode switching control signal.

Claims (4)

[Claims] 1. A semiconductor memory device formed by integrating a core circuit including a randomly accessible memory cell array and a peripheral circuit on a semiconductor chip, comprising a circuit for generating an internal address for a serial access mode, The circuit that generates the internal address is
A semiconductor comprising a combination of an address counter and a shift register, wherein the internal address comprises a plurality of address bits, the upper address bits of which are selected by the address counter and the lower address bits are selected by the shift register. Storage device. 2. A semiconductor memory device formed by integrating a core circuit including a randomly accessible memory cell array and a peripheral circuit on a semiconductor chip, a circuit for generating an internal address for a serial access mode, and this circuit. And an external address for the random access mode, and a circuit for generating the internal address is composed of a combination of an address counter and a shift register,
The semiconductor memory device according to claim 1, wherein the internal address is composed of a plurality of address bits, an upper address bit thereof is selected by the address counter, and a lower address bit thereof is selected by the shift register. 3. The semiconductor memory device according to claim 1, wherein the memory cell array is a randomly accessible memory cell array using a memory cell composed of a set of MOSFETs and a MOS capacitor. . 4. The address counter according to claim 1, wherein the address counter comprises a row address counter for outputting a row-direction internal address and a column address counter for outputting a column-direction internal address. Semiconductor memory device.