JP2703642B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that performs a sequential read / write operation.

[Conventional technology]

FIG. 36 is a block diagram showing an example of a conventional semiconductor memory device. In the figure, reference numeral 1 denotes a row address input, 2 denotes a row address buffer for amplifying or inverting the address input 1, and 3 denotes a row address input. 4 is a column address input, 5 is a column address buffer for amplifying or inverting the column address input 4, and 6 is a column address given to the column address input 4. It is a column address decoder for decoding a signal. Reference numeral 7 denotes a memory cell array (hereinafter referred to as a block) in which memory cells for storing information are arranged in a matrix, 8 denotes a multiplexer, 9 denotes a sense amplifier that senses and amplifies a read voltage having a small amplitude, and 10 denotes an output of the sense amplifier 9. Further, an output data buffer for amplifying to a level to be taken out of the semiconductor memory device, 11 is a read data output, 12 is a write data input, and 13a is a write data input 12
An input data buffer for amplifying the signal given to the memory cell 13b is a write driver for writing data to the memory cell. 14 is a chip select input, 15 is a read / write control input, 16 is the sense amplifier 9, output data buffer 10, write data buffer 13a, write driver 1 according to chip selection / non-selection and data read / write mode.
A read / write control circuit for controlling 3b and the like, and 99 is a data bus connecting the sense amplifier 9 and the output data buffer 10 and connecting the write driver 13b and the write data buffer 13a.

FIG. 37 is a block diagram showing in detail a peripheral portion of a memory cell of the semiconductor memory device shown in FIG. 36. Here, for simplicity of description, a configuration having two rows and two columns is used. In the figure, 20a, 20b and 21a, 21b are corresponding bit line pairs, respectively, 22 and 23 are word lines connected to the output point of the row address decoder 3, and 24a to 24d are word lines 22, 23 and bit lines. Memory cells 25a, 25b and 26a, 26b arranged at the intersections of the line pairs 20a, 20b and 21a, 21b are bit line loads having one end connected to the power supply 18 and the other end connected to the bit line. 27a, 27b and 28a, 28b
The output signal of the column address decoder 6 is input to the gate, and the drain or source is connected to the bit lines 20a, 20b and 2
A transfer gate which is connected to 1a, 21b and whose source or drain is commonly connected to an input / output line (hereinafter referred to as I / O line) pair 29a, 29b, and which constitutes the multiplexer 8. 9
Is a sense amplifier for detecting a potential difference between the I / O line pair 29a and 29b, and 10
Is an output buffer for amplifying the output of the sense amplifier 9. In addition, with the increase in the number of memory cells, if many memory cells 24 are attached to the word lines 22 and 23, the load on one word line increases. Therefore, it is not preferable for high speed access time and low power consumption. As a solution to this, block 7
Are reduced to reduce the load on one word line. For this reason, a block address for selecting each block is required.

As the memory cell 24, for example, a high resistance load type NMOS memory cell shown in FIG. 38 (a) or a CMOS type memory cell shown in FIG. 38 (b) is used. Here, FIGS. 38 (a) and 38 (b)
The NMOS and CMOS memory cells will be described in detail with reference to FIGS. 41A and 41B. N-channel driver transistors 41a and 41b have drains connected to the storage nodes 45a and 45b, gates connected to the other drains, and sources connected to the ground 19, 42a. , 42b have drains or sources connected to storage nodes 45a, 45b, gates connected to word lines 22 or 23, and sources or drains connected to bit lines.
An N-channel access transistor 43a, 43b connected to 20 or 21 has one end connected to the power supply 18 and the other end to storage nodes 45a, 45b.
The load resistors 44a and 44b are P-channel transistors having a drain connected to the storage node, a gate connected to the other drain, and a source connected to the power supply 18.

Next, the operation will be described. First, when selecting the memory cell 24a, a row address signal corresponding to the row where the memory cell 24a to be selected is inputted from the row address input 1, and the word line 22 to which the memory cell 24a is connected is selected ( For example, the High level is set, and the other word lines 23 are set to the non-selected (for example, Low) level. Similarly, when selecting a bit line, the memory cell 24 to be selected from the column address input 4
a and a bit line pair 20a, 20 to which the memory cell 24a is connected.
A column address signal corresponding to the column where b is located is input,
Since only the transfer gates 27a and 27b connected to the bit line pair 20a and 20b conduct, the selected bit line 2
0a and 20b are connected to the I / O line pair 29a and 29b, and the other bit lines 21
a and 21b are not selected and are disconnected from the I / O line pair 29a and 29b. The operation timing at this time is shown in FIG. In the figure, A _IN is an address input, A _OUT is an address buffer output, WL is a word line, I / O is an I / O line, SA _OUT is a sense amplifier output, and D _OUT is a data output.

Next, a read operation of the selected memory cell 24a will be described.

Now, it is assumed that the storage node 45a of the memory cell is at the high level and the storage node 45b is at the low level. At this time, one driver transistor 41a of the memory cell is non-conductive, and the other driver transistor 41b
Is in a conductive state. Since the word line 22 is in the selected state of High, the access transistors 42a and 42
b are both conductive. Therefore, a DC current is generated in the path of the power supply V _CC 18 → the bit line load 25 b → the bit line 20 b → the access transistor 42 b → the driver transistor 41 b → the ground 19. However, the other path, power supply V _CC 18 →
Bit line load 25a → bit line 20a → access transistor
In the path from 42a → driver transistor 41a → ground 19, no DC current flows because the driver transistor 41a is non-conductive. At this time, the bit line where no DC current flows
The potential of 20a is the bit line load transistor 25a, 25b, 26a, 2
If the threshold voltage of 6b is Vth, it becomes [power supply potential-Vth].
The potential of the bit line 20b through which the direct current flows is divided by the resistance of the conduction between the driver transistor 41b, the access transistor 42b, and the bit line load 25a, and the potential drops by ΔV from [power supply potential -Vth]. , [Power supply potential−Vth−ΔV]. Here, ΔV is called a bit line amplitude, which is usually about 50 mV to 500 mV, and is adjusted according to the magnitude of the bit line load. This bit line amplitude appears on the I / O lines 29a and 29b via the transfer gates 27a and 27b, and is amplified by the sense amplifier 9 and further output buffer 10a.
And is read out as the data output 11. In the case of reading, the write data buffer 13a and the write driver 13b do not drive the I / O line pair 29a, 29b by the read / write control circuit 16. In the case of writing, writing is performed by forcibly lowering the potential of the bit line on which Low data is written to a low potential and raising the potential of the other bit line to a high potential. For example, to write inverted data in the memory cell 24a, data is sent from the write data buffer 13a to the write driver 13b, and the write driver 13b sets one I / O line 29a to a low level and the other I / O line The write operation is performed by setting 29b to the high level, setting one bit line 20a to the low level, and setting the other bit line 20b to the high level.

[Problems to be solved by the invention]

The conventional semiconductor memory device is configured as described above. Data read / write of an arbitrary memory cell is always selected by using two sets of addresses of a row and a column. I needed it. On the other hand, in an image processing apparatus or the like that requires a high-speed operation, it is not always necessary to read / write an arbitrary address as a semiconductor memory device, but to read / write addresses in a certain order (hereinafter referred to as serial access). Call) and high-speed performance is emphasized. However, the shift register takes a large area to serially access many data at high speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor memory device capable of high-speed serial access without increasing the area of a shift register.

[Means for solving the problem]

A semiconductor memory device according to the present invention includes a first-stage shift register to which a lower-order address data or an address signal is inputted, and a second-stage shift register to which a higher-order address data or an address signal is inputted. It is a layered shift register using registers. Further, a counter is used for selecting a row address, and a shift register is used for selecting a column address. Further, when a memory block storing data to be accessed is switched to the next block, word lines existing in both blocks are simultaneously activated for a certain period. Further, when the memory block storing the data to be accessed is switched from the end to the head, the word lines existing in both blocks are simultaneously activated for a certain period.

[Action]

A semiconductor memory device according to the present invention includes a first-stage shift register to which a lower-order address data or an address signal is inputted, and a second-stage shift register to which a higher-order address data or an address signal is inputted. Since the shift register is hierarchized by using (1) and (2), the number of bits of the shift register can be reduced, and as a result, the area of the shift register can be reduced. Since a counter is used to select a row address and a shift register is used to select a column address, high-speed serial access can be performed.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a semiconductor memory device according to one embodiment of the present invention. In this embodiment, a case having 32 divided blocks is shown.
Arrows indicate main signal flows. In the figure, reference numeral 101 denotes a serial normal controller which switches between a serial and random access mode and controls serial access. 102 is a data bus shift register, 103 is a transfer gate shift register,
Select a column address. A sense amplifier write driver shift register 104 selects the sense amplifier 9 and the write driver 13 for each block. 105
Is a block word line shift register for selecting a word line 22 in block units. Reference numeral 107 denotes a normal row address counter which outputs row address data to the row address decoders 3 of blocks 1 to 31 except for block 0. 108
Is a prefetch row address counter, which outputs row address data to the prefetch row decoder 109 of block 0. A pre-read row decoder 109 selects the word line 22 of the block 0 in the serial mode. Reference numeral 110 denotes a normally only row decoder, which selects the word line 22 of the block 0 at the time of random access. A transfer gate shift generator 111 controls a shift operation of the transfer gate shift register 103 by a signal from the data bus shift register 102. 112 is a sense amplifier / write driver shift generator, which is a data bus shift register.
A shift operation of the sense amplifier / write driver shift register 104 is controlled by signals from the transfer gate shift register 102 and the transfer gate shift register 103. 113 is a block word line shift generator, which is a data bus shift register 10
The shift operation of the block word line shift register 105 is controlled by a signal from the transfer word shift register 103 and the transfer gate shift register 103. Reference numeral 114 denotes a row address count generator (hereinafter abbreviated as a count generator), which controls the counting operation of the normal row address counter 107 and the pre-read row address counter 108 by a signal from the block word line shift register 105. 116 is a data bus selector.

In the following description, a 4M × 1 configuration will be described as an example. The column address is Y0 to Y6, and the block address is Y7
Consider a case in which there are five lines of ~ Y11 and ten line addresses of X0 ~ X9. Y3 to Y6 of the seven column addresses are specified by the data bus shift register 102. Similarly, column addresses Y0 to Y
2 is a transfer gate shift register 103; block addresses Y7 to Y11 are sense amplifier / write driver shift registers 104 and row shift registers 105; row addresses X0 to X9 are normal row address counters 107, prefetch row address counters 108, and block words. Line shift register
At 105, it is specified by the prefetch row selection decoder 109 and the decoder 3.

Next, in describing the operation of the present invention, an address selection method at the time of serial access will be described with reference to FIG. In the following, the serial access is mainly described for the read operation.

One row is selected by the row address counters 107 and 108. Next, only the word lines of one block are selected by the block word line shift register 105. Normally, when one block is read, 16 sense amplifiers 9 are transferred to the transfer gate shift register 103 by the write driver shift register 104 of the sense amplifier.
As a result, the transfer gate 27 becomes 16 in one block.
A pair is selected. The data output through the 16 pairs of transfer gates 27 is amplified by the sense amplifier 9 and
The data is output to the data bus 99. The data bus shift register 102 selects one of the 16 data buses, and one bit is selected.

Next, the operation of each register and shift generator will be described.

First, when the selection of all 16 data buses is completed by the data bus shift register 102, the data bus shift register 102
The transfer shift generator 111 receives the signal and transfers the signal to the transfer gate shift register 103.
In the shift operation. As a result, the next 16 pairs of transfer gates 27 are selected, and the data bus 99 is selected by the data bus shift register 102. Here, when the selection of the transfer gate 27 further completes, the block word line shift generator 113 and the sense amplifier / write driver shift generator 11
By means of 2, the shift operation of the block word line shift register 105 and the sense amplifier / write driver shift register 104 is performed, and the word line and the sense amplifier or the write driver of the next block are selected.

Similarly, blocks 0 to 31 operate, but when returning from block 31 to block 0, the count generator
Since the row address is counted up by 114, serial access is performed to the next row address.

As described above, address selection at the time of serial access is realized. Also, compared to address selection from the address buffer at random access, in the serial mode, address selection is performed from the shift register, so there is no decoding time, so that access can be performed at a higher speed than in random access. Data bus shift register 102, transfer gate register 103, sense amplifier / write driver shift register 104, and block word line shift register 1
05, the row address counters 107 and 108 operate in this order, and the shift registers and counters are hierarchized.

Here, the hierarchization of the shift register will be described with reference to FIG. 2 taking a 16-bit shift register as an example.

First, when the data is not hierarchized, it is composed of 16 bits as shown in FIG. 2 (b).

Next, as shown in FIG. 2 (c), for example, considering the hierarchization of two layers, it is possible to reduce the number of shift registers by two to 8 bits of 4 bits + 4 bits, that is, 8 bits compared to before the layering. Can be. To select an address,
For the second layer i bits (i = 0 to 3), the first layer 0 to 0
Three bits are performed, for a total of 16 bits. With such a hierarchical structure, the number of bit lines and the area of the shift register can be reduced.

Here, the difference between the shift register and the counter will be described.

Here, as an example, consider three addresses Y0, Y1, and Y2. As shown in FIG. 2 (d), assuming that ● is an “H” state and ○ is an “L” state, the shift register is controlled by a clock or the like and moves bits. The bit is ○. Therefore, when used as storage for an address system, it is used as storage for a decode signal.

On the other hand, in the counter, as shown in FIG. Therefore, when it is used as storage for an address system, it is used for storing output signals of an address buffer.

In this case, the shift register has 8 bits and the counter has 3 bits.
It becomes a bit configuration. Thus, the counter is more effective in reducing the number of bits and the area. However, since the counter is used as the output signal of the address buffer,
It is necessary to decode, and the operation is slower than the shift register already decoded. For this reason, in the serial circuit of the present invention, a shift register is used for a column system in which an address changes at high speed, and a row system having a sufficient time only for changing while the column system is changing is used for the purpose of area reduction. A counter is used.

Hereinafter, the configuration of each shift register and counter and the serial operation method will be described.

FIG. 3 shows a sense amplifier 10 for one block of a path-out system.
FIG. 4 is a detailed block diagram showing the configuration around the data bus shift register 102 and the data bus shift register 102. In FIG.
And eight columns are connected to each sense amplifier 9 through the transfer gate 27. The outputs of the 16 sense amplifiers 9 are transmitted to the 16 data buses 99, one data bus is selected by the data bus shift register 102 by the data bus selector 116, and read data is output. At this time, one of eight transfer gates 27 is selected by the transfer gate shift register 103, and one is selected by the sense amplifier / write driver shift register 104.
The sense amplifiers 9 for the blocks, that is, all 16 sense amplifiers in FIG. 3 are selected. The transfer shift register 103 is a transfer gate 27 for each block.
It is connected with.

FIG. 4 shows the state of the lowest data bus shift register 102 in the hierarchical shift registers. This data bus shift register 102 is composed of 16 bits,
The numeral 5 indicates the bit number of the data bus shift register, and the data bus of the number corresponding to the bit number of the shift register is selected by the data bus shift register 102. The data bus shift register 102, the transfer gate shift register 103, and the sense amplifier / write driver shift register 104 are each divided into two banks A and B. For example, in FIG. 4, the data bus shift register 102 has numbers A, 0, 1, 4, 5, 8, 9, 12, 13 of bank A and numbers 2, 3,
6, 7, 10, 11, 14, and 15 belong to bank B.

In FIG. 3, the transfer gate shift register 10
3 and sense amplifier / write driver shift register 1
04 is divided into banks A and B respectively, and 16 columns from the left end of the block, two for the sense amplifier 9 and numbers 0 and 1 for the data bus 99 belong to bank A,
Each of the next 16 columns, two sense amplifiers 9, and the numbers 2 and 3 of the data bus 99 belong to the bank B. Thus, the data bus shift register 102, the transfer gate shift register 103, the sense amplifier write driver shift register
104 is divided into banks A and B.

Next, the operation of these shift registers will be described.

FIG. 5 shows a timing chart of the data bus shift register 102 and the transfer gate shift register 103. As an example here, the start address of the serial access is block 0, and the transfer gate is the 0th. The serial mode of this embodiment is performed by inputting a serial enable signal and an external clock signal to the serial normal controller 101. Fig. 5 (a)
The uppermost waveform shows this external clock.
2 operates, the data bus 99 is sequentially selected from 0 to 15, and outputs data serially. The output data is A, A, B, B,
AA... And banks A and B alternately appear twice. When the data on the data bus 13 is output, the data output is completed for the 0th bit data of the transfer gate of the bank A. While the 14th and 15th data on the data bus 99 are being output, the transfer gate of the bank A is operated by the transfer gate shift generator 111 to shift the transfer shift register 103 of the bank A during the period a in FIG. Next, the first bit of the transfer gate is selected. Fig. 5 (a) from the top 2
And the third waveform corresponds to this. Similarly, bank B is the data bus of the first bit of the transfer gate of bank A.
During the period b during which the 0th and 1st bits are read, the transfer shift register 103 of the bank B is shifted by the transfer gate shift generator 111, and then the first bit of the transfer gate is selected. In the same manner, transfer gates 1 to 7 are performed in the same manner. FIG. 5B shows this operation.

Next, FIG. 6 shows a timing chart when a block changes from block 0 to block 1 as an example.

After the 7th bit, the transfer gate returns to the 0th bit by the same operation as described above. Similarly, the sense amplifier / write driver shift register 104 shifts the bank A by the sense amplifier / write driver shift generator 112 during the period a and the bank B during the period b. Write driver is selected.

In this way, the data is divided into two banks, and while the data of one of the banks is being accessed, the other bank performs a shift operation, so that the transfer gate 27 can be accessed at the time when the selection of the sense amplifier 9 is switched. To eliminate the delay.

On the other hand, in the word line 22 selected by the block word line shift register 105, the word line 22 has a large capacitance and a large resistance, and thus requires a long selection time. Therefore, the sixth
As shown in the figure, when the fourth data from the end of block 0 starts to be read, the block word line shift register 105 shifts the block word line shift register 105 by the block word line shift generator 113, and the word line of block 1 also rises. When all the data of block 0 has been read, the block word line shift register 105 shifts the block word line shift register 105 to unselect the word line of block 0. In the period c in FIG. 6, the word lines 22 are double-selected, that is, the word lines 22 of the next block are simultaneously selected, thereby eliminating the delay of the access time due to the next block switching.

As described above, the data from the block 0 to the block 31 can be serially accessed at high speed by the word line 22 of one row.

Next, a method for switching the next row address to the word line 22 will be described.

FIG. 7 is a diagram showing a configuration related to the selection of the word line 22 of the block 0 and the block 1. The normal row address counter 107 is a counter for the row addresses of the blocks 1 to 31, and the prefetch row address counter 108 is a counter for the row address of the block 0. Block 0 has two row decoders, and one is a normal only row decoder for selecting a word line e during normal random access.
Reference numeral 110 denotes a pre-read row decoder 109 for selecting a word line at the time of serial access.

Now, it is assumed that the word line d of the block 1 is selected. At this time, the block word line shift register 105 sends a signal to the count generator 114. The count generator 114 sends a count signal to the prefetch row address counter 108. The prefetch row address counter 108 increases the row address by one and sends an address signal to the prefetch row decoder 109. Thus, while the word line d of the block 1 is selected, the block 0 is prepared so that the word line e of the next row address can be selected. And blocks
When the data of the 31 word line 22 becomes four data before the end of reading, the block word line shift register 105 operates the pre-read row decoder 109 of the block 0 and the word of the block 0 as in the case of the block change shown in FIG. Line e is selected. On the other hand, when the data of block 0 starts to be read,
Block word line shift register 105 sends a signal to count generator 114. Count generator 114 sends a count signal to normal row address counter 107. The normal row address counter 107 increases the row address by one and sends an address signal to the row decoder 3 of the blocks 1 to 31. Thus, while the word line e of the block 0 is selected, the blocks 1 to 31 are prepared so that the word line of the next row address can be selected.

As described above, even when the row address is switched, by dividing the row decoder system into two types of prefetch and normal,
It is possible to access the serial without delay.

Here, the count of the row address of the block 0 is shown as an example when the word line d of the block 1 is selected, but the count is similarly performed when the word line 22 of any of the blocks 1 to 31 is selected. Operate.

Next, a specific circuit example and operation of each component block will be described.

8 and 9 are specific circuit diagrams of the serial normal controller 101. In this embodiment, the external pin SE
Is "L", the serial mode is set, and a clock is input to the Y3 address to increment the serial access address.

In the circuit of FIG. 8, when a serial mode enable signal is received from an external pin, it indicates that the circuit has entered the serial mode. The signal lines SE, ▲ ▼ and the signal lines SL, φ _IA , φ _IB operate to write the serial access start address to each shift register and counter (115 is a delay circuit, as shown in FIG. 10, It consists of an inverter capacitor and adjusts the delay time by adjusting the number of answers).

FIG. 11 shows the above signal lines, external ▲ ▼, SE, ▲
▼, SL, φ _IA , φ _IB show timing waveform diagrams. External signal S
When E becomes “L”, the signal line SL outputs a pulse signal. As a result, the current row and column addresses are written into each shift register and counter. This is the start address for serial access. Next, signal lines φ _IA and φ
_{The IB} outputs a pulse signal (depending on the start address, whereby the shift generators 111, 112, 113 and the count generator 114 operate).
φ _IA and φ _IB are given so that the pulse of each signal line does not overlap so as not to destroy the latch data of each shift register and counter. After these three signals, the signal line SE becomes “H” and the signal line ▲ ▼ becomes “L”, and the serial access operation is started. Hereinafter, the period of these three signals will be referred to as an initialization period.

In the circuit of FIG. 9, when a clock is input to the external pin Y3, the circuit functions to send a signal to each shift register and counter. The signal lines φ _A and φ _B control each shift generator and count generator. Signal line φ _B ′, φ
▲ ▼, φ _Y3D controls the data bus shift register 102. The signal lines Y3, ▲ ▼ are input to the Y3, Y4, Y5, Y6 decoder 120 in the data bus selector 116. The signal line ATDS is an address change detection signal in the serial mode.

 FIG. 12 shows a timing waveform chart of each of the above signals.

Signal line SE is "H", the signal line ▲ ▼ is "L" and later becomes initiatives rise period, the clock signal signal line signal without overlapping the input phi _A of the external Y3, phi _B is output (external Y3
Fall in pulse phi _A is rising pulse phi _B of the external Y3 is generated) of. The specific operation of each signal will be described in each circuit.

FIG. 13 shows the configuration of the data bus shift register 102. The data bus shift register 102 has a total of 16 bits, numbers from 0 to 15 indicate bit numbers of the registers, and alphabets A and B indicate banks. The registers are divided into two groups, an even number and an odd number, and shift data in each group. Signal line OSRPi (i =
0 to 15) are signal line names sent from the i-th bit to the next (i + 1) -th bit. However, OSR14 and OSR15 are sent to 0 and 1 bits, respectively. A signal line OSRi (i = 0 to 15) is an output signal line of each bit to the Y3Y4Y5Y6 decoder 120 shown in FIG. For example, the 0th bit of the data bus shift register 102 receives the data of the signal line OSRP14 output from the 14th bit of the data bus shift register 102 as input, and the signal line OSRP0
And outputs the second bit of the data bus shift register 102 to the Y3Y4Y5Y6 decoder 120 via the signal line OSR0.

In general, a shift register performs a data shift operation. Hierarchically, the access time of serial access is determined at the lowest order. Data bus shift register
102 requires a high-speed shift, the first phase is the logical product of φ ▲ ▼ and φ _Y3D , the second phase is φ _B ′, and the external Y3 is “H” → “L”, “L” → “ Occurs when "H" is reached. Therefore, the data bus shift register 102 sets the external Y3 to “H” →
The shift operation is not completed unless it changes from “L” to “H”.

Therefore, the external Y3 cannot output serial data in each of “H” → “L” and “L” → “H”. However, in the present embodiment, by performing the following, the external Y3 can output serial data in each of “H” → “L” and “L” → “H”.

That is, as described above, the normal shift register 1
Only the bits are “H” and the others are “L”. However, this is always set to "H" for 2 bits, and the logical AND of the lower address bit and the upper address bit Y3 in FIG. This is connected to the data bus selector 116. This enables the data bus corresponding to the lower bit when external Y3 goes from “H” to “L”.
99 is selected, and when the external Y3 changes from “L” to “H”, the data bus 99 corresponding to the higher bit is selected. As described above, by using the logical product signal of the 2-bit selection of the data bus shift register 102 and the in-phase and out-of-phase signals of the external Y3, the data bus can be selected at half the speed of the shift register operation. Can be.

Hereinafter, the data bus shift register 102 will be described in more detail.

FIG. 14 is a specific circuit configuration diagram of one bit of the data bus shift register 102. In FIG. 14, reference numeral 117 denotes a master latch, and 118 denotes a slave latch. NAND circuit 119
, Two of the decode signal lines Y3D0 to Y3D15, which are the outputs of the column address buffers 5 of Y3, Y4, Y5 and Y6 shown in FIG. ▲ ▼ and ▲ for even bits
▼ (i = 0 even number of 0 to 14), and odd number data bus shift register 102 have ▲ ▼ and ▲ ▼ (i =
(Odd number from 1 to 15). That is, register numbers 0 and 1, 2
, 3,..., 14 and 15 each receive the same decode signal. In normal random access, one of ▲ (i = 0 to 15) is “L”, and the other is “H”. For this reason, only two out of the 16 data bus shift registers 102 have the output of the NAND circuit 119 being “H”.
Here, assuming now that the serial mode has been entered, the signal line SL emits a pulse signal as shown in FIG. As a result, the transfer gates 120 and 121 open. And NA
Only two bits in the data bus shift register 102 from which the ND circuit 119 outputs “H”, the node f becomes “H”,
The signal lines OSRi and OSRPi also become “H”. The start value of the serial mode of the data bus selection address has been written to the data bus shift register 102 by the pulse signal of the signal line SL.

Next, it is assumed that serial access starts after the start address is written. FIG. 15 shows the operation of each signal line in FIG. 14, and shows the case where the start address is written in the 14th and 15th bits of the data bus shift register 102. External Y3, φ ▲ ▼, _φY3D ,
φ _B ′ is shown in FIG. φ ▲
When both ▼ and φ _Y3D become “H”, the data of OSRPI-2 is transmitted to the node f. OSRP is activated by the pulse signal operation of signal line SL.
14 and OSRP15 are "H", and the others are "L". No.
13 As shown in FIG, 0 and 1 bit of the data bus shift register 102, since the respective enter OSRP14, OSRP15, as shown in FIG. 15, phi ▲ ▼ and phi _Y3 are both "H" Then, the 0th bit and the 1st bit of the node f become "H", and OSR0 and OSR1 become "H". Then phi 'when _B is operated pulse, OSRP0 and OSRP1 becomes "H". When the next φ ▲ ▼ and _φY3D are simultaneously “H”, OSR2 and OSR3 become “H”, and the other OSRi become “L”.

FIG. 16 shows a block diagram of the data bus selector 116, which comprises a Y3Y4Y5Y6 decoder 120 and a selector unit 121, as shown in FIG.

FIG. 17 is a circuit diagram of the Y3Y4Y5Y6 decoder 120. In this figure, i indicates a decoder number and a bit number of the data bus shift register 102. SE during normal random access and serial mode initialization
= “L”, ▲ ▼ = “H”, the output of the NAND circuit 122 passes through the transfer gate 123 and is transmitted to the signal line OSi. on the other hand,
N during serial access because SE = “H” and ▲ ▼ = “L”
The output of the AND circuit 124 is transmitted to the signal line OSi through the transfer gate 125.

Thus, the outputs of the NAND circuits 122 and 124 are switched by SE and ▲ ▼. The NAND circuit 122 has four inputs and outputs from the column address buffer 5 in FIG.
Y4 or ▲ ▼ for ▼, h, Y5 or ▲ ▼, j for i
Enter Y6 or ▲ ▼. Therefore, there are 16 combinations, and there are 16 Y3Y4Y5Y6 decoders 120. Although an example of a four-input NAND is shown here, it is also possible to first pre-decode with Y3Y4Y5Y6, and then use a two-input NAND. The output data ▼ from the NAND circuit 122 is sent to the data bus shift register 102, and is used at the time of setting the start address of serial access. The NAND circuit 124 receives Y3 or ▼ shown in FIG. 9 and the output OSRi (i = 0 to 15) of the data bus shift register 102. Where i in OSRi is even, ▲ ▼
However, Y3 enters where it is odd.

Based on the waveform diagram in Fig. 15,
The operation of the Y3Y4Y5Y6 decoder 120 will be described. OSR0 and ▼ are input to the 0th of the Y3Y4Y5Y6 decoder 120, and OS0 is an output. First, OSR1 and Y3 are input, and OS1 is output. Now, in period k in FIG. 15, OSR0,
Both OSR1 are “H”. Also ▲ ▼
Is in phase with the external Y3, and Y3 is an in-phase signal. For this reason,
OS0 is “H” when external Y3 is “L”, OS when external Y3 is “H”
1 becomes “H”. Similarly, OS2, OS3... OS15 sequentially become “H”.

FIG. 18 shows the selector 121 and the output data buffer 10
The selector section 121 is composed of 16 transfer gates, the drain is connected to the data bus, the gate corresponds to each data bus number, the output OSi of the Y3Y4Y5Y6 decoder 120 is input, and the source side is Are output to the output data buffer 10 in common. When OE is “H”, the output data buffer 10 outputs the input data as a data output. When OE is “L”, the data output is floating. Now, when OE is “H”,
As described in the description of the operation of the Y3Y4Y5Y6 decoder 120, OS0, OS1,..., OS15 sequentially become “H”, so that the data No. 0 to No. 15 of the data bus 99 are sequentially output as the data output.

As described above, 16 data bus data are read serially by the operation of the data bus shift register 102.

Next, the data bus shift register 102 shown in FIG.
The operation of the transfer gate shift register 103 will be described based on a specific circuit example.

Figure 19 shows the transfer gate shift generator 111
FIG. 20 shows a configuration diagram of the transfer gate shift register 103. As shown in FIG. The transfer gate shift register 103 has a 16-bit configuration, and each of the 8 bits belongs to the banks A and B. The number in the square indicates the bit number of the transfer gate shift register 103, and the transfer gate 27 corresponding to the number is selected by the signal line TGAi or TGBi. As shown in FIG. 3, eight transfer gates 27 are connected to one signal line TGAi or TGBi per block. The shift of data between the bits of the transfer gate shift register 103 is closed in each bank. For example, the 0th bit of the bank A of the transfer gate shift register 103 is the output T of the 7th bit of the transfer shift register 103.
It receives GRAP7 as input and outputs TGRAP0 to the first bit of the transfer shift register 103.

FIG. 21 shows a specific example of a circuit diagram of one bit of the transfer shift register 103. In the figure, reference numeral 126 denotes a master latch, and 127 denotes a slave latch.

FIG. 22 shows a Y0Y1Y2 decoder circuit. In this figure, i is a decoder number and a transfer gate shift register.
Shows the 103 number. 132 NAND circuit inputs, l, m, n are ▲ ▼ or Y0, Y1 or ▲ ▼, Y2 or ▲ ▼, respectively.
Enters. During the normal random access and serial mode initialization periods, the output of the NAND circuit 132 is transmitted to TGAi and TGBi because SE = “L” and, = “H” (at this time, one of i = 0 to 7). Only one is “H” and the others are “L”). TGAi is connected to the transfer gate 27 of bank A, and TGBi is connected to the transfer gate 27 of bank B. When serial access starts, SE = “H” and SE = “L”, so that the output of the NAND circuit 132 is not transmitted to TGAi and TGBi. At the time of serial access, TGAi and TGBi are controlled by the output of the transfer gate shift register 103.

Next, the operation of the transfer gate shift register 103 during the serial mode initialization period will be described.

As shown in FIG. 11, when entering the serial mode, the signal line SL outputs a pulse signal. Then, the transfer gate
128 and 129 are opened, and the data of TGAi and TGBi are written to the master latch 126 and slave latch 127 to each bit of the transfer gate shift register 103. At this time, only one bit of i = 0 to 7 has the node p at "H" and the others at "L". This “H” is the start address. As described above, the start address of the transfer gate 27 is written.

Next, the serial access operation will be described. FIG. 23 shows a timing diagram of the data bus shift register 102, the transfer gate shift generator 111, and the transfer gate shift register 103. In this figure, the timing when the selection of the transfer gate 27 changes from the 0th bit to the 1st bit is shown. ing. OSR12, OSR14, OSRP14, OSR0 are the first
The movement is similar to that shown in FIG. Transfer gate shift register of bank A at timing t in FIG.
Looking at the 0th bit of the 12th bit and the 0th bit of the transfer gate shift register 12 of the bank A, the input TG
RAP0 = “H”, output TGA1 = “L”, TGRAP1 = “L”. 19th
In the figure, when OSRP12 = “H” and φ _A = “H”, φ _TGAA = “H”
Becomes As a result, the transfer gate 130 shown in FIG.
Is opened, TGA1 = "H", TGA0 = "L", and the transfer gate 27 of the bank A shifts from the 0th bit to the 1st bit. Thereafter, the data is transferred to the data slave latch 127 of the master latch 126 by φ _TGAB , and only TGRAP1 becomes “H”.

Similarly, the bank B operates by φ _TGBA and φ _TGBB .

The periods a and b in FIG. 23 correspond to the periods a and b shown in FIG.
You can see that it is working.

However if, at the timing p shown in FIG. 23, if the serial mode begins, the bank A is no condition to be also phi _A is also "H" to OSRP, the transfer gate register 10
No shift operation of 3 is performed. To eliminate this,
As shown in FIG. 19, 133 circuits are provided. After the signal line SL outputs a pulse as shown in FIG. 11, φ _IA , φ
_IB issues a pulse and at timing q OSR14
Since it is "H", the transfer gate shift generator 111 in FIG. 19 _issues each pulse of φ _TGAA and φ _TGAB to complete the shift of the transfer gate shift register 103 of the bank _A. Thereafter, serial access is started. As described above, by providing the circuit 133, the start address of the data bus selection address Y3, Y4, Y5, Y6 at the time of serial access can be arbitrarily set.

Next, the block relation will be described. FIG. 24 shows a circuit configuration of one block of a block selection system excluding a shift generator. In the figure, z is the block address Y7 ~
This is a Y11 decode signal line. At the time of normal random access and during the serial mode initialization period, a block selection signal is transmitted to the row decoder 3 via the transfer gate 136 and the inverter 137, and the word line 22 is selected by a logical product with the row address signal. . At the time of serial access, the transfer gate 136 is closed, and the block signal z is not transmitted. Instead, a signal is transmitted from the block word line shift register 105 to the signal line ▲ ▼,
The word line 22 is selected (when ▲ = “L”, the word line 22 is selected. The data shift is performed between blocks ▼ and ▼). On the other hand, the sense amplifier and the write driver 13 normally have z
SWAi and SWBi respectively operate to activate the sense amplifier 9 or the write driver 13 of the banks A and B in the block. At the time of serial access, SWAi and SWBi are controlled by the sense amplifier / write driver shift register 104. The data shift between each block is performed by bank A
Is SWRAPi-1 and SWRAPi, Bank B is SWRBPi-1 and SWRBPi
Is performed by the sense amplifier / write drive shift register 104 of each bank.

Next, the sense amplifier and write drive shift register
The operation of 104 will be described. The sense amplifier / write driver shift register 104 is 32 for each bank and block.
There are bits. Although these circuits have different input / output signal line names, the transfer shift register 10 shown in FIG.
Exactly the same as 3. The sense amplifier / write driver shift generator that controls the sense amplifier / write drive shift register 104 will be described with reference to FIG. 25 because the circuit is different from that of the transfer gate shift generator 111. In the figure, NAND circuits 134 and 135 are circuits that operate during a serial mode initialization period. Others operate in the normal serial mode. φ _SAA ,
φ _SAB , φ _SBA , φ _SBB respectively correspond to φ _TGAA , φ _TGAB , φ _TGBA , φ _TGBB of the transfer gate shift generator 111, and transfer gates corresponding to 130 and 127 in FIG. 21 of the sense amplifier write shift register 104. To realize the operation shown in FIG.

 Next, the operation of the row shift register 105 will be described.

As shown in FIG. 6, the row shift register 105 has a double selection period c of the word line 22. This will be described. FIG. 26 shows a specific circuit example of one bit (one block) of the block word shift register 105. During the serial mode initialization period, the signal line SL performs a pulse operation, so that the transfer gates 139 and 140 are opened. Master latch 137 and slave latch 138
The data of ▼ is written. ▲ ▼ indicates i =
Of 0 to 31, only one is "L" and the others are "H". Therefore, "L" is the start block address for serial access. Also, ▲ is “L” for only one block. Now, ▲ ▼ = “L”, ▲
▼ = “H”. FIG. 27 shows a schematic diagram at this time, and square numbers indicate block numbers. Node y in FIG. 26
Is "L" in block 0, "H" in block 1,
▼ = “L”, ▲ ▼ = “H”. Therefore, the word line 22 of the block 0 is selected. Now, WLA, WBφ _A ,
A positive pulse enters the order of WBφ _B. ▲
When ▼ = “L”, the transfer gate 141 is opened by WLA, and the node x becomes “H”. NMOS transistor 142 is O
After the N state, it changes to “L” only when the node y is “H”. When ▼ = “H”, since the node x is “L”, the NMOS transistor 142 is off, and the node y does not change.

Next, when the transfer gate 143 is opened by WBφ _A, ▲ ▼ = is "L" when, not change because the node y in WLA pulses already a "L". ▲
When ▼ = “H”, it changes to “H” only when the node y is “L”. Then the WBfai _B, the data in the master latch 137 is transferred to the slave latch 138 via a transfer gate 141, changing the ▲ ▼. To summarize the above operation in the case of FIG. 27, the node y of the block 1 of the block word line shift register 105 is W
It changes to “L” by the LA pulse, ▼ = “L”, the node y of block 0 of the block word line shift register 105 of block 0 becomes “H” by the WBφ _A pulse, and ▲
▼ changes to “H”. In other words, the period between the WLA pulse and the WBφ _A pulse becomes “L” in both of ▲ and ▼, and the word line 22 is in the double selection period, and in FIG. 6 c, WLA, WBφ _A , WBφ
_This is realized by the three-phase clock of _B.

FIG. 28 is a circuit diagram of a block word line shift generator 113 for generating pulses WLA, WBφ _A and WBφ _B, and FIG.
Figure 9 shows the timing chart. FIG. 29c shows the double selection period. If serial access starts during period R, the NAND circuits 145 and 146 in FIG. 28 set the word line double selection state during the serial mode initialization period.

The circuit diagram and operation of each shift register and shift generator have been described above.

 Next, the row address counters 107 and 108 will be described.

FIG. 30 is a specific circuit diagram of one bit of the normal row address counter 107, in which 147 is a master latch and 148 is a slave latch. Signal line φ _NACA ,
_NACB controls transfer gates 151 and 150, respectively. Signal lines Ci-1 and Ci propagate the carry signal. Xi,
▼ indicates a row address signal line, which is connected to the row decoder 3 and the normally only row decoder 110. In this embodiment, the row address has 10 bits of X0 to X9, and the normal row address counter 107 has 10 bits (▲ == ▲).
▼ = …… = ▲ ▼ = “H” is the lowest row address and X0 =
X1 = ... X11 = "H" is the highest address).

 Next, the operation will be described.

During the serial mode initialization period, the signal line SL
Gives a positive pulse, so transfer gates 149,154
Is opened, and the data of the row address signal line Xi is written to the master latch 147 and the slave latch 148.

Next, it is assumed that a serial access mode has been entered. At this time, SE = "H". The NOR circuit 155 has Ci-1 = "H" and Xi =
Only when “H” is Cu = “H”. That is, when the digit raising signal “H” comes from the previous counter to the signal line Ci−1 and the signal itself is Xi = “H”, ▲ = “L”, the digit raising signal is set to the signal line Ci = Tell it by setting it to “H”. _Assuming that positive pulses that do not overlap each _{other in} the order of the signal lines φ _NACA and φ _NACB are transmitted, the value of the slave latch 148 is transmitted to the master latch 147 through the transfer gate 131 as it is. Next, when Ci-1 is "L", the value of the master latch 147 is directly transmitted to the slave latch 148 through the transfer gates 152 and 149. That is, when the signal line Ci = “L”, the signal lines Xi and ▲ ▼ do not change. Next, the signal line Ci =
When “H”, slave latch 148 to master latch 147
Does not change from master latch 147 to slave latch 1
To 48, the inverted signal of the master latch 147 is transmitted to the slave latch 148 via the transfer gates 153, 147. Therefore, when a pulse _{arrives at the} next signal line φ _NACA , the data of the master latch 147 is inverted, and the data of the signal lines Xi, ▼ are also inverted. As described above, when a positive pulse comes to the signal line φ _NACA after ▲ ▼ becomes “H”, the signal lines Xi and ▲
▼ data changing turn over of (in FIG. 31, the initial a .t ₀ shown a timing diagram states, Ci-1 at t ₁ is the Xi at t ₂ When becomes "H""L" → " H ").

The row address counting operation is performed as described above. Note that the bit for outputting data to the lowest row address X0, ▲ ▼ of the normal row address counter 107 is C
i-1 is always "H". The look-ahead row address counter 108 is different from the normal row address counter _except that the timing of outputting a positive pulse to the signal lines φ _NACA and φ _NACB and that the signal lines Xi and ▲ ▼ are connected to the look-ahead row decoder 109 are all other. Same as 107.

Actually, in the _pre- read row address counter 109, the signal line φ _NACA is changed to φ _LACA , and the signal line φ _NACB is changed to φ _LACB .

FIG. 31 shows a count shift generator 114 for generating a positive pulse signal on the signal lines φ _NACA , φ _NACB , φ _LACA , φ _LACB.
The circuit diagram of FIG. The NAND circuits 156 and 157 are circuits that operate during the serial mode initialization period. Since the count shift generator 114 takes a long time to propagate when the carrier signal Ci is “H” in each counter, the positive pulses of the signal lines φ _NACA , φ _NACB , φ _LACA , φ _LACB are converted to the signal lines φ _A ,
It is taking longer than in the φ _B. FIG. 33 shows the movement of the signal lines related to the normal row address counter 107 of the count shift generator 114. While the data in block 0 is being accessed, the normal row address counter 107 reads the
While the data is being accessed, the signal line φ _NACA ,
Count operation is _performed at φ _NACB , φ _LACA , φ _LACB .

FIG. 34 is a circuit diagram of the row address buffer 2. When the signal line SE = “H”, the signal of the external Xi is applied to the signal lines Xi, ▲ ▼.
Does not reach. The signal lines Xi, ▼ are controlled by the row normal address counter 107.

Next, FIG. 35 shows a circuit corresponding to one word line of the pre-read row decoder 109 and the normally-only row decoder 110 shown in FIG.

Actually, there are 1024 row addresses since there are X0 to X9. In FIG. 24, x is the logical product of the decode signal of the pre-read row address counter 108 and the inverted signal of ▼ in FIG. y is the logical product of the decode signal of the normal row address counter 107 and the inverted signal of ▼. At the time of serial access, the word line 22 is selected by the right circuit because SE = “H” and ▼ = “L”. At the time of normal random access, the word line 22 is selected by the left circuit. Note has been described mainly in the read operation so far, the write operation, changes to the sense amplifier 9 and the output data buffer 10, changes to the write driver 13b and an output data buffer 10, write driver 13b and the write data buffer 13 _a is Others are the same except for the operation. Also outside ▲
When ▼ is “H”, the random access operation shown in the conventional example is possible.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the front-stage shift register to which the lower one of the address data or the address signal is input and the upper-side shift register of the address data or the address signal The shift register is hierarchized by using a subsequent-stage shift register to which the input is input, so that the area occupied by the shift register can be reduced. In addition, a counter is used to select a row address, and a shift register is used to select a column address. Thus, there is an effect that high-speed serial access can be performed.

In addition, when the memory block storing the data to be accessed is switched to the next block, the word lines existing in both blocks are activated synchronously for a certain period of time. There is an effect that it can be reduced.

In addition, when the memory block storing the data to be accessed is switched from the last to the first, the word destinations in both blocks are simultaneously activated for a certain period, so that the address change from the last block to the first block is performed. There is an effect that high-speed data reading can be performed even at the time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2A is a diagram for explaining an address selection method at the time of serial access by the semiconductor memory device according to an embodiment of the present invention. 2 (b) is a configuration diagram of a shift register in a conventional general semiconductor memory device,
FIG. 2C is a configuration diagram of a hierarchical shift register in the semiconductor memory device according to one embodiment of the present invention.
FIG. 2D is a schematic diagram of a shift register, FIG. 2E is a schematic diagram of a counter, FIG. 3 is a detailed configuration diagram of one block of a read system, and FIG. 4 is a schematic diagram of a data bus shift register. FIG. 5 (a) is an operation timing diagram of the data bus shift register and the transfer gate shift register;
FIG. 5 (b) is an operation timing diagram of the transfer gate shift register, FIG. 6 is an operation timing diagram of the transfer gate, the sense amplifier / write driver, and the block word line shift register, and FIG. 7 is a word selection of blocks 0 and 1. 8 and 9 are circuit diagrams of a serial normal controller, FIG. 10 is a configuration diagram of a delay circuit, and FIG.
11 is a timing chart of the initialization period, FIG. 12 is a timing chart of the serial normal controller, FIG. 13 is a configuration diagram of the data bus shift register, and FIG. 14 is a circuit configuration diagram of one bit of the data bus shift register. FIG. 15 is an operation timing chart of the data bus shift register, and FIG.
The figure shows the block diagram of the data bus selector.
FIG. 18 is a circuit diagram of a select block and an output buffer, FIG. 19 is a circuit diagram of a transfer gate shift generator, FIG. 20 is a diagram of a transfer gate shift register, and FIG. 21 is a diagram of the transfer gate shift register. FIG. 22 is a circuit diagram of a Y0Y1Y2 decoder, FIG. 23 is an operation timing diagram of a transfer gate shift register, FIG. 24 is a circuit diagram of a block selection system, and FIG. Fig. 25 is a circuit diagram of the transfer gate shift generator.
26 is a circuit diagram of one bit of the block word line shift register, FIG. 27 is a wiring diagram of the word line shift register of blocks 0 and 1, FIG. 28 is a circuit configuration diagram of the block word line shift generator, and FIG. Operation timing diagram of block word line shift register, FIG. 30 is a circuit configuration diagram of one bit of the counter, FIG. 31 is an operation timing diagram of the counter, FIG. 32 is a circuit configuration diagram of the count generator, FIG.
The figure shows the operation timing chart of the count generator, FIG. 34 is a circuit configuration diagram of the row address buffer, and FIG. 35 is a block diagram.
FIG. 36 is a block diagram of a conventional semiconductor memory device, FIG. 37 is a block diagram showing a memory cell peripheral portion of the conventional semiconductor memory device in detail, and FIG. FIG. 38 is a circuit configuration diagram of the memory cell of FIG. 37, and FIG. 39 is an operation timing diagram of the conventional semiconductor memory device. 1 ... line address input, 2 ... line address buffer, 3 ...
... row address decoder, 4 ... column address input, 5 ...
Column address buffer, 6 ... column address decoder, 7 ...
... memory cell array (block), 8 ... multiplexer, 9 ... sense amplifier, 10 ... output data buffer,
11 read data output, 12 write data input, 13a input data buffer, 13b write driver, 14 chip select input, 15 read / write control input, 16 read / write control Circuit, 18 ...
... Power supply, 20,21 ... Bit line, 22,23 ... Word line, 25,2
6 ... Bit line load, 27,28 ... Transfer gate, 29
... I / O line, 41 ... N-channel driver transistor, 42 ... Access transistor, 43 ... Load resistance,
44 …… P-channel transistor, 99 …… Data bus,
101: Serial normal controller, 102: Data bus shift register, 103: Transfer gate shift register, 104: Sense amplifier / write driver shift register, 105: Block word line shift register, 107: Normal row address Counter, 108 ……
Look-ahead row address counter, 109... Look-ahead row decoder, 110... Normally only row decoder, 111... Transfer gate shift generator, 112... Sense amplifier / write driver shift generator, 113. ... row address count generator, 116 ... data bus selector, 115 ... delay circuit, 117, 126, 137, 147 ... master latch, 118, 127, 138, 148 ... slave latch, 120 ... Y3Y4
Y5Y decoder, 121 selection section, 122, 124 NAND circuit, 123, 125 transfer gate, 128-131 transfer gate, 132, 134, 135 NAND circuit, 133
Logic circuit, 136… Transfer gate, 139-144 ……
Transfer gate, 145,146… NAND circuit, 149-154
…… Transfer gate, 155… NOR circuit, 156,157…
... NAND circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasumasa Nishimura 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. LSI Research Institute (72) Inventor Kenji Anami 4-1-1 Mizuhara, Itami-shi, Hyogo Address Mitsubishi Electric Corporation, within LSI Laboratories (56) References JP-A-63-282995 (JP, A) JP-A-62-6482 (JP, A)

Claims (2)

(57) [Claims] A row address selecting means for inputting row address data or a row address signal; and a column address selecting means for inputting column address data or a column address signal. A memory cell at a predetermined address is selected by the means,
In a semiconductor memory device in which stored data is continuously read and written in a certain order, the column address selecting means may be arranged in a stage before the lower one of the column address data or the column address signal is input. An n-bit shift register, and a subsequent m-bit shift register to which the higher-order one of the column address data or the column address signal is inputted. The address of the preceding n-bit shift register is the n-th bit. And in the state where the address of the subsequent-stage m-bit shift register is the j-th bit, the next column address data or column address signal is
The address of the bit shift register becomes the first bit,
The address of the above-mentioned m-bit shift register on the subsequent stage is (j +
1) A semiconductor memory device which operates so as to become a bit. 2. The semiconductor memory device according to claim 1, wherein a counter is used as said row address selecting means, and a shift register is used as said column address selecting means.