JP3232046B2 - Dynamic semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to a structure for performing multi-bit serial access mode operations such as a page mode and a static column mode at a higher speed.

[0002]

2. Description of the Related Art Semiconductor random access memories (R)
AM) includes a static RAM (SRAM) and a dynamic RAM (DRAM). SRAM and DR
A major difference from the AM is that the DRAM requires a refresh operation for periodically rewriting the memory cell data.

In an SRAM, usually, a row address and a column address are applied simultaneously, and these row and column addresses are taken into the device by a chip enable signal / CE to access a selected memory cell. ing.

On the other hand, since the 1K (2 ¹² ) DRAM of 1974, row addresses and column addresses are time-division multiplexed and applied to the same address input terminal. The address multiplex method in the DRAM will be briefly described.

FIG. 2 shows a DIP of a 1M (2 ²⁰ ) DRAM.
It is a figure showing arrangement of an external signal I / O pin terminal of a (dual-in-line) package. In FIG. 2, the pin numbers are shown in square frames. In a 1M DRAM, 10-bit row address signals A0 to A9 and 10-bit column address signals A0 to A9 are assigned pin numbers 5 to 8 respectively.
And time-division multiplexed to the pin numbers 10 to 15 and applied. The timing of taking in the row address and column address applied to these address input terminals into the device is determined by the row address strobe signal / RA applied to pin number 3.
S and a column address strobe signal / CAS applied to pin number 16. Here, in FIG. 2, “bar” is added to the signal, which indicates negative logic, and in this specification, “/” will be used hereinafter.
Indicates this "bar" symbol. When row address strobe signal / RAS falls to L level, the device is activated and the row address is taken into the device. On the other hand, when column address strobe signal / CAS falls to L level, the column address is taken into the device. Data write and read operations of the semiconductor memory device are provided by a write enable signal / WE (applied to pin number 2). When write enable signal / WE is at H level, it indicates that this semiconductor memory device is in a read operation,
On the other hand, when write enable signal / WE is at L level, it indicates that this device is in a data write operation. Input data DI is applied to pin number 1 and output data DO
Is output from pin number 17.

[0006] The data write timing includes a write enable signal / WE and a column address strobe signal / CA.
It is given by the falling timing of S to the L level which is later. Regarding the data read timing, the signal / C
Valid data is read out after a predetermined time elapses after AS and / WE are at H level and signal / CAS falls to L level.

As described above, for example, in the case of a 1M DRAM, a 20-bit address signal is required. This 20-bit address signal is divided into a 10-bit row address signal and a 10-bit column address signal, and these row and column address signals are time-division multiplexed and applied to the same address input pin terminal. For example, a 20-bit address signal can be input at a 10-bit pin terminal. Therefore, even if the number of bits of the address signal increases as the capacity of the semiconductor memory device increases, the increase in the number of pin terminals can be suppressed. Next, the conventional 1M DR
The internal configuration of the AM will be schematically described with reference to FIG.

Referring to FIG. 3, a 1M DRAM has two memory cell array blocks 1a and 1b each having memory cells arranged in a matrix of 256 rows (2 ⁸ ) rows and 2K (2 ¹¹ ) columns. including. Memory cell array block 1
a and 1b each provide a storage capacity of 512K bits, and provide a storage capacity of 1M bits as a whole.

Each time a memory cell of memory cell array block 1a, 1b is selected, externally applied row address signals A0-A9 are received, latched in response to signal / RAS, and generate internal row address signals RA0-RA9. Row address latch 3 and address input terminal 2
Column address signals A0 to A
9 and latches in response to a signal / CAS to generate internal column address signals CA0-CA9, and receives internal row address signals RA0-RA7 from row address latch 3 and outputs data from 256 rows. , And the internal column address signals CA0 to CA9 from the column address latch 4 and the uppermost internal row address signal R from the row address latch 3.
In response to A9, column decoders 6a and 6b for selecting one of the 2K columns are provided.

The internal row address signal RA8 from the row address latch 3 is used as a block selection address, and enables only one of the memory cell array blocks 1a and 1b.

External row and column address signals A0 to A0
In order to input / output data to / from the memory cell selected by A9, a sense amplifier for detecting and amplifying information of the memory cell connected to one row selected by row decoders 5a and 5b, and a column decoder 6a and 6
An I / O gate for selecting a 1-bit memory cell in response to the column decode signal from b and connecting to the I / O buffer 7 is provided. In FIG. 3, the sense amplifier and I
The / O gate is shown by one block 8a, 8b.

An external row address strobe signal // applied from input terminal 11 for defining operations of data writing / reading, row selection, and column selection of the semiconductor memory device.
RAS-related clock generator 12 receiving RAS and generating an internal control signal related to a row selection operation;
A CAS clock generator 14 for generating an internal control signal related to column selection in response to a column address strobe signal / CAS externally supplied through R / W clock generator 15 for generating a clock signal for giving data write and read operation timing in response to an internal control signal from CAS clock generator 14, and a clock signal from R / W clock generator 15 In response to write enable signal / WE externally applied,
An R / W control circuit 16 for activating one of the input unit and the output unit of the buffer 7 is provided.

Here, in FIG. 3, address signals A0 to A9 are applied to the input terminal 2;
Has a width of 10 bits. Next, the operation will be briefly described.

First, 10-bit row address signals A0 to A9 are applied from the outside via the address input terminal 2. Row address latch 3 latches a row address signal applied to address input terminal 3 in response to transition of signal / RAS to L level, and outputs internal row address signals RA0-RA0.
Generate RA9. Of the 10-bit internal row address signals RA0 to RA9, 8-bit internal row address signals RA0 to RA7 are applied to row decoders 5a and 5b. One-bit internal row address signal RA8 is used as a block selection address. Therefore, only one of memory cell array blocks 1a and 1b is enabled by row address signal RA8. Now, it is assumed that the memory cell array block 1a is selected by the internal row address signal RA8. In this case, the row decoder 5a is activated, decodes the internal row address signals RA0 to RA7, selects one of the 256 rows of the memory cell array block 1a, and raises the potential of the word line defining this row to H. Get up to level. Thereafter, the sense amplifier included in the block 8a is activated, and information of the memory cell connected to the selected word line is detected and amplified.

Next, column address signals A0 to A9 are applied to column address latch 4 via address input terminal 2. Column address latch 4 receives a given 10-bit address signal as a column address signal in response to column address strobe signal / CAS, and generates internal column address signals CA0-CA9. Column decoder 6a receives the internal column address signal CA0 of 10 bits.
CA9 and 1-bit most significant row address signal RA9 are decoded, and one of the 2K columns is selected. The memory cells connected to the selected column are connected to the I / O buffer 7 via the I / O gate included in the block 8a. Next, data is written to or read from the selected memory cell according to the state of write enable signal / WE.

Here, externally applied address signals A0 to A9 are simultaneously applied to the row address latch 3 and the column address latch 4 via the input terminal 2. Each of the row address latch 3 and the column address latch 4 takes in a signal given as a trigger signal at the falling edge of the control signal to L level, and separates a row address and a column address.

A data field formed by memory cells connected to one row selected by one row address (one set of row address signals A0 to A9) as described above is called a "page". While the signal / RAS is kept at L level without changing the row address, the signal / CA
The operation of toggling S, taking in a column address from the outside for each toggle, and selecting data of this page is called "page mode". In the page mode operation, it is not necessary to apply both the row address and the column address as in the normal 1-bit operation mode. After the row address is applied, the column address strobe signal is changed only by changing the column address. Since the memory cell can be accessed by toggling / CAS, the memory cell can be accessed at higher speed than in the normal mode. The page mode, which is a high-speed serial access mode, and the address multiplexing method for reducing the number of pin terminals are still employed as standard techniques in DRAMs. Further, various improvements have been proposed to further speed up the row selection by row address and the column selection by column address in order to further speed up such a high-speed serial access mode.

As another high-speed serial access mode, a 4-bit memory cell is selected at a time.
A nibble mode for accessing these 4-bit memory cells by sequentially toggling the signal / CAS, for example, a 2K-stage shift register is provided, and data is exchanged between the shift register and a selected page.
There is a method adopted in a video RAM or the like that inputs and outputs data to and from the outside via a shift register.

On the other hand, even if the integration of the semiconductor memory device is increased to increase the capacity, the sense capability of the sense amplifier for detecting and amplifying the signal potential of the bit line (column line) is limited. There is. When the ratio between the bit line capacity and the memory cell capacity exceeds a certain value, the sense amplifier cannot accurately detect data on the bit line.
The sense margin of this sense amplifier will be described with reference to FIG.

FIG. 4 is a diagram schematically showing a configuration of one column of a memory cell array block. In FIG. 4, the bit line forms a folded bit line, and bit line BL and complementary bit line / BL are arranged in pairs and parallel to each other. 256 word lines WL1 to WL256 and two dummy word lines DWL so as to cross bit lines BL and / BL.
1 and DWL2 are provided.

A memory cell MC is provided at one of the intersections of one word line and a pair of bit lines. That is, bit line BL has memory cell MC at the intersection with word lines WL1, WL3 (not shown),..., WL255, and complementary bit line / BL is word line WL2,.
There is a memory cell MC at the intersection with 256. A dummy cell DM is provided at the intersection of the dummy word line DWL1 and the bit line BL.
Is provided. Dummy cell DM is provided at the intersection of dummy word line DWL2 and complementary bit line / BL. Dummy cell DM stores information of Vcc / 2 (H level information stored in the memory cell is set to Vcc level), and gives a reference potential at the time of memory cell data sensing operation.

The memory cell MC includes a memory capacitor C for storing information in the form of electric charges, and a transfer gate transistor T which is turned on in response to a word line potential and connects the memory capacitor C to a corresponding bit line. Is done.

An equalizing / precharging circuit PE is provided for precharging and equalizing the potentials on bit lines BL and / BL to a predetermined potential VB during standby of the semiconductor memory device.

In order to detect and amplify the signal potential difference on bit lines BL and / BL, sense amplifier activating signal φ0
, And a sense amplifier SA that differentially amplifies signal potentials on bit lines BL and / BL is provided.

In order to access a memory cell, bit lines BL and / BL are connected to data input / output bus I / O in response to a column decode signal from column decoder 6, respectively.
I / O gate transistor TR connected to O, / I / O
1 and TR1 'are provided. Next, the operation of reading memory cell data will be briefly described with reference to FIG.

Now, suppose that word line WL1 is selected.
When the word line WL1 is selected, the transfer gate transistor T of the memory cell MC is turned on, and a signal potential corresponding to information stored in the memory cell MC appears on the bit line BL. On the other hand, at this time, the dummy word line DWL2 is selected, and the information of the dummy cell DM is transmitted onto the complementary bit line / BL. After a signal potential appears on bit lines BL and / BL, sense amplifier S
A is activated in response to sense amplifier activation signal φ0, and further amplifies this signal potential difference. When the signal potentials on bit lines BL and / BL are determined by sense amplifier SA, I / O gate transistors TR1 and TR1 are supplied by a column decode signal from column decoder 6.
1 'is turned on, and bit lines BL and / BL are connected to data input / output bus lines I / O and / I / O.
Next, data writing or reading is performed.

Now, consider the signal potential difference between bit lines BL and / BL for detection by sense amplifier SA. It is assumed that memory cell MC stores a charge corresponding to H-level signal potential VH in its memory capacitor, while dummy cell DM stores a reference potential VR (normally VH / 2). The capacitance of each of the bit lines BL and / BL is CB, and the capacitance of the memory capacitor is C
Assuming that S, the potential difference between the bit lines BL and / BL when the word line is selected is given by the following equation.

[0028]

(Equation 1)

As can be seen from the above equation, the sense amplifier S
In order to make A operate as quickly as possible and to surely perform its sensing operation, CB / CS should be made as small as possible. However, when a large number of memory cells are connected to the bit line, the bit line capacitance CB increases due to factors such as an increase in parasitic capacitance and bit line length associated with the memory cell and an increase in wiring capacitance.
On the other hand, as the size is reduced, the capacitance CS of the memory capacitor C decreases. Therefore, the capacitance ratio CB / CS becomes large. In a normal DRAM, the ratio CB / CS is a value of about 10 to 15. If the value of the capacitance ratio CB / CS is made larger than this value, the signal potential difference appearing between the bit lines becomes small, and the sensing operation cannot be performed reliably. Therefore, the value cannot be made larger than this value. Usually, in a large capacity DRAM,
Since the capacitance value of the memory capacitor is approximately 40 fF to 50 fF, the bit line capacitance CB cannot be increased to 400 to 750 fF or more. 4M DRAM, and 1
In a 6M DRAM, the bit line capacitance CB is 35
It is set to about 0 to 400 fF.

On the other hand, when 128 memory cells are connected to the bit line, the bit line capacitance CB is about 500 fF. Therefore, the maximum number of memory cells connected to one bit line is about 128, and the maximum number of memory cells connected to one column, that is, the bit line BL and the complementary bit line / BL is 256 at the maximum.

Due to the above-mentioned limitations, for example, in the case of a 16-Mbit DRAM, the number of word lines is 256 and the number of sense amplifiers is 64K (64K columns). When the address signal is applied by the above-described conventional address multiplex system, the number of bits of the row and column addresses is 12 bits. The data field that can be accessed with a 12-bit column address is
2 ¹² or 4K bits, the remaining 60K bits cannot be accessed. That is, one page is 4K
Bit.

On the other hand, to access 256 word lines, an 8-bit address signal can be used.
Of the bit row address signals, an 8-bit row address signal is used for word line designation, and the remaining four bits must designate a data field.

For this reason, in a 16 Mbit DRAM, a 16 Mbit memory array is used as shown in FIG.
It is divided into 16 1M bit blocks (256 rows × 4K columns), and the remaining 4 bits of the row address signal are used for dividing these 1 bits.
In this configuration, one of the six blocks is designated. That is, as shown in FIG. 5, one of the 256 word lines in each block is selected by the 8-bit internal row address signals RA0 to RA7, and the remaining 4-bit row address signals RA8 to RA11 are used. Only one of these 16 blocks is selected and enabled. At this time, the remaining 15 blocks are disabled. This selected 1M
A data field of a selected page is accessed by a 12-bit column address for a memory cell array block of bits.

[0034]

As described above, in the case of a conventional 16 Mbit DRAM, the memory array is divided into 16 blocks, and these 16 blocks are supplied by one row address supply. Only one of the memory cell blocks is selected and made accessible. Therefore, when accessing all 16 memory cell blocks, it is necessary to supply the row address 16 times, which causes a disadvantage that the overall access time becomes longer. That is, for example, when a 16 Mbit DRAM is used as a video memory for storing image data, 16 Mbits may be required in one field depending on the bit width of the image data and the number of pixels on one horizontal scanning line. There is also. In such a video memory, writing and reading of image data must be performed at a high speed of, for example, 4f _C or 8f _C (f _C : color subcarrier frequency). However, the conventional 16 Mbit DRA
In M, in order to access all the blocks, it is necessary to supply the row address 16 times even if the page mode which is the high-speed access mode is used.
Data cannot be written and read at high speed. That is, in a video memory, one horizontal scanning line is made to correspond to one row of a memory cell array. However, data writing and reading during one horizontal scanning period cannot be performed at high speed. Occurs.

The above-mentioned conventional 16 Mbit DRAM
In, the data size of one page is 4K bits, and depending on the use of the DRAM, the data size of this page may cause a problem.

The DRAM requires a periodic refresh operation. In order to refresh all the memory cells of the 16-Mbit DRAM, 2 ¹² (12-bit row address) refresh cycles are required, which increases the time required for refreshing the memory cells. In this refresh operation, one row of memory cells is refreshed in one refresh cycle in accordance with a refresh address. However, in order to refresh one row of memory cells in all blocks by the same refresh address, 16 refreshes are performed. Refresh operation is required. During this refresh operation, external access is prohibited, so that an external device such as a CPU (Central Processing Unit) is in a standby state during that time, causing a problem that the efficiency of memory access is reduced.

When the page size is increased,
The number of memory cells in one row increases. In the memory cell column,
Each of them is connected to a sense amplifier, and data of a memory cell connected to the selected row is detected, amplified, and latched by the corresponding sense amplifier. If all the sense amplifiers operate at the same time during the detection and amplification of these one row of memory cell data, the current consumption of the sense amplifiers increases,
In addition, power supply noise or the like may occur due to a power supply current during a sense operation of the sense amplifier, and a malfunction may occur.

An object of the present invention is to provide a DRAM which eliminates the above-mentioned drawbacks of the conventional DRAM and can further reduce access time and improve access efficiency and current consumption. is there.

Another object of the present invention is to provide a DRAM having an extended page data size, which can be accessed at higher speed without increasing current consumption.

[0040]

A dynamic semiconductor memory device according to the present invention includes a plurality of memory arrays each divided into a plurality of blocks. Each block is arranged corresponding to a plurality of memory cells arranged in a matrix and each row, a plurality of word lines to which the memory cells of the corresponding row are connected, and arranged corresponding to each column, And a plurality of bit lines connected to memory cells in a corresponding column.

The dynamic semiconductor memory device according to the present invention is given further in response to a row address supplied from the outside, means for selecting one word line from each block over multiple memory arrays, external Means for selecting at least one column from the entire plurality of memory arrays in response to an externally applied column address. The number of bits forming the row address is smaller than the number of bits forming the column address. Also, the row address is composed of address bits all are taken in response to a row selection instruction signal given by the first timing, also the column address is given by the slower second timing than the first timing It is composed of all the address bits taken in in synchronization with the column selection instruction signal. Also, word lead wire selection means includes means for driving the corresponding word line to a selected state according to block selection signals, respectively are sequentially activated in each array block over multiple memory arrays. After activation of a block selection signal for a corresponding memory array block, a bit line is sequentially selected based on a column address provided in response to each column selection instruction signal, and data is written or read. Further, a dynamic semiconductor memory device according to a second aspect of the present invention includes:
A plurality of memory arrays each having a plurality of memory array blocks are provided. Each of the plurality of memory array blocks includes a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of words arranged corresponding to each of the rows and connected to the memory cells of the corresponding row. With a line. Dynamic semiconductor device according to a second aspect of the present invention
The body memory further includes an externally provided row address.
A plurality of memory arrays in response to a plurality of memory arrays
From each of the blocks, the row address corresponds to the row specified by
Row selecting means for selecting a word line arranged by
A plurality of memory arrays each coupled to the row selection means;
Word lines selected in a number of memory array blocks
Each memory array over the plurality of memory arrays.
Block selection signal activated sequentially for ray blocks
Sequentially activating means for sequentially activating in response to
Repeat after activation of memory array block of memory array
Each of the column selection instruction signals to be applied in return and each of the column selection instructions
Responds to externally supplied column address in response to signal
At least one column from the entire memory array.
A selection address means for sequentially selecting memory cells is provided. order
By the next activation means, a plurality of menus are stored in each memory array.
The selected word lines of the memory array block are activated sequentially.
Driven to the selected state. Column address given externally
Is the row address given from the outside
And the row address
Responds to the row selection instruction signal given at the first timing
Address bits that are internally
And the column address is later than the first timing.
In response to the column selection instruction signal given at the timing of 2.
It consists of all address bits taken in at the same time.
It is. Also, preferably, the memory cell on the selected row and column by matrix selection unit, writing or reading data according to a column selection instruction signal given by the second timing
It further comprises means for extracting.

The number of bits forming a row address is made smaller than the number of bits forming a column address. That is, for example, in the case of a 16 Mbit DRAM, the address is 2
Although four bits are required, of these 24-bit address signals, eight bits are used as a row address and the remaining 16 bits are used.
Use bits as column addresses. Thus, one of 256 rows can be selected by an 8-bit row address,
With a 16-bit column address, a 64-Kbit data field can be accessed. This allows
The data size of one page can be expanded to 64K bits, and data can be written to and read from memory cells at higher speed.

Also, 64K columns of memory cells are connected to one row, and sense amplifiers are connected to these 64K columns. If the 64K-bit sense amplifiers are operated simultaneously, the peak current flowing during the sense operation increases, causing fluctuations in the substrate potential and the like, and increases the current consumption. However, in each block across the plurality of memory arrays, by driving the word line to the selected state in accordance with the block selection signal sequentially activated,
In each block, the sense amplifier is activated in accordance with the selected word line, so that the sense amplifier operation is sequentially performed over the entire block. Therefore, the peak current during the sense operation can be dispersed and reduced.

A row address is constituted by all the address bits taken in according to a row selection instruction signal given at a first timing, and a column selection instruction given at a second timing later than the first timing. By configuring the column address with all the address bits taken in in response to the signal, when the row address and the column address are applied through the same address input terminal,
An operation mode instruction signal or the like can be applied via the empty terminal when a row address is applied, and a multifunctional semiconductor memory device can be realized. Further, both the row address and the column address are taken in synchronizing with the selection instruction signal, so that the page size during the page mode operation can be greatly expanded easily. Further, at the time of normal data access, data is written or read to or from the memory cell selected by the row and column selecting means in accordance with the column selection instruction signal provided at the second timing, whereby the memory cell selected by the row selecting means is selected. Column selection is sequentially performed on the selected row by the column selection means, and data can be written or read in accordance with the page mode, thereby realizing high-speed access.

Referring to FIG. 1, memory array M is divided into two sub-arrays Ma and Mb. Each of the sub-arrays Ma and Mb has eight array blocks M
1 to M8 and M9 to M16. That is,
A 16 Mbit memory cell is divided into 16 blocks as a whole. Each of the array blocks M1 to M16 has a storage capacity of 1 Mbit. That is, each of the memory cell array blocks M1 to M16 has memory cells arranged in 256 rows and 4K (2 ¹² ) columns.

In each of the memory cell array blocks M1 to M16, if each column has a folded bit line configuration, a bit line and a complementary bit line are arranged in pairs corresponding to one column. Each of sub arrays Ma and Mb is provided with row decoders 50a and 50b, respectively, for selecting one row from memory cell array blocks M1 to M16. The row decoder 50a is connected to the row address latch 30
, One word line is selected from each of memory cell array blocks M1-M8 in response to 8-bit internal row address signals RA0-RA7. The row decoder 50b
In response to an 8-bit internal row address signal from row address latch 30, memory cell array blocks M9-M1
6, one row, that is, one word line is selected. As will be clearly shown later, in the sub-array Ma, word lines are commonly arranged in the memory cell array blocks M1 to M8. In sub-array Mb, similarly, one word line is arranged extending over memory cell array blocks M9 to M16. Therefore, each of row decoders 50a and 50b has 256 outputs, and one word line is selected in each of memory cell array blocks M1 to M16 by the outputs of row decoders 50a and 50b.

Each of the memory cell array blocks M1 to M16 has a sense amplifier for detecting and amplifying information of a selected memory cell, a latch means for latching data detected and amplified by these sense amplifiers, and a column address. Peripheral circuit block B including a column decoder for selecting a corresponding column in response to an internal column address signal from a latch, and an I / O gate for connecting the selected column to a data input / output bus in accordance with the output of the column decoder
1 to B16 are provided. These blocks B1 to B1
An example of the specific configuration of No. 6 will be described later.

Each of the memory cell array blocks M1 to M16 is provided with an error detection and correction (ECC) circuit block E1 to E16 for detecting and correcting an error in memory cell data during operation.

Further, in order to reduce the peak current at the time of the sensing operation, the potential of the selected word line is delayed for a predetermined time between the input / output blocks of the memory cell array block and transmitted to the subsequent memory cell array block. Repeaters R1 to R14 are provided.

Row address latch for receiving a row address signal A0-A7 applied through address input terminal 20 and generating an 8-bit internal row address signal RA0-RA7 for selecting a row of memory sub-arrays Ma and Mb. 30 are provided. The operation timing of the row address latch 30 is defined by an external row address strobe signal / RAS applied through the input terminal 11.

In order to select a column from the entire memory subarrays Ma and Mb, a 16-bit internal column address signal is received in response to a signal / CAS in response to column address signals A0 to A15 provided through address input terminal 20. C
A column address latch 40 for generating A0 to CA15 is provided. Column address strobe signal / CAS
Is provided through an input terminal 3. Of the 16-bit column address signal from column address latch 40, 1
The 4-bit internal column address is applied to the column decoders included in blocks B1 to B16, and the remaining 2-bit column address signals CA0 and CA1 are applied to selector 62 defining input / output data bit width.

The address input terminal 20 has 16 input pins, and receives a column address and an 8-bit row address via these 16 input pins.
Control signals for defining the internal operation of the DRAM are applied to the remaining 8-bit address input pins which are not used when the row address is applied. These control signals are applied to the control signal latch 70 and latched. Control signal latch 7
0 latches a signal applied in response to a row address strobe signal / RAS from the input terminal 11 and applies a corresponding operation mode designating signal to the mode control circuit 60. In the above-described configuration, the operation mode designating signal and the row address signal are applied to the address input terminal 20 at the same time, and then the column address signals A0 to A15 are applied to the address input terminal 20 in a time division manner.

In order to perform a refresh operation of the DRAM, a refresh address activated in response to a refresh instruction signal from the mode control circuit 60 is generated and applied to the row address latch 30, and the error detection / correction blocks E1 to E1 are generated. Start signal H to each of E16
A refresh counter 61 for applying / V is provided. Each of the ECC blocks E1 to E16 performs an error detection / correction operation in response to a control signal H / V from the refresh counter 61.

The mode control circuit 60 generates a corresponding internal operation designating signal in response to the operation mode designating signal from the control signal latch 70, and
/ RAS and / C applied via
The presence or absence of a refresh operation instruction is detected in response to AS.

Further, in the above configuration, when the operation mode designating signal applied via the address input terminal 20 is a signal designating the data input / output width, the mode control circuit 60 specifies the input / output data bit width. Is applied to the selector 62 and the I / O buffer 63. The configuration shown in FIG. 1 shows a configuration in which the bit width of the input / output data is selectively switched between 1 bit and 4 bits by a control signal from mode control circuit 60. In response to the 2-bit internal column address signal from column address latch 40, selector 62 selects one bit of the 4-bit data read simultaneously when the input / output data bit width is 1 bit. Apply to the I / O buffer 63. Similarly, when the input / output data bit width is 4 bits, the selector 62
The 4-bit data read simultaneously is transmitted to I / O buffer 63 as it is. In the configuration shown in FIG. 1, memory cell array blocks M1 to M16 are further divided into four sub-blocks, and a 1-bit memory cell is selected from each sub-block in response to a 14-bit internal column address signal. Is shown as an example.

Further, in order to define the internal operation timing of this DRAM and the data input / output (write / read) operation, it is necessary to select a row in response to a row address strobe signal / RAS applied via input terminal 11. RAS system clock generator 12 for generating an internal control signal, and column selection system in response to column address strobe signal / CAS applied through input terminal 13 and an internal control signal from RAS system clock generator 12. Clock generator 14 for generating an internal control signal required for
R which generates a signal for giving data input / output operation timing in response to an internal control signal from system clock generator 14
/ W clock generator 15 and R / W clock generator 15
R / W controller 16 for setting the data input / output path of I / O buffer 63 to write or read data in response to write enable signal / WE is provided.

FIG. 6 shows the memory sub-array Ma shown in FIG.
FIG. 5 is a diagram schematically showing a configuration of a main part of Mb and Mb, and showing a mode of activating a word line in each of memory cell array blocks M1 to M16. Repeater R1
Each of R14 is activated in response to drive signal φi (i = 1 to 15), and the memory cell array block Mi of the preceding stage is activated.
Is transmitted to the selected word line in the subsequent memory cell array block Mi + 1. Drive signal φi is sequentially activated over each of memory cell array blocks M1 to M16 of the memory sub-array.

Row decoders 50a and 50b are activated in response to activation signals φ0 and φ8, respectively.
Given 8-bit internal row address signals RA0-RA
7 is decoded and the corresponding word line is selected. These drive signals φ0 to φ15 are generated by delaying the externally applied row address strobe signal / RAS by a predetermined time. Therefore, in each of memory cell array blocks M1 to M16, the timing at which the selected word line potential rises is all different, and the selected word line potential is changed from memory cell array block M1 to block M1.
16 are transmitted in sequence. Drive signals φ0 to φ15
Are the memory cell array blocks M1 to M16.
This is because they are sequentially activated after being delayed for a predetermined time.

The sense amplifier included in each of blocks B1 to B16 has a sense amplifier activation signal φs0 to φs1.
Activated in response to 5. Sense amplifier activation signal φ
s0 to φs15 are activated after the potential of the word line of the corresponding block rises. That is, each of sense amplifier activation signals φs0 to φs15 is generated by delaying each of drive signals φ0 to φ15 by a predetermined time.
Therefore, the activation timings of the sense amplifiers in the memory cell array blocks M1 to M16 are different from each other. Thus, when one word line is selected, 6
Since the activation timing of the sense amplifier for detecting and amplifying the data of the 4K-bit memory cell differs for each memory cell array block, the peak current flowing when the sense amplifier is activated can be dispersed, and the substrate potential can be reduced. Fluctuations and the like can be reduced.

After the potential of the selected word line in each of memory cell array blocks M1 to M16 rises according to the outputs of row decoders 50a and 50b, blocks B1 to B10 follow internal column address signals CA0 to CA10.
A 1-bit memory cell in a 64-Kbit data field is I / O by a column decoder included in B16.
It is connected to the O bus (when the input / output data has a 1-bit width).

FIG. 7 shows an example of a specific configuration of the repeater. As described above, each of the memory cell array blocks M1 to M1
M16 has the same number of rows. Repeater Rn (n =
1) to 14) include a NAND gate 90 provided between each word line of the preceding memory cell array block and each of the subsequent memory cell array blocks, and an inverter 91 receiving a NAND gate output. NAND gate 90 receives the word line potential of the corresponding preceding memory cell array block at one input and receives drive signal φn at the other input. Inverter 91 receives an output of NAND gate 90 and transmits the output to a corresponding word line in a memory cell array block at a subsequent stage. That is, the word line W
For L1, a NAND gate 90-1 and an inverter 91-1 are provided. For the word line WL2,
A NAND gate 90-2 and an inverter 91-2 are provided. For word line WL3, NAND gate 90-3 and inverter 91-3 are provided. Bit lines defining columns in memory cell array blocks M1 to M16 (a folded bit line configuration is shown in the figure, and one column is defined by bit lines BL and / BL) are arranged on corresponding columns. Is provided with a sense amplifier SA for detecting and amplifying the signal potential of the signal. Therefore, since 64K columns are connected to one row of word lines, 64K sense amplifiers SA are provided in the configuration of the 16-Mbit DRAM. Each sense amplifier SA is activated in response to a sense amplifier activation signal φsl generated at a different timing for each block. In the above configuration, the memory cell array block M
n, the selected word line (word line WL1 in FIG. 7)
When the sense amplifier SA is activated in response to the sense amplifier activation signal φsl, the data of the memory cell connected to the selected word line becomes active on the bit line. Determine. Next, when the drive signal φn + 1 rises to the H level, only the signal potential of the selected word line is at the H level.
1, only the output of NAND gate 90-1 is L
Level. Therefore, only the signal potential on the word line in memory cell array block Mn + 1 corresponding to this selected word line WL1 rises to H level. This operation is repeated in memory cell array blocks M2 to M16.

In this configuration, the activation of sense amplifier SA is performed after the word line potential in each memory cell array block is determined, and the activation of sense amplifier SA in memory cell array block Mn and memory cell array block Mn + 1 is performed. The timing is different. As a result, the peak current flowing when the sense amplifier SA is activated can be dispersed as described above, and a malfunction due to a reduction in current consumption and a fluctuation in the substrate current can be prevented.

FIG. 8 is a signal waveform diagram representing an operation timing at the time of access operation of the 16-Mbit DRAM according to the embodiment of the present invention shown in FIG. Referring to FIG. 8, the operation of the 16-Mbit DRAM according to the embodiment of the present invention will be briefly described below.

When row address strobe signal / RAS externally applied via input terminal 11 falls to L level, the semiconductor memory device is activated, and in response, row address latch 30 causes address input to be performed. Terminal 2
Latch the 8-bit row address given to 0,
Bit internal row address signals RA0-RA7 are generated and applied to row decoders 50a and 50b. Row decoder 50a is activated in response to drive signal φ0 from RAS clock generator 12, decodes applied internal row address signals RA0-RA7, and raises the potential of the selected word line in memory cell array block M1 to the H level. Start up. After the potential of the selected word line in memory cell array block M1 rises and the signal potential (read potential) in each column is determined, sense amplifier SA in memory cell array block M1 receives sense amplifier activation signal φ.
Activated in response to s0, the signal potential on each column is detected and amplified. Subsequently, the potential of the selected word line in the memory cell array block M2 rises by the function of the repeater R1, and the memory cell data connected to the selected word line is read out on each column and the signal of each column is read in the same manner as described above. The potential is determined. This operation is sequentially repeated for memory cell array blocks M3 to M16, and word lines are sequentially driven to the selected state in memory cell array blocks M3 to M16. Memory cell array blocks M1 to M
After the sequential activation operation and the sensing operation of the sense amplifier at 16 are completed, column address strobe signal / CAS applied to input terminal 13 falls to L level.
In response, column address latch 40 takes in the 16-bit address signal applied to address input terminal 20, and outputs 16-bit internal column address signals CA0-C.
A15 is applied to a column decoder included in blocks B1 to B16.

The column decoder decodes the applied 16-bit internal column address signal, selects one bit out of the 64K bits connected to the selected word line, and connects it to the I / O bus (however, In this case, the input / output data is one bit).

Next, after the access to the memory cell is completed, signal / RAS is held at L level and signal / RAS is maintained.
After CAS is once raised to H level, it is again lowered to L level. By the toggle of signal / CAS, the 16-bit address signal applied to address input terminal 20 is taken into column address latch 40 again, and an internal column address signal is generated and applied to the column decoder.
In response, one bit of the 64K-bit data field is selected again and connected to the I / O bus.

The data size of one page is 64 K bits, and all 64 K bits can be accessed at high speed simply by simply toggling the signal / CAS and externally applying a column address in response thereto. Therefore, in this access operation, instead of using both signal / RAS and signal / CAS, signal / CA is simply used.
Since the memory cell of 64K bits can be accessed by S and the column address, the same operation as that of a normal SRAM of 64K bits can be performed.
A bit DRAM can be used as a 64K bit pseudo SRAM.

FIG. 9 shows an example of a circuit configuration for generating a sense amplifier activation signal and a drive signal for driving a repeater. Referring to FIG. 9, a circuit for generating a signal for driving a repeater and a sense amplifier includes a RAS buffer 100 for receiving an externally applied row address strobe signal / RAS and generating an internal control signal RAS.
And delay circuits D1 to D8 each of which delays the internal control signal RAS from the RAS buffer 100 for a predetermined time and outputs the delayed signal. Each of the delay circuits D1 to D8
Cascaded.

As is apparent from the configuration shown in FIG. 9, sense amplifier activating signal φsi changes to H level after a predetermined time has elapsed after signal φi for driving the repeater corresponding to the block has risen to H level. Get up.

As shown in the operation waveform diagram of FIG. 10, by using the structure shown in FIG. 9, after the repeater is driven in each memory cell array block, the potential of the selected word line in that block rises to the H level. Activate the sense amplifier included in the block, and the sense amplifier activation and word line selection operation can be sequentially transmitted to the subsequent memory cell array block in each memory cell array block.

FIGS. 11 and 12 show more specifically operation waveform diagrams in the normal mode and the page mode of the 16-Mbit DRAM according to the embodiment of the present invention.

As shown in the operation waveform diagram at the time of the normal mode data read operation of FIG. 11, each of delay circuits D1 to D8 shown in FIG. 9 has a delay time of about 50 ns. Row address strobe signal / RAS
Falls to the L level, an external row address is taken into the device to generate an internal row address signal, and the activation of the word line and the activation of the sense amplifier in each of memory cell array blocks M1 to M16 are completed. until,
It takes about 850 ns to 900 ns. Thereafter, column address strobe signal / CAS falls to L level, a 16-bit column address applied to address input terminal 20 is fetched, and internal column address signal CA
0 to CA15 are generated, whereby 1-bit memory cell data of 64K bits connected to the selected word line is output. The data write / read operation is instructed by raising write enable signal / WE to H level, whereby data read is performed under the control of R / W control circuit 16 shown in FIG.

In the page mode of the high-speed serial access mode, as shown in detail in the operation waveform diagram at the time of reading in FIG. 12, until the first 1-bit data is read, the normal mode shown in FIG. The second access is performed by toggling the column address strobe signal / CAS to take in an external column address. Therefore, unlike the normal mode, it is not necessary to take in the row address and the column address, respectively, and the data can be read at high speed.

In the above configuration, the memory cell array block M1 to the memory cell array block M1
The activation of the word line and the activation of the sense amplifier are sequentially performed toward 6. That is, the memory array M
Are sequentially activated over the entire subarrays Ma and Mb. However, instead of this configuration, the memory sub-arrays Ma and Mb may be simultaneously accessed in parallel. That is, one memory cell array block in the memory sub-array Ma and one memory cell array block in the memory sub-array Mb may be simultaneously accessed. In this case, as compared with a configuration in which the memory cell array blocks are sequentially activated one by one, one memory cell array block M
The time required to activate 1 to M16 is reduced to about half, and the access can be performed at higher speed.

Further, instead of the above-described configuration, the order of sequentially activating the memory cell array blocks is as follows: from memory cell array block M16 to memory cell array block M1.
Activation may be performed in the reverse order as performed. That is, in each memory cell array block,
The same effect as in the above-described embodiment can be obtained if the activation timings of the sense amplifier and the selected word line are different and the configuration is such that the peak current flowing when the sense amplifier is activated is reduced.

Further, according to the present invention as described above,
In an M-bit DRAM, the number of word lines is 256
This is a book, and all word lines can be selected with an 8-bit row address. Therefore, in order to refresh all the 16 Mbit memory cells, the conventional DR
The refresh cycle required 2 ¹² (256 × 16) times in AM can be reduced to 256 times, and the time required for refresh can be reduced.
It is possible to improve memory access efficiency and ease of timing design of a system using the DRAM.

Further, a 16 Mbit DR according to the present invention
In AM, the data size of one page is 64K bits, and so-called hidden refresh in which a refresh operation is internally performed in parallel with external memory access can be performed.
It can be used as a K-bit PSRAM.

Next, a configuration for easily performing the hidden refresh will be described with reference to FIG.

FIG. 13 shows a main portion of a structure for easily performing a refresh operation of the DRAM according to the present invention. In FIG. 13, two pairs of bit lines,
The configuration of a column, two rows of word lines and their associated sense amplifiers and main functional units is shown. Referring to FIG.
A latch circuit L configured using, for example, an SRAM cell for latching data on each column, that is, bit lines BL and / BL, is provided. Transfer gate transistor Q which is turned on or off in response to transfer signal φTn is provided between latch circuit L and bit lines BL and / BL. Latch circuit L and data input / output bus I /
O and / I / O, I / O gate TR for selectively coupling latch circuit L to data input / output buses I / O and / I / O in response to an output from column decoder 6; TR 'is provided.

FIG. 14 is a signal waveform diagram representing an operation timing of activation of the transfer gate and the sense amplifier shown in FIG. As shown in FIG. 14, the transfer control signal φTn is
Sense amplifier activation signal φsl in the corresponding memory cell array block rises to H level, and rises to H level after the sense amplifier is activated. As a result, the signal detected and amplified by the sense amplifier is transferred to the latch circuit L via the transfer gate Q in the ON state. Transfer control signal φTn falls to L level after the last memory cell array block, for example, sense amplifier activating signal φs15 in M16 rises to H level, and the transfer operation in that memory cell array block is completed, and falls to L level. The sense amplifier is electrically disconnected.

FIG. 15 shows an example of a circuit configuration for generating the signals shown in FIG. Referring to FIG. 15, a transfer control signal generating circuit receives a sense amplifier activating signal φsl, delays the signal by a predetermined time, and outputs the delayed signal.
A delay circuit 151 which receives a sense amplifier activation signal φs15 for activating a sense amplifier of a memory cell array block which is activated lastly, delays the signal by a predetermined time, and outputs it
An SR flip-flop 152 receiving the output of delay circuit 150 at its set input S and receiving the output of delay circuit 151 at its reset input R. Transfer control signal φTn
Is provided from the output Q of the SR flip-flop 152. Next, the data transfer operation will be described in detail with reference to FIGS.

When row address strobe signal / RAS is L
After a predetermined time has elapsed, the sense amplifier activation signal φsn for activating the sense amplifier in the memory cell array block rises to the H level. In response, the sense amplifier SA is activated to detect the signal potential on the bit line and differentially amplify it. When the signal potential on the bit line pair is detected and amplified by the sense amplifier SA and the signal potential is determined, the transfer control signal φTn from the flip-flop 152 rises to the H level. As a result, the transfer gate transistor Q is turned on, and the data latched by the sense amplifier SA is transferred to the latch circuit L. The latch circuit L
This transferred data is latched. Transfer control signal φT
n falls to the L level when the sensing operation in the last memory cell array block M15 is completed, that is, when a predetermined time elapses after the sense amplifier activation signal φs15 in the memory cell array block M15 rises to the H level, and the sense amplifier SA Disconnect from the latch circuit L. As a result, 64K bits of data corresponding to one page data field are latched by the 64K latch circuits L.

The selection of the latch circuit L is performed according to a column decode signal from the column decoder 6 so that the latch circuit L connected to the corresponding column is turned on by the transistors TR and TR '.
This is performed by connecting to a data input / output bus I / O via an (I / O gate). Therefore, after data is transferred from sense amplifier SA to latch circuit L, the column selecting operation for each memory cell array block can be performed independently of the row selecting operation. Therefore, after data is latched in latch circuit L, refreshing can be performed on each of memory cell array blocks M1 to M16. In particular, if an auto-refresh function or a self-refresh function is provided, a memory cell access by a column address can be performed in parallel with the refresh operation, so that a 64-Kbit pseudo-static RAM (PSRAM) can be realized. .

That is, as shown in FIG.
AS falls to the L level, and the memory array block M1
After latching one page of data in M16 to M16 in the latch circuit L, the signal / RAS is raised to the H level again,
The signal / RAS is held at the H level to generate the signal / C.
When AS falls to L level, this 16 Mbit DRA
In M, while performing CAS-before-RAS refresh, it is possible to simultaneously access latch circuit L and select one column in accordance with an external column address to read memory cell data.

In the CAS-before-RAS refresh cycle, the time required for activating all the word lines in one row is about 750 ns to 800 ns, and during that period, the memory cells in one row are refreshed.

In place of the CAS-before-RAS configuration, if the self-refresh function automatically generates a refresh address during a refresh instruction in response to an external refresh instruction signal, signal / RAS needs to be toggled. And refresh can be performed more easily. This self-refresh instruction can be performed using an 8-bit row address via eight address input pins that are not required when a row address is applied, for example. In this case, the 8-bit control signal is latched by control signal latch circuit 70 in response to activation of row address strobe signal / RAS. Control signal latch circuit 70
Generates an internal refresh instruction signal REF under the control of the mode control circuit 60 and supplies it to the refresh counter 61. The refresh counter 61
It is activated in response to the internal refresh instruction signal REF from the mode control circuit 60, and generates a refresh address. Row address latch 30 selectively passes a refresh address from refresh counter 61 in response to an internal refresh instruction signal from mode control circuit 60, and generates row decoders 50a and 50a as internal row address signals RA0-RA7.
to b. Thereby, row decoders 50a and 5a
0b each memory sub-array Ma in response to the selection signal.
And Mb, a refresh operation can be performed in parallel with the column selection operation performed on the latch circuit.

Further, in addition to the above configuration, it is also possible to perform error detection and correction of memory cell data read at the time of refresh. This configuration is shown as ECC circuits E1 to E16 in FIG. next,
A configuration for detecting and correcting an error in memory cell data during the refresh operation will be briefly described.

FIGS. 17A and 17B are diagrams showing an error detection / correction method used in the DRAM according to the present invention. FIG. 17 (A) and FIG.
In the configuration shown in (B), 9-bit memory cells are used as information bits, 7-bit memory cells are used as check bits, and a total of 16-bit memory cells are connected to one word line WL. The configuration in the case where there is is shown as an example. This configuration is described, for example, in Nikkei Microdevices March 1987, pp. 69-71. The 9 information bits are stored in memory cells MC0 to MC8. Memory cells MC9 to MC
Reference numeral 15 is used as a check bit for storing 7 parity check bits. In this configuration, 1
Six-bit memory cells are logically arranged in two-dimensional horizontal and vertical groups. At this time, as shown in FIG. 17B, the memory cells are arranged in the order of the numbers such that the memory cells are sequentially arranged diagonally in a matrix of four rows and four columns. That is, four physically adjacent memory cells in the memory cell array illustrated in FIG. 17A are grouped so that the memory cells in this unit belong to different horizontal and vertical groups, respectively. By such blocking, a divided selector configuration for selecting one of the adjacent 4-bit memory cells can be adopted for both the horizontal group and the vertical group. The horizontal group and the vertical group are selected by vertical group selection signals V0 to V3 and horizontal group selection signals H0 to H3.
Each of the memory cells MC9 to MC15 stores a parity bit in a horizontal group or a parity bit of a memory cell in a vertical group. FIG. 18 shows an example of a specific configuration of the ECC circuit.

FIG. 18 also shows, by way of example, a configuration in which a memory cell having a total of 16 bits of 9 information bits and 7 check bits is connected to one word line WL. In FIG. 18, memory cells are grouped in units of four memory cells to form four memory cell groups. Horizontal selectors HS1 to HS4 are provided to select one row in the horizontal direction for each of the four memory cell groups. Each of the horizontal direction selectors HS1 to HS4 selects one of the 4-bit memory cells in response to the horizontal group selection signals H0 to H3.

To select one row in the vertical direction among the four memory cell groups, vertical selectors VS1 to VS4
Are provided corresponding to the respective memory cell groups. Each of the vertical direction selectors VS1 to VS4 selects one memory cell in a corresponding group in response to vertical group selection signals V0 to V3. Vertical selector VS
The vertical group selection signal applied to each of 1 to VS4 is shifted by one bit. Horizontal group selection signal H for a selector for selecting a group in the horizontal direction
0 to H3 are given to the selectors HS1 to HS4 in the same order.

To perform a parity check in the horizontal direction, ExOR gates HE1 to HE receiving the output of each of the horizontal direction selectors HS1 to HS4 and adding the module 2
4 are provided. In order to perform a parity check in the vertical direction, the output of the vertical selectors VS1 to VS4 is
ExOR gates VE1 to VE4 for performing addition modulo.

The multiplexer MUX includes horizontal group selection signals H0 to H3 and vertical group selection signals V0 to V
3 selects the one-bit memory cell selected by the EXOR gate 20 and the data for the selected memory cell
0, and the output of the ExOR gate 200 is written again to the selected memory cell.

In order to detect an error in the memory cell selected by the horizontal and vertical group selection signals, ExO
An AND gate 201 receiving outputs of R gates HE4 and VE4 is provided. Next, the operation will be briefly described.

At the time of error detection / correction, a column address signal (horizontal / vertical selection signal, which is sequentially generated from refresh counter 61 by a control signal from mode control circuit 60 in the configuration shown in FIG. 1)
Are supplied to the selectors HS1 to HS4 and VS1 to VS4, respectively. These selectors select the memory cells in each row of the horizontal and vertical groups, and the memory cell data in each of them is E.
xOR circuits HE1 to HE4 and VE1 to VE4. If one memory cell data is incorrect in the horizontal selection group, the ExOR gate HE
4 is "1", and if all are correct, "0"
Becomes Therefore, when the data of the selected memory cell located at the intersection of the horizontal group and the vertical group is erroneous, the outputs of the EXOR gates HE4 and VE4 are both "1", and the output of the AND gate 201 is also "1". (H level). Multiplexer MUX
Reads 1-bit memory cell data designated by the horizontal and vertical group selection signals, and
xOR gate 200. ExOR gate 20
When the output of the AND gate 201 is at the H level, 0 is output by inverting the output of the multiplexer MUX.
On the other hand, when the output of the AND gate 201 is at the L level, the output data from the multiplexer MUX is passed as it is. The multiplexer MUX transfers the output data from the ExOR gate 200 to the selected memory cell data again, and writes the same into the selected memory cell data. Thereby, error detection and correction of the memory cell data can be performed.

With the above configuration, the horizontal group selection signal H0 is periodically output from the refresh address counter.
To H3 and the vertical group selection signals V0 to V4 are sequentially generated, so that error detection and correction of the memory cell data connected to the selected row can be performed. In this case, since the memory cells connected to one row of word lines are 64K bits, one row in each memory cell array block is also 4K bits. Therefore, in order to sequentially read out each 4K-bit memory cell data and perform error detection and correction, it is necessary to perform 4K times of error detection and correction. It is possible that the correction cannot be made. Therefore, in this case, a column is further divided into sub-blocks of an appropriate block size in one memory cell array block, and error detection / correction is performed on the divided sub-blocks using the configuration shown in FIG. Is performed, error detection and correction of all the memory cell data of 64 K bits can be reliably performed with a margin in one refresh cycle.

By providing the above configuration, error detection and correction of memory cell data can be performed at the time of refresh operation, and it is not necessary to perform error detection and correction at the time of data reading. Reading can be performed.

Further, usually, in a large capacity DRAM, the bit width of input / output data is set by a master slicing method or a connection switching of a bonding pad. In this case, the bit width of the input / output data is fixed and cannot be made variable. However, as shown in FIG. 1, a data bit length designating signal is applied by using an 8-bit address input terminal which is unnecessary at the time of taking in a row address, and the selector 62 and the I / O buffer 63 are operated by this control signal. Then, the bit length of the input / output data can be appropriately set according to the use of the DRAM.

In the structure shown in FIG. 1, 4-bit memory cells are simultaneously selected by 2-bit internal column address signals CA0 and CA1, and one or four bits of the data of these 4-bit memory cells are selected. A configuration for connecting to the I / O buffer 63 via 62 is shown. However, instead of this configuration, if a 3-bit column address signal is applied to the selector 62, the number of input / output data bits can be 8 bits. Further, with this configuration, the bit length of the input / output data can be freely set to 1 bit, 4 bits, and 8 bits according to the application.

Although the specific configuration is not shown, the number of address input terminals which are not used when applying a row address is eight.
Since the bits, the signal of the 8 bits, it is possible to specify two ⁸ kinds of operation modes, it is possible to provide a configuration for controlling the various diverse internal operations. Examples of such a configuration include a bit mask function and a bit comparison function.

In the above-described embodiment, a 16-Mbit DRAM is shown as an example of a large-capacity DRAM. However, the storage capacity of this DRAM is not limited to this, and other storage capacities may be used. Also, the same effect as in the above embodiment can be obtained.

Further, in the above-described embodiment, a configuration is shown in which a row address and a column address are applied in a time-division multiplexed manner. Alternatively, a DRAM (for example, PSD) in which a row address and a column address are applied simultaneously.
Even in a configuration such as a RAM, if the number of bits between the row address and the column address is made different, the data size of one page can be expanded, and the same effect as in the above embodiment can be obtained.

[0102]

As described above, according to the present invention, the number of bits forming the row address is made smaller than the number of bits forming the column address, so that the data size of one page can be expanded. , Faster access can be realized.

[0103] Furthermore, since sequentially activates the normal access mode Note rear lay blocks throughout memo rear ray, it is possible to reduce the peak current in the sensing operation of the memory cell data. Also, the row address and the column address are each constituted by an address bit taken in in response to a selection instruction signal applied at a different timing. Can be used as another control signal input terminal, thereby realizing a multifunctional storage device. Ma
And, according to the column selection instruction signal given by the second timing to the selected memory cell, the data write or read
By performing the output, writing of data in the page mode
/ Reading is possible .

The word lines are sequentially driven to the selected state via the repeater, and the row decoder is required only to drive the word line of one memory cell block. The circuit scale is reduced (since the current driving force is small and the element size is small). Further, in each memory cell array block, the selected word line is driven to the selected state by the repeater. Therefore, in each memory cell array block, the selected word line potential is driven to the selected state at high speed.

Since the data size of a page is expanded, when this DRAM is used as a video memory for writing / reading image data at high speed, image data can be written / read at high speed, and real-time Thus, a video memory that can be used in a system that processes image data can be obtained.

[Brief description of the drawings]

FIG. 1 shows an example of an overall configuration of a dynamic semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an arrangement of external pin terminals for inputting and outputting signals of a conventional 1 Mbit DRAM.

FIG. 3 is a diagram schematically showing an overall configuration of a conventional 1-Mbit DRAM.

FIG. 4 is a diagram schematically showing a configuration of a main part of a memory cell array of a conventional DRAM.

FIG. 5 is a diagram showing a schematic configuration of a conventional 16 Mbit DRAM.

FIG. 6 is a diagram schematically showing a configuration of a memory cell array portion of the dynamic semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a diagram schematically showing a configuration of a repeater connecting adjacent memory cell array blocks of the dynamic semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a signal waveform diagram representing an operation of the dynamic semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is a diagram showing an example of a circuit configuration for generating a signal for controlling the repeater shown in FIG. 7;

FIG. 10 is an operation waveform diagram showing generation timings of a sense amplifier activation signal and a repeater activation signal shown in FIG. 6;

FIG. 11 is a signal waveform diagram representing an operation at the time of data reading in the normal mode of the dynamic semiconductor memory device according to the embodiment of the present invention.

FIG. 12 is a signal waveform diagram representing an operation timing when reading data in a page mode of the dynamic semiconductor memory device according to the embodiment of the present invention.

FIG. 13 shows a structure of a main part of a dynamic semiconductor memory device according to another embodiment of the present invention.

14 is an operation waveform diagram showing a timing relationship between a transfer control signal for driving the transfer gate shown in FIG. 13 and a sense amplifier drive signal.

15 is a diagram showing an example of a circuit configuration for generating the transfer control signal shown in FIG.

FIG. 16 is a signal waveform diagram representing an operation of a dynamic semiconductor memory device according to another embodiment of the present invention.

FIG. 17A shows an arrangement of memory cells connected to one word line for an error detection / correction circuit;
(B) shows that the memory cells in one row shown in (A) are logically 2
It is a figure showing arrangement arranged in a dimension.

FIG. 18 shows the error detection and detection shown in FIGS.
FIG. 9 is a diagram illustrating a specific configuration example for performing correction.

[Explanation of symbols]

Ma, Mb memory subarray, M1 to M16 memory cell array block, B1 to B16 block including sense amplifier, column decoder and I / O gate, E1
To E16 error detection and correction circuit block, R1 to R14
Repeater, 11 row address strobe signal input terminal, 12 RAS system clock generator, 13 column address strobe signal input terminal, 14 CAS system clock generator, 15 R / W clock generator, 16 R / W controller, 20 address input Terminal, 30 row address latch, 40 column address latch, 60 mode control circuit, 70 control signal latch circuit, 62 selector, 63 I / O buffer, 90-1 to 90-3N
AND gate, 91-1 to 91-3 inverter, SA
Sense amplifier, L latch circuit, TR, TR 'I /
O gate, Q transfer gate transistor, 50a, 50
b Row decoder, 6 column decoder.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Richard Charles Foss Canada, CA2K1EX6 Ontario, Kanata, P.O.Box 13579, in Moside Incorporated ( 56) References JP-A-63-282996 (JP, A) JP-A-63-282997 (JP, A) JP-A-60-7690 (JP, A) JP-A-60-13393 (JP, A)

Claims (3)

(57) [Claims] 1. A semiconductor device comprising: a plurality of memory arrays each having a plurality of array blocks; each of the plurality of array blocks having a plurality of memory cells arranged in a matrix of rows and columns; A plurality of word lines arranged correspondingly, each connected to a memory cell in a corresponding row, and a plurality of bit lines arranged corresponding to each column, each connected to a memory cell in a corresponding column. has, further in response to a row address supplied from the external <br/> unit, before SL includes a row selection means for selecting one word line from each array block of the memory array, said row selection means the corresponding array in response to the block selection signals sequentially activated for each array block over previous SL plurality of memory arrays
Means for driving the word line of the block to a selected state, and further comprising column selecting means for selecting at least one column from the entire memory array in response to an externally applied column address; The number of bits forming the externally provided column address is made larger than the number of bits forming the externally provided row address, and the row address is the first.
A column selection signal composed of all address bits simultaneously taken in in response to a row selection instruction signal applied at the timing of, and wherein the column address is applied at a second timing later than the first timing in response to a column selection instruction is given in response consists of all address bits to be incorporated therein at the same time, and further
Bit lines are used to block corresponding memory array blocks.
After the activation of the clock select signal,
Selected sequentially based on the column address given in response
A dynamic semiconductor memory device in which data is written or read out . Comprising a wherein a plurality of memory arrays each having a plurality of memory array blocks, each of said plurality of memory array blocks includes a plurality of memory cells arranged in rows and columns Mato Riku scan shaped, each arranged corresponding to the row, the row corresponding to each have a plurality of word lines to which the memory cell is connected, further in response to a row address supplied from the external, a plurality of the plurality of memory arrays from each of the memory array block, row selection means for selecting a word line arranged corresponding to the rows where the row address is designated, coupled to said row selection means, a plurality of each of the previous SL plurality of memory arrays in response to the block select signal to a selected word line in the memory array block are sequentially activated for each memory array block throughout the previous SL plurality of memory arrays Comprising a sequence activation means for sequentially activating Te, wherein the sequential activation means, each of said memory array
A selected word of the plurality of memory array blocks
Line is driven to the selected state are sequentially activated, and each pre
Select word line of memory array block of memory array
Column select instruction signal applied repeatedly after sequential activation of
The plurality of memory arrays in response to each and a column address externally provided corresponding to each of the column selection instruction signals.
Selection for sequentially selecting at least one column of memory cells from the whole
The number of bits forming the externally applied column address is made larger than the number of bits forming the externally applied row address, and the row address is set at a first timing. The column address is constituted by all the address bits taken in response to the selection instruction signal, and the column address is simultaneously stored in response to a column selection instruction signal given at a second timing later than the first timing. Dynamic semiconductor memory device composed of all address bits taken into the memory. 3. A data to each of said following each <br/> column selection instruction signal given by the second timing, the row selection means and a memory cell on the selected row and column by column selection means
3. The dynamic semiconductor memory device according to claim 1, further comprising means for writing or reading data.