JP3677187B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that performs burst data transfer.
[0002]
[Prior art]
In a conventional DRAM having a basic configuration as shown in FIG. 10, as shown in FIG. 11, data read from a memory cell selected by a word line is given to sense up via a bit line, The pair of data sense-amplified by the sense-up is read out to the output buffer via the pair of FETs 101 whose conduction is controlled by the signal of the column select line CSL.
[0003]
FIG. 12 shows a partial configuration of one architecture of a conventional synchronous DRAM (SDRAM) with respect to such a DRAM. The configuration shown in FIG. 12 shows a data transfer path for performing a synchronous operation for one data input / output. The operation will be briefly described below.
[0004]
In outputting a series of serial data, if an address of the head data is given, two adjacent CSLs corresponding to the column select lines CSL1-2 are selected, and four data are read out to four pairs of DB lines. Since the data read from two columns at the same time in two clock cycles is serially output in the SDRAM 2-bit prefetch system, two pairs of data matching the serial access addressing from these four pairs of DB lines. The DB line is selected. This selection is performed by the DB select.
[0005]
The data of the selected two pairs of DB lines is transferred to the two pairs of RWD lines. The data of the two pairs of RWD lines is stored in the registers R1 and R2 for the first two cycles of data, and the data of the next two cycles is stored in R3 and R4. At this time, the RWD switches 1 and 2 determine in which order the data of the RWD line is stored in the register. Through this switch, the data is stored in the registers R1 to R4 in the order of access by the register transfer gates 1 and 2 that open alternately every two cycles, thereby realizing high-speed data output.
[0006]
The RWD switches 1 and 2 and the register transfer gates 1 and 2 shown in FIG. 12 are configured by gates made of, for example, FETs, and the data stored in the registers R1 and R4 are stored in the shift register 102, for example, as shown in FIG. The data is read out to the output buffer through the FET gate 103 whose conduction is controlled corresponding to each output.
[0007]
The timing diagram of FIG. 14 shows the state of the data transfer described above with time. FIG. 14 shows data transfer with a burst length of 8 and a latency of 3 from address setting.
[0008]
FIG. 14 shows the state of each part of FIG. 12, which will be described in order.
[0009]
First, / CAS becomes L in the clock cycle (CLK), the head address of a series of burst data is set, and access is started. After the head address is determined, an internal address is generated every two cycles in accordance with the addressing order of burst access of data, and two column select lines CSL rise to perform an access operation.
[0010]
When the column select line CSL rises, the DB line pair immediately enters the busy state. When data is sufficiently determined for the DB line pair, the DB selector operates to transfer data from two pairs of the four DB lines to the RWD line pair, and the RWD line is set to the busy state every two cycles. When data is sufficiently determined on the RWD line, one of the RWD switch and the register transfer gate 1 or 2 operates to store the data in the register.
[0011]
In this operation, the RWD switch is turned on when the appropriate one of 1 or 2 is selected by the burst data addressing, and the register transfer gate always turns on 1 and 2 alternately to store the data in the register. Go. As soon as each register transfer gate is turned on, the contents of the register are rewritten to enter the busy state, and data is output serially from OUTPUT.
[0012]
When controlling these burst data transfers, the internal operation is performed with a cycle of 2 clock cycles, so there is a limit to the start clock cycle of a new burst access after the end of a series of data burst accesses. come. There is a limit to starting a new access from any cycle after the end of the burst. In order to start a new access from an arbitrary cycle after the end of the burst, it is necessary to once reset the control of the clock cycle and start a new two clock cycles.
[0013]
For this reason, a data burst end signal is generated internally when a series of burst access is completed and access control of this burst becomes unnecessary. The control system is reset from the clock cycle in which this signal is generated. In FIG. 14, it is clock cycle 9. Since a new burst cycle cannot be started unless the reset is completed and a time of ten and several ns is required for the reset, a new start address is set from the clock cycle 11. Therefore, a new burst access cannot be set in clock cycles 9 and 10. Accordingly, new burst data cannot be output from the thick dotted line in FIG. 14, and data output from only the thin dotted line.
[0014]
[Problems to be solved by the invention]
On the other hand, in a conventional synchronous DRAM, a multi-bank cell array and a data transfer system are not optimally arranged, resulting in an increase in chip area.
[0015]
The present invention solves the above-described problems, and an object of the present invention is to optimize the arrangement configuration of a multi-bank cell array and a data transfer system, thereby preventing an increase in chip area. It is to provide a semiconductor device.
[0016]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a plurality of cells arranged in a matrix, and a plurality of cell arrays divided into a plurality of banks and n-bit (n is a positive integer) data between the plurality of cell arrays. A plurality of n-bit I / O buses for input / output; each bank is divided into m blocks (m is a positive integer) including a plurality of cell arrays; and the n-bit I / O buses are adjacent to each other. is used in time division into banks adjacent disposed between mutual banks, said n bit I / O bus of the n / m bit I / O bus for each n / m bits corresponding to each block group And each group of n / m bit I / O buses is located in a region adjacent to the corresponding block, and the first of the two groups of n / m bit I / O buses in one bank Group buses are second group Not not extend in parallel in the vicinity of the bus, each block in each bank, the data is input and output between the data bus of n / m-bit I / O bus and the blocks.
[0017]
[Action]
In the present invention, each bank is divided into m blocks, an n-bit I / O bus is divided every n / m bits, and each group of n / m-bit I / O buses is adjacent to a corresponding block. Arranged in the area. In addition, for any two groups of n / m-bit I / O buses in one bank, the first group buses do not extend in parallel with the vicinity of the second group buses. Therefore, since the I / O bus that can be used in a time-sharing manner between banks can be shared by the cell array and the bank, an increase in chip area can be prevented.
[0018]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
FIG. 1 is a diagram showing a configuration of a synchronous DRAM according to an embodiment of the present invention.
[0020]
In FIG. 1, a 64M (mega) bit synchronous DRAM is specifically considered. FIG. 1 shows an embodiment in which a 64M synchronous DRAM is configured as 4096 rows × 512 columns × 8 I / O4 banks.
[0021]
Each bank is composed of two blocks of eight 1-Mbit array pairs 1. More specifically, the 1M bit cell array pair 1 is composed of two cell arrays of 1024 columns × 512 rows sandwiching a sense amplifier. In each bank, each block has 4 I / O data buses 2. By dividing the bank into two blocks and corresponding to half I / O in this way, it is possible to handle 8 I / O with a bus corresponding to 4 I / O.
[0022]
In the activation of the cell array, for example, in the case of bank 1, the 1M cell array pair 1 with hatching is activated, and each cell array pair 1 corresponds to 2I / O data. The I / O bus 2 is composed of 4 I / O units, and is shared between two adjacent banks. This is because data transfer is not performed simultaneously with two banks due to the specification of the synchronous DRAM.
[0023]
Next, the configuration of the data transfer path between the cell array and the I / O bus will be described. FIG. 2 is a diagram showing a detailed configuration of the cell array pair 1 (shaded portion) in FIG.
[0024]
In FIG. 2, the cell array 3 has 1024 columns × 512 rows, and the sense amplifier (S / A) 4 performs a sensing operation of the activated cell array 3 shared by the cell arrays 3 on both sides. The S / A 4 arranged on both sides of the selected activated cell array 3 performs the sensing operation of the bit lines of the cell array 3. There are four pairs of data bus lines DB11, 12, 13, 14, 21, 22, 23, and 24 between the cell arrays 3, and two pairs are selected by the DB selector 5 for data transfer. This is the same as the description of FIG.
[0025]
Although not shown in FIG. 2, the connection between the bit line 6 indicated by the dotted line and the S / A 4 is disconnected from that of the cell array which is not activated. Is inserted in between.
[0026]
The bit lines 6 of one cell array 3 are distributed to the left and right two by two to form different I / Os. Column select lines CSL1 and CSL2 represent two adjacent column select lines that are simultaneously selected every clock cycle. As a result, four pairs of DB lines are connected to the S / A 4 for each I / O on both sides of the cell array 3.
[0027]
Next, FIG. 3 shows a state of connection with the RWD line constituting the I / O bus. FIG. 3 corresponds to a portion surrounded by a dotted line in FIG.
[0028]
In FIG. 3, the RWD line of each I / O shared by bank 1 and bank 2 is shown. It is assumed that the hatched portion 1 of the bank 1 is selectively activated. As shown in detail on the cell array 1, two cell arrays 3 are activated every other one. The DB selector 5 to be activated is also shown by diagonal lines, but in the illustrated half blocks constituting the bank, they are connected to the RWD lines of I / O 1, 2, 3, 4 in order from the end. Further, the remaining half of the bank (not shown) is connected to the RWD lines of I / Os 5, 6, 7, and 8. Since the DB line is shared by the cell arrays 3 on both sides, activation of the cell array 3 is performed every other line, and if such a data transfer path is connected, the address of each I / O is saved in the cell array. Can be assigned.
[0029]
Therefore, according to the configuration of the cell array and data transfer line path of the above embodiment, the bank is divided into blocks and the I / O allocation is divided into two, and the data bus that cannot be used in time division is localized as much as possible. A data bus that is separated and can be used in a time-sharing manner between banks or the like can share a data transfer path between a cell array, a bank, and the like, and a large capacity synchronous DRAM can be configured by minimizing an increase in the area of the system due to the data transfer path.
[0030]
In the above embodiment, one bank is divided into two. For example, as shown in FIG. 4, one bank is divided into four blocks, and each block is associated with a 2 I / O bus. Good.
[0031]
In the arrangement shown in FIG. 1, an I / O buffer (not shown) corresponding to each I / O bus 2 is adjacent to an I / O pad (not shown) as shown in FIG. If the pad is provided in the pad arrangement region 6, the wiring path between the I / O buffer and the I / O pad is shortened, and the chip area can be reduced.
[0032]
FIG. 6 is a block diagram of a clock system for controlling internal operations, showing an architecture for relaxing restrictions by reset explained in the conventional example for internal clocks for controlling data transfer.
[0033]
In FIG. 6, one signal path is indicated by a thick line. When a series of operations of this system is completed, a reset and switching signal is transmitted to each block as indicated by a dotted line.
[0034]
The external clock CLK is transmitted through the switch S1 to the internal clock system 1 that generates a signal for controlling the outputs of the registers R1 to R4 shown in FIG. Internal clock system 1 receives an external signal / CAS signal and generates an internal clock for control from external clock CLK. The internal clock passes through the switch W1 and drives the burst controller 7 that controls the burst of data access.
[0035]
When a series of burst access is terminated by the burst control unit 7 or a burst interrupt signal for interrupting burst access is input from the outside, an END signal is generated from the burst control unit 7 to generate a reset and switching signal ES8 Is output. The block ES8 alternately outputs the signal R1 or the signal R2 every time it receives the END signal. FIG. 6 shows the case where the signal R1 rises. At this time, the signal R2 rises. As a result, the switch S1 is turned off, the switch S2 is turned on, the internal clock system 1 enters the reset state, and the internal clock system 2 enters the standby state.
[0036]
Next, when the / CAS signal is input, the internal clock system 2 can operate at any time according to the external clock CLK. Further, the switch W1 is turned off and the switch W2 is turned on. As a result, the next burst control is performed from the internal clock system 2.
[0037]
In this way, the next operation can be performed using another internal clock system without waiting for the end of the reset of the internal clock system used so far, so that there is no limitation as in the prior art.
[0038]
The switches S1, S2, W1, and W2, the internal clock systems 1 and 2, and the burst control unit 7 shown in FIG. 6 are configured as shown in FIG. 7, for example, and the switches S1, S2, W1, and W2 are complementary types. The internal clock systems 1 and 2 are composed of FETs, and the internal clock systems 1 and 2 generate a control signal for sequentially controlling the conduction of the transfer gate 9 that controls the output of data from the registers R1 to R4, and the internal clock system generated by the shift register 10. 1 or an internal clock system 2 is selected by the switching signal R1 or R2 output from the block ES8 and is provided to the transfer gate 9, and the burst control unit 7 determines the length of a series of burst data transfers. A counter 12 for counting the length and determining the end, and an output of the counter 12 or a burst interrupt signal And a OR gate 13 for outputting an END signal by the input of.
[0039]
The block ES8 is configured as shown in FIG. 8, for example, and the clocked inverter 14 shown in FIG. 8 acts as an inverter when the signal written therein rises, and when the signal falls, the output becomes high impedance. Become. Since / END is a complementary signal to the END signal, the signals R1 and R2 rise alternately as shown in FIG. 9 every time the END signal is supplied.
[0040]
In this way, by providing two internal clock systems for controlling data transfer and using them alternately, it is possible to eliminate restrictions on data transfer due to the time taken to reset the clock system. Further, by combining with the configuration shown in FIG. 1, it is possible to provide a large-capacity SDRAM that combines cost reduction by reducing the area required for the system and ease of use by relaxing restrictions on data transfer.
[0041]
【The invention's effect】
As described above in detail, according to the present invention, the bank is divided into a plurality of blocks, the I / O bus is divided corresponding to each block, and the I / O bus is shared between adjacent banks. At the same time, since the data bus is shared between the adjacent cell arrays, an optimal arrangement configuration of the banked cell array and the data transfer mechanism is possible, and the configuration can be downsized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a relationship between a cell array and a data bus shown in FIG.
FIG. 3 is a diagram showing a relationship between a data transfer path and a bank shown in FIG. 1;
4 is a configuration diagram showing a modification of FIG. 1; FIG.
FIG. 5 is a diagram illustrating an arrangement example of an I / O buffer according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of a control circuit applied to the present invention.
7 is a diagram showing a specific example of a part of the configuration shown in FIG. 6;
8 is a diagram showing a specific example of a part of the configuration shown in FIG. 6;
9 is a diagram showing operation timing of the configuration shown in FIG. 8. FIG.
FIG. 10 is a diagram showing a basic configuration of a conventional DRAM.
11 is a diagram showing a partial configuration of FIG. 10;
FIG. 12 is a diagram showing a partial configuration related to burst data transfer of a conventional synchronous DRAM.
13 is a diagram showing a partial configuration of FIG. 12;
14 is a diagram showing operation timing of the configuration shown in FIG. 12. FIG.
[Explanation of symbols]
3 Cell array pair 2 I / O bus 4 Sense amplifier 5 DB selector 6 I / O bus, I / O bad arrangement area 7 Burst control unit 8 Block ES
9, 11 Transfer gate 10 Shift register S1, S2, W1, W2 switch

Claims (23)

A plurality of cells arranged in a matrix, a plurality of cell arrays divided into a plurality of banks, and
A plurality of n-bit I / O buses for inputting / outputting n-bit (n is a positive integer) data to / from the plurality of cell arrays;
Each bank is divided into m blocks (m is a positive integer) including a plurality of cell arrays,
The n-bit I / O bus is disposed between adjacent banks and is used in a time-sharing manner between adjacent banks.
The n-bit I / O buses are grouped into n / m-bit I / O buses every n / m bits corresponding to each block,
Each group of n / m-bit I / O buses is located in an area adjacent to the corresponding block, and for any two groups of n / m-bit I / O buses in one bank, the first group of buses Does not extend parallel to the vicinity of the second group of buses,
A semiconductor device, wherein data is input / output between an n / m bit I / O bus and a data bus of each block in each block of each bank.   2. The semiconductor device according to claim 1, wherein the n / m bit I / O bus is connected to an adjacent cell array in the block.   2. The semiconductor device according to claim 1, wherein the data bus is disposed between the adjacent cell arrays, and the adjacent cell arrays are alternately activated.   The n = 8 and m = 2, the 8-bit I / O bus is shared by adjacent banks, each bank is divided into two blocks, and each block is a part of the 8-bit I / O bus. 2. The semiconductor device according to claim 1, which corresponds to a 4-bit I / O bus.   N = 8 and m = 4, and an 8-bit I / O bus is shared by adjacent banks, each bank is divided into 4 blocks, and each block is an 8-bit I / O bus. 2. The semiconductor device according to claim 1, wherein the semiconductor device corresponds to a 2-bit I / O bus.   6. The semiconductor device according to claim 1, further comprising an I / O buffer corresponding to each I / O bus and connected to an I / O pad. A plurality of cells arranged in a matrix, a plurality of cell arrays divided into a plurality of banks, and
Activating means for activating the cell array;
A plurality of data buses provided in the plurality of cell arrays and having a first data bus set used in a time-sharing manner in a first adjacent cell array alternately activated by the activating means;
A plurality of n-bit I / O buses for inputting / outputting n-bit (n is a positive integer) data to / from the plurality of cell arrays;
Each bank is divided into m blocks (m is a positive integer) including a plurality of cell arrays,
The n-bit I / O bus is disposed between adjacent banks and is used in a time-sharing manner between adjacent banks.
The n-bit I / O buses are grouped into n / m-bit I / O buses every n / m bits corresponding to the blocks,
Each group of the n / m bit I / O bus is arranged in an area adjacent to the corresponding block, and in any two groups of the n / m bit I / O bus of one bank, the first group The bus does not extend parallel to the vicinity of the second group of buses,
A semiconductor device, wherein data is input / output between an n / m bit I / O bus and a data bus of each block in each block of each bank.   The plurality of data buses have a second data bus set including a predetermined number of data buses, and the second data bus set is used in a time division manner in a second adjacent cell array. 8. The semiconductor device according to claim 7, wherein each cell array of the cell array to be activated is alternately activated by the activating means.   9. The semiconductor device according to claim 8, wherein the first adjacent cell array shares one cell array of the second adjacent cell array.   8. The sense amplifier is provided between the first adjacent cell arrays, and the sense amplifier is connected to one of the first adjacent cell arrays via a bit line pair. Semiconductor device.   The semiconductor device according to claim 10, wherein the first data bus set is connected to the sense amplifier. A plurality of cells arranged in a matrix, a plurality of cell arrays divided into a plurality of banks, and
Activating means for activating the cell array;
A plurality of data buses provided in the plurality of cell arrays and having a first data bus set used in a time-sharing manner in a first adjacent cell array alternately activated by the activating means;
A plurality of n-bit I / O buses for inputting / outputting n-bit (n is a positive integer) data to / from the plurality of cell arrays;
Each bank is divided into m blocks (m is a positive integer) including a plurality of cell arrays,
The n-bit I / O bus is disposed between adjacent banks and is used in a time-sharing manner between adjacent banks.
Each of the n-bit I / O buses is arranged corresponding to at least one of the banks,
The n-bit I / O buses are grouped into n / m-bit I / O buses every n / m bits corresponding to each block,
Each group of the n / m bit I / O buses is arranged adjacent to a corresponding block,
A semiconductor device, wherein data is input / output between an n / m bit I / O bus and a data bus of each block in each block of each bank.   The plurality of data buses have a second data bus set including a predetermined number of data buses, and the second data bus set is used in a time division manner in a second adjacent cell array. 13. The semiconductor device according to claim 12, wherein each cell array of the cell array to be activated is alternately activated by the activating means.   13. The semiconductor device according to claim 12, wherein the first adjacent cell array shares one cell array of the second adjacent cell array.   The n = 8 and m = 2, the 8-bit I / O bus is shared by adjacent banks, each bank is divided into two blocks, and each block is a part of the 8-bit I / O bus. 13. The semiconductor device according to claim 12, wherein a 4-bit I / O bus is supported.   N = 8 and m = 4, and an 8-bit I / O bus is shared by adjacent banks, each bank is divided into 4 blocks, and each block is an 8-bit I / O bus. 13. The semiconductor device according to claim 12, wherein two of these I / O buses correspond to each other.   A data bus selection circuit provided corresponding to the first and second data bus sets and selectively connecting the first and second data bus sets to the adjacent n / m-bit I / O bus; The semiconductor device according to claim 13, further comprising: A first block disposed in a first row, a first column and having a plurality of memory cells;
A second block disposed in a first row and a second column, forming a first bank with the first block, and having a plurality of memory cells;
A third block disposed in the second row, first column and having a plurality of memory cells;
A fourth block disposed in a second row, a second column, forming a second bank with the third block, and having a plurality of memory cells;
A fifth block disposed in a third row, first column and having a plurality of memory cells;
A sixth block, arranged in a third row, a second column, forming a third bank with the fifth block, and having a plurality of memory cells;
A seventh block disposed in a fourth row, first column and having a plurality of memory cells;
An eighth block arranged in a fourth row and a second column, forming a fourth bank together with the seventh block, and having a plurality of memory cells;
Each of the first to eighth blocks is divided into a plurality of memory cell arrays,
A first I / O bus disposed between the first and third blocks and transferring data to and from memory cells in the first and third blocks;
A second I / O bus disposed between the second and fourth blocks and transferring data to and from memory cells in the second and fourth blocks;
A third I / O bus disposed between the fifth and seventh blocks and transferring data to and from memory cells in the fifth and seventh blocks;
A fourth I / O bus disposed between the sixth and eighth blocks and transferring data to and from memory cells in the sixth and eighth blocks;
And an activating means for activating a plurality of memory cell arrays in the same bank. Said activating means, claim 18, wherein the activating and N cell array of N cell array other in one block of the one bank in one block of the one bank The semiconductor device described. 20. The semiconductor device according to claim 19 , wherein N = 2. A first block disposed in a first row, a first column and having a plurality of memory cells;
A second block arranged in a first row, a second column and having a plurality of memory cells;
A third block arranged in a first row, a third column and having a plurality of memory cells;
A fourth block arranged in a first row and a fourth column, forming a first bank together with the first to third blocks, and having a plurality of memory cells;
A fifth block arranged in a second row, a first column and having a plurality of memory cells;
A sixth block disposed in the second row, second column and having a plurality of memory cells;
A seventh block disposed in the second row, third column and having a plurality of memory cells;
An eighth block arranged in a second row and a fourth column, forming a second bank together with the fifth to seventh blocks, and having a plurality of memory cells;
A ninth block disposed in a third row, first column and having a plurality of memory cells;
A tenth block disposed in the third row, second column and having a plurality of memory cells;
An eleventh block arranged in a third row, a third column and having a plurality of memory cells;
A twelfth block arranged in a third row and a fourth column, forming a third bank together with the ninth to eleventh blocks, and having a plurality of memory cells;
A thirteenth block disposed in a fourth row, first column and having a plurality of memory cells;
A fourteenth block arranged in a fourth row, a second column and having a plurality of memory cells;
A fifteenth block arranged in a fourth row, a third column and having a plurality of memory cells;
A sixteenth block arranged in a fourth row and a fourth column, constituting a fourth bank together with the thirteenth to fifteenth blocks, and having a plurality of memory cells;
A first I / O bus disposed between the first and fifth blocks and transferring data to and from memory cells in the first and fifth blocks;
A second I / O bus disposed between the second and sixth blocks and transferring data to and from memory cells in the second and sixth blocks;
A third I / O bus that is disposed between the third and seventh blocks and transfers data to and from memory cells in the third and seventh blocks;
A fourth I / O bus disposed between the fourth and eighth blocks and transferring data to and from memory cells in the fourth and eighth blocks;
A fifth I / O bus disposed between the ninth and thirteenth blocks for transferring data to and from memory cells in the ninth and thirteenth blocks;
A sixth I / O bus disposed between the tenth and fourteenth blocks for transferring data to and from memory cells in the tenth and fourteenth blocks;
A seventh I / O bus that is disposed between the eleventh and fifteenth blocks and transfers data to and from memory cells in the eleventh and fifteenth blocks;
And an eighth I / O bus that is arranged between the twelfth and sixteenth blocks and transfers data to and from memory cells in the twelfth and sixteenth blocks. Semiconductor device. Each of the banks includes a plurality of memory cell arrays having a plurality of memory cells arranged in a matrix, and further includes an activation circuit that simultaneously activates the plurality of memory cell arrays in the same bank. Item 22. The semiconductor device according to Item 21 . 23. The semiconductor device according to claim 22 , wherein the activation circuit simultaneously activates four memory cell arrays in one selected bank.

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