JPH0255877B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that combines a random access memory (RAM) with a multi-bit input/output configuration and a shift register for high-speed reading. Regarding equipment.

[Conventional technology]

Traditionally, the dynamics of 1-bit input/output configuration
RAM, e.g. 64K word x 1 bit configuration RAM
Semiconductor storage devices (memories) that combine a serial shift register and a serial shift register have already been announced. Also, a multi-bit input/output configuration, for example, a combination of a 4-bit RAM and an externally connected shift register, which has a similar function, has also been announced. This kind of memory generally allows high-speed reading of the shift register side asynchronously with random access on the RAM side, and the cycle time ratio between the RAM side and the shift register side is usually 1:5 to 1:10. . That is, with respect to data input/output between the CPU data bus and RAM, the speed of data transferred from RAM to the shift register and read from the shift register is extremely high, and therefore the speed of data transferred between the CPU and the video display device is extremely high. It is used for high-speed processing of image data.

[Problem that the invention seeks to solve]

Generally, if the bit configuration on the RAM side is 1 bit configuration, data transfer between the CPU data bus and RAM,
Especially when writing, compared to reading from the shift register,
As mentioned above, this is extremely slow, so interleaving methods and the like have been used to improve the transfer efficiency, but this requires the use of a large number of devices.

Therefore, it is conceivable to incorporate a shift register for high-speed serial reading in a RAM having a multi-bit input/output configuration to increase the data transfer speed by random access and to match the serial reading speed. Generally, multiple bit input/output configurations are used.
RAM has an internal structure made up of multiple blocks, for example, RAM with a 16K word x 4 bit structure.
Generally, a configuration is adopted in which four memory cell array blocks of 256 rows and 64 columns are arranged in parallel. In that case, the 4-bit data for each word is stored separately in each block, so a shift register in which each column output is coupled to each stage is attached to each block, and these shift registers are connected in series. If the configuration is such that the serial output is taken out, there is a problem in that simultaneous parallel writing or reading data by random access does not appear continuously all at once in the serial output, which is extremely inconvenient in data processing. To avoid this, it is possible to provide a separate data bus for each shift register attached to each block and convert the output from each shift register to serial output via a multiplexer, but the bus line This creates a problem in that it requires the addition of a multiplexer, which complicates the configuration.

[Means for solving problems]

An object of the present invention is to provide a semiconductor memory device that solves the above-mentioned problems, and the means thereof is to make each column output of a random access memory correspond to each stage of a shift register, and to perform a transfer operation of the shift register. Accordingly, each column output data is configured to be output as serial data, and the input/output device for multiple bit input/output is configured to access multiple columns corresponding to multiple adjacent stages of the shift register in parallel. The present invention is characterized in that data of multiple bits written or read simultaneously by parallel access by the output device is continuously outputted even in serial data output.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a semiconductor memory device as an embodiment of the present invention. In this example
It combines a 16K word x 4 bit RAM and a 256 bit serial shift register as a reading means. CPU data bus data is I/O ₁
~Access RAM simultaneously via I/O ₄
The contents of are transferred to and from the shift register, and the shift register serially outputs data at high speed from the terminal _SOUT in response to the shift clock _SCLK . This configuration has the feature that the RAM side can be randomly accessed as an independent memory asynchronously with high-speed reading by the shift register, and therefore, like an image memory between a CPU and a video display, It is used when high-speed serial data output and independent image data processing are required.

FIG. 2 is a block diagram showing the semiconductor memory device shown in FIG. 1 in detail. In Figure 2, 1 is a column decoder, 2 is a row decoder, and I/O ₁ to
I/O ₄ is an input/output device, SA ₁ to _{SA 256} are sense amplifiers, SR ₁ to _{SR 256} are shift registers as reading means, M is a plurality of memory cells, B is a bit line pair, and W is a word. The line pairs T ₁ and T ₂ are transfer gates provided between each sense amplifier and the data bus and between each bit line and each stage of the shift register, respectively, and TCLK is a transfer gate for turning on and off the transfer gate T ₂ . This is the transfer clock. The shift register performs a shifting operation using the clock S _CLK , and produces a serial output from the serial output terminal S _OUT . In such a configuration, each sense amplifier is controlled by a transfer gate _T1 controlled by the column decoder output.
They are connected to independent data bus lines DB ₁ to _{DB 14} in the order of the data bus lines as shown. That is, for 256 columns, 64 sense amplifiers are connected to the data bus line connected to one I/O.
The two sense amplifiers are connected to each other via a transfer gate _T1 . Such a connection method is also applied to other data buses. On the other hand, column decoder 1 carries any four sense amplifiers and selects four transfer gates _T1 at one time. This is done by counting four sense amplifiers as one and determining which one of the 64 sense amplifiers to select. Therefore, column decoder 1 selects one of 64 groups of four sense amplifiers each using six signals from addresses CA ₀ to CA ₅ , while row decoder 2 uses six sense amplifiers from addresses CA ₀ to _{CA 5} to select one of 64 groups. 8 lines are used to select one of the 256 word lines. In this way, in the present invention, as described above, the four sense amplifiers are connected in accordance with the order of the four data bus lines.
Data input simultaneously by bit random access is serially output from the shift register SR as adjacent data.

In this case, each stage of the shift register SR ₁ to _{SR 256}
The output of each column is the transfer gate as shown.
Since it is provided so that it is input via T ₂ , it is functionally divided into four stages each corresponding to the four data buses DB ₁ to _{DB 4} , similar to the sense amplifier. Therefore, the four columns that are accessed in parallel by I/O ₁ to I/O ₄ are connected to four adjacent stages of the shift register.
The bit write or read data is also continuous at the output of the shift register.

In the embodiment described above, the data bus and the sense amplifier are connected through the transfer gate, but it goes without saying that the data bus may be arranged and connected to the other end of the bit line.

〔Effect of the invention〕

As explained above, according to the present invention, the multi-bit configuration speeds up data writing and reading, but since the output of the shift register is used for high-speed image processing, multi-bit simultaneous input data and In this regard, the present invention can create a correlation between CPU processing and shift register output, and can process temporally close data together. can. Therefore, by making such data related to each other possible, it is possible to process a certain specific area with high efficiency in image processing, for example. As a result, an equivalently high transfer rate can be achieved by combining the multi-bit configuration and shift register according to the present invention.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device as an embodiment of the present invention, and FIG. 2 is a detailed block diagram of the device of FIG. Explanation of symbols: 1... Column decoder, 2... Row decoder, I/O... Input/output device, SA... Sense amplifier, SR... Shift register.

Claims (1)

[Claims] 1. In a semiconductor memory device that combines a random access memory with a multi-bit input/output configuration and a shift register for reading, each column output of the random access memory is associated with each stage of the shift register, and the shift register is The structure is such that each column output data can be output as serial data in accordance with the transfer operation of the register, and the input/output device for inputting/outputting multiple bits connects multiple columns corresponding to adjacent multiple stages of the shift register in parallel. What is claimed is: 1. A semiconductor memory device, characterized in that the data of multiple bits written or read simultaneously by parallel access by the input/output device is successively outputted also in serial data output.