JP2695265B2 - Multi-port memory - Google Patents

Description

TECHNICAL FIELD The present invention is used for raster scan graphics display, and outputs data for display to a random port for changing display contents by access from the CPU side and display. The present invention relates to a multi-port memory having a serial port that operates.

Conventional technology As a frame buffer for bitmap display systems, DRAM-based multi-port memory appeared in the 64K-bit era. This is provided with a serial access memory (SAM) in addition to a random access memory (RAM) composed of DRAM memory cells so that data for one word line of the RAM can be collectively transferred to the SAM. The data once transferred to the SAM is output as display data from the serial port, which is independent of the random port, so even when the display data is being output, the CPU side accesses the RAM via the random port and rewrites the display contents. be able to. When the conventional general-purpose DRAM was used to configure the frame buffer, the CPU could only access for drawing during the display blanking period, but with the advent of this multi-port memory, RAM to SAM It became possible to access for drawing anytime except during the data transfer period, and the drawing efficiency was greatly improved.

With the increase in the integration density of general-purpose DRAM, multi-port memory has come to have a high integration density of 64K bits to 256K bits, and further 1M bits. At the same time as the generational change due to the improvement in the degree of integration, functionally, the real-time data transfer function, pointer function, write mask function,
Each function such as arithmetic write function, block write function and flash write function was added. However, the basic configuration of transferring data for one word line from RAM to SAM in the data transfer cycle has not changed.

An example of such a conventional multi-port memory is shown in FIG. FIG. 4 is a main part of a 256K-bit multiport memory having a 64K × 4 bit structure, which is provided with a memory cell array 1, a row decoder 2, a column decoder 3, a serial data register 4 and a random port input / output circuit 5. . An actual chip is often divided into several blocks due to layout considerations, wiring resistance, wiring capacitance, etc., but the basic configuration is as described above.
In addition, two bit lines and data lines are actually used as a pair including a line for complementary data, but it is not necessary to draw two lines separately for the description of the present invention. Therefore, it is represented by one line for simplicity.

First, consider the case of accessing the multi-port memory from the CPU side and writing data from the random port for drawing. Random port data input / output terminal
According to the data input from I / O ₀ , I / O ₁ , I / O ₂ , I / O ₃ ,
The random port input / output circuit 5 has data lines D ₀ , D ₁ , D ₂ , D ₃
Drive. Of the bit lines B ₁ , B ₂ , ..., B ₁₀₂₄ , one selected by the column decoder 3, for example, B ₁ , B ₂ ,
B _3, B ₄ are respectively connected to the data lines _{D 0, D 1, D 2} , D 3 via the column selection transfer gate _{T 1, T 2, T 3} , T 4. as a result,
In the memory cell array 1, data is written in the memory cells of the row selected by the row decoder 2 on the bit lines B ₁ , B ₂ , B ₃ , B ₄ .

On the other hand, considering the case where data is output from the serial output terminal of the serial port for display, first, in the data transfer cycle, the data in the memory cells in the row selected by the row decoder 2 is transferred to the bit lines B ₁ , B ₂ , …
…, Transfer from B ₁₀₂₄ directly to serial data register 4. The data transferred to the serial data register 4 is serially output from the serial output terminals SO ₀ , SO ₁ , SO ₂ , SO _{3 of} the serial port in units of 4 bits in synchronization with the serial clock and used for CRT display.

5th with 4 such 256Kbit multi-port memories
One plane of a display screen of 1024 × 1024 pixels as shown in the figure can be constructed. For example, divide the screen vertically into four and
Lines 1 to 256 are the first multiport memory, 257
Lines 512 through 512 are the second multiport memory, 513
Lines 768 to 768 is the third multiport memory, 769
Lines 1024 to 1024 may be allocated as a fourth multiport memory. The 4 bits that are output simultaneously from the serial port use a P / S conversion circuit to display 4 consecutive pixels on the display screen in the horizontal direction, such as P _(0,0) ,
It shall be assigned to P _(0,1) , P _(0,2) , and P _(0,3) . Considering the movement of the scanning line on the CRT, the data serially output from the serial port will be allocated side by side in the order in which they are output on the horizontal line. The number of bits in the serial data register is the same as the number of all bit lines 1024
Therefore, one line of data transfers one row of horizontal data from the RAM to the SAM on the display screen of FIG.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, in the conventional multi-port memory, one row of data obtained by selecting the row address is transferred from RAM to SAM, and the data is moved by the scanning line on the CRT. It was outputting serially according to. for that reason,
One line of data in RAM corresponds to one line of pixels on the display screen, or, depending on the screen configuration, part of one line on the screen or part of two lines at maximum. It was.

However, then, considering the case of drawing vertical and horizontal lines, which is often the case when displaying figures with EWS etc.,
In the example shown in FIG. 5, the horizontal line allows data for 4 pixels to be written to the RAM in one write cycle.
Even if multiple write cycles are required for lines of more than pixels, pixels arranged in the horizontal direction correspond to the same row of RAM, so writing can be performed using a high-speed access mode such as page mode, and at a relatively high speed. Can be drawn. However, since a vertical line must be written in a normal access mode in which both the row address and the column address are input pixel by pixel, drawing time becomes long. Therefore, the burden on the CPU side for drawing becomes large, which causes a decrease in display speed.

In order to shorten the drawing time, even with the conventional multi-port memory, some 1Mbit products have added high-speed write functions such as block write and flash write. However, all of these are high-speed writing functions along the scanning line of the CRT, which is effective for speeding up the filling of the surface, etc., but for the drawing of figures consisting of vertical, horizontal, and diagonal lines. Had little effect.

Means for Solving the Problems In order to solve the above problems, the present invention associates one line of data in a RAM with a two-dimensional rectangular area (hereinafter, this rectangular area is called a page) on a display screen, Make it possible to draw vertical and horizontal lines with one access on this page, and even if it is a figure such as diagonal lines that can not be drawn at once, draw with high-speed access mode such as page mode as long as it is on this page It enables you to do it.

To achieve this object, the multi-port memory of the present invention comprises a memory cell array arranged in a matrix, row access means for accessing a selected row of the memory cell array according to a row address, and the memory cell array of the memory cell array. A plurality of columns belonging to any one of a plurality of column groups each of which is obtained by dividing the entire example
First column access means for simultaneously selecting according to the column address of, and electrically coupling to a plurality of data lines, respectively.
At least one column from each of the plurality of column groups,
Second column access means for simultaneously selecting according to a second address and electrically coupling to the plurality of data lines, and a row selected by the row access means through the plurality of data lines, Write means for writing data input from a random port to a memory cell in a column selected by the first column access means or the second column access means, and a serially coupled electrically connected to the plurality of data lines. A serial data register that can be serially accessed from the port, and is selected by the row address via the plurality of data lines using the row access means and the first column access means during a data transfer operation. Of the data in the memory cells in the selected row, only the data in the column selected by the first column address is selected. Characterized in that it forwards to the serial data register.

Function With this configuration, it is possible to write vertical lines or figures that extend over two or more scanning lines in a page to RAM faster than conventional multi-port memory. The time to access the memory is shortened and the drawing speed is improved.

Embodiment An embodiment of the multiport memory of the present invention is shown in FIG. The bit lines B ₁ , B ₂ , ..., B ₁₀₂₄ in FIG. ₁ are the bit lines B ₁ , B ₂ , ... B _{32 in} FIG. 5 showing the display screen when, for example, the row R ₁ is selected. Is the pixel P _(0,0) , P _(0,1) ,
……, P _{(0, 31)} , bit lines B ₃₃ , B ₃₄ ,…, B ₆₄ are pixels
P _(1,0) , P _(1,1) , ..., P _(1,31) , ..., bit line B
₉₉₃ , B ₉₉₄ , ..., B ₁₀₂₄ is the pixel P _(31,0) , P _(31,1) , ...
…, It corresponds to P _(31,31) .

FIG. 3 is an enlarged view of a page composed of such 32 × 32 pixels. Each time a row address is input and one row is selected by the row decoder 2, one page of pixels is selected on the display screen. The more detailed location within this page is specified by the column address.

For CRT display, for example, pixels P _(0,0) , P _(0,1) , ...
…, When transferring the data of P _(0,31) to the serial port, the column address designating the first row of the page row is input to the horizontal column decoder 3 and the bits belonging to the first row of the same page row are input. The data on lines B ₁ , B ₂ , ..., B ₃₂ is the column select transfer gate T.
Data lines D ₀ , D ₁ , ..., D ₃₁ through ₁ , T ₂ , ..., T ₃₂
And is input to the serial data register 4.
In the example of FIG. 1, such a data transfer cycle is executed every time 32 pixels are displayed on the CRT.

Next, let's look at writing data from the CPU side to the multiport memory for drawing. First, the page to be drawn is selected by the row address. When writing the vertical line A in FIG. 3 on this page, the vertical line A
The column address designating the second column of the page column is input to the vertical column decoders 6, 7, ..., 37, and the bit lines B ₂ , B ₃₄ , ... belonging to the second column of the page column in each page row are input. …, B
_The data on the data lines D ₀ , D ₁ , ..., D ₃₁ are transmitted to the column ₉₉₄ through the column selection transfer gates T ₁₀₂₆ , T ₁₀₅₈ , ..., T ₂₀₁₈ , and selected by the row address representing the page on these bit lines. The data is written in the memory cells that are being written. On the data lines D ₀ , D ₁ , ..., D ₃₁ , the random port input / output circuit 5 allows the data input / output terminals I / O ₀ , I / O
The data input from O ₁ , ..., I / O ₃₁ is transmitted.

When writing the horizontal line C in FIG. 3 within the page,
As with the transfer cycle, a horizontal column decoder is used. That is, the column address designating the second row of the page row is input to the horizontal column decoder 3, and the column selection transfer gate T ₃₃ is applied to the bit lines B ₃₃ , B ₃₄ , ..., B ₆₄ belonging to the second row of the page row. , T ₃₄ , ..., through T ₆₄ , data lines D ₀ , D ₁ , ...
..., data D ₃₁ is transmitted, the data is written to the memory cells belonging to the selected row in these bit lines. As described above, in the page, it is possible to draw any of the horizontal and vertical lines of 32 pixels in one write cycle.

In the case of the slanted line B in FIG. 3, writing cannot be performed once, but even if writing is performed for every two pixels using the vertical column decoder, the writing can be performed 16 times, which is half that of the conventional multi-port memory. Complete. In addition, these writing operations can use the page mode cycle, which takes about half the time of the normal writing cycle, so that drawing will be completed in about 1/4 of the time required by the conventional multi-port memory.

In the case of the embodiment shown in FIG. 1, every time 32 pixels are displayed on the CRT, a transfer cycle must be executed to transfer new data to the SAM. Since access from the random port side is not possible during the transfer cycle, depending on the case, the large number of transfer cycles may cause a decrease in drawing efficiency. In order to improve this point, the portion other than the random port input / output circuit 5 in FIG. 1 may be used as one block, which is connected and used as shown in FIG.

In FIG. 2, 39, 40, 41 and 42 are such blocks. In order to select which block is accessed from the random port, the block decoder 38 and the block selection transfer gate T ₂₀₄₉ , T ₂₀₅₀ , ..., T
₂₁₇₆ is provided. The serial port output of each block is multiplexed by the multiplexer 43, and when the serial output from the block 39 is completed, the next block 40,
When the serial output from the block 40 is completed, the four blocks 39 to 42 are sequentially switched to the block 41, and the serial output is obtained. Therefore, once the data transfer cycle is executed, data for 128 pixels can be serially output. That is,
One data transfer cycle may be executed while displaying 128 pixels on the CRT.

When the multi-port memory shown in FIG. 2 is used, the selection of one row address selects an area for four continuous pages in the horizontal direction on the display screen. The four pages correspond to a block 39, a block 40, a block 41, and a block 42 in order from the left. The multi-port memory of FIG. 2 has 256K memory cells in each block as shown in FIG. 1, so that the number of blocks is 1M, and can be made into one chip by the current manufacturing technology. If this is used, in the case of a 1024 × 1024 display screen as shown in FIG. 5, data for one plane can be stored in one chip.

Effects of the Invention As described above, according to the present invention, it is possible to realize a multi-port memory capable of drawing a line perpendicular to the scanning line direction or a figure extending over two or more scanning lines at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a multiport memory according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. FIG. 4 is a schematic diagram showing one page on the display screen when displaying, FIG. 4 is a block diagram showing a configuration of a conventional multiport memory, and FIG. 5 is a display screen when displaying using the multiport memory. It is a schematic diagram which shows. B ₁ , B ₂ , ……, B ₁₀₂₄ …… Bit line, D ₀ , D ₁ , ……, D ₃₁
…… Data line, T ₁ , T ₂ , ……, T ₂₀₄₈ …… Column select transfer gate.

Claims (2)

(57) [Claims] 1. A memory cell array arranged in a matrix, row access means for accessing a selected row of the memory cell array according to a row address, and an entire column of the memory cell array obtained by dividing. First column access means for simultaneously selecting a plurality of columns belonging to any one of a plurality of column groups each including a plurality of columns in accordance with a first column address and electrically coupling them to a plurality of data lines, respectively. Second column access means for simultaneously selecting at least one column from each of the plurality of column groups in accordance with a second column address and electrically coupling the plurality of data lines to the plurality of data lines, respectively. In a row selected by the row access means via a line, the first
Write means for writing the data input from the random port to the memory cell of the column selected by the column access means or the second column access means and the serial port electrically connected to the plurality of data lines. A serial data register that is serially accessible, and a row selected by the row address via the plurality of data lines using the row access means and the first column access means during a data transfer operation. Among the data of the memory cells of (1), only the data of the column selected by the first column address is selectively transferred to the serial data register. 2. A plurality of blocks comprising the memory cell array according to claim 1, row access means, first and second column access means, and serial data registers, and at least one of the plurality of blocks. A multi-access unit having block access means for selecting one block and accessing it from a random port, and serial access means for serially accessing the contents of serial data registers of the plurality of blocks serially from the serial port. Port memory.