JPH02186834A - Line memory - Google Patents

Abstract

PURPOSE:To enable write to be started from an arbitrary address by setting a start address on a write address generation circuit from the outside by a start address setting means. CONSTITUTION:The initial values A1-Am (m is positive integer) of write addresses are supplied from the outside to the write address generation circuit 3 consisting of a counter to which the initial value can be inputted, and also, the initial values A1-Am are inputted by supplying a load signal, the inverse of LD, and are set on the counter. Also, a write address generated at the write address generation circuit 3 is returned to '0' when an address progresses to the final address of a memory cell array 1, and hereafter, it is incremented again. Thus, since the start address can be set on the write address generation circuit 3 from the outside by the start address setting means, the write can be started from the arbitrary address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line memory suitable for use in scrambling video signals in pay broadcasting, for example.

[Conventional Technique vFI] In recent years, with the development of digital signal processing technology, various types of memories have been developed for different purposes, such as dual-port memory cards and memory for image processing.

Line memory is one such memory, and this line memory is a memory for storing data for one horizontal scanning period of a video signal.

FIG. 3 shows the configuration of the original line memory. In the figure, 1 is a memory cell array that can store data for one scanning interval of a video signal, and 2 is a memory cell array that can store data for one scanning interval of a video signal, and 2 is a memory cell array that stores data Dil- (n is a positive integer) in a memory array. 3 is a write address generation circuit configured as a counter and generates a write address; 4 is an output huffer for reading 11 pieces of data Dol to Don from the memory cell array; 7.5 is a read address generation circuit composed of a counter and for generating a read address.

In the above configuration, the memory cell array! To obtain it, proceed as follows.

That is, the start-up reset signal n (shown in FIG. 4B) is supplied to the write address generation circuit 3, the counter therein is reset to rQJ, and the write clock WCK (fourth Diagram A
(shown in FIG. 4C) is supplied, and the write address is sequentially incremented (shown in FIG. 4C).

In addition, the write enable signal T
1 is supplied, a write clock WCK is also supplied, and n-bit data Dil to D'1 are sequentially supplied to the memory cell array 1 via the manual buffer 2.

As a result, n pieces of data Dil-Din are sequentially written into the memory cell array l starting from address "0".

On the other hand, reading from the memory cell array l is performed as follows.

That is, the read reset signal R (shown in FIG. 5B) is supplied to the read address generation circuit 5, the counter therein is reset to "0", and the read address generation circuit 5 is supplied with the read clock. R.C.K.
(shown in FIG. 51A) is supplied, and the read address is sequentially incremented (shown in FIG. 5C).

The output buffer 74 also has a read enable signal ■
1 is supplied, read a clock RCK is supplied, and n-bit data Do from memory cell array 1 is supplied.
1 to Don are sequentially outputted via the output buffer 4.

As a result, from the memory cell array 1, the address r O
Eleven pieces of data Dol to Don are sequentially read from J.

Note that writing and reading are performed non-synchronously.

Such a line memory is used, for example, as a memory for line delay, time axis conversion, or synchronization of multiple input signals in television receivers and video tape recorder systems.

[Problems to be Solved by the Invention] By the way, in the line memory shown in the example in FIG. 3, writing cannot be started from an address in the middle of the memory, so
Movie I! ! It has become common practice to cut the data for one horizontal scanning interval of a signal at the junction and swap the left and right sides. Therefore, in this invention, writing can be started from the address of the designated person, and the input Its purpose is to provide memory.

[Means for Solving the Problems] The present invention provides a line memory comprising a write address generation circuit, a read address generation circuit, and a memory cell array capable of storing data for one horizontal scanning period of a video signal. The write address generation circuit is provided with a start address setting means for externally setting a start address.

[Function] In the above configuration, the write address generation circuit 3
Since the start address can be set externally by the start address setting means, writing can be started from any address.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, the write address generation circuit 3
It consists of a counter that can be manually operated. This write address generation circuit 3 is supplied with the initial value AI - Am (m is a positive integer) of the write address from the outside, and this initial value Al set on the counter.

The write address generated by the write address generation circuit 3 returns to "0" when it reaches the final address of the memory cell array 1, and is incremented again thereafter.

The rest of the structure is the same as the example shown in FIG.

In the above configuration, writing to the memory cell array 1 is performed as follows.

That is, the write address generation circuit 3 receives the rotat signal r.
By supplying T (shown in FIG. 2B), a period value At-Am (shown in FIG. 2C) is manually set in the counter. As a result, the write start address is specified by the initial pjl value Al-Am (0≦X≦2
-1). Then, the write clock W CK (shown in FIG. 2A) is supplied to the write address generation circuit 3, and the write address is incremented by 1111th (shown in the second diagram). This write address is "0" when it becomes the final address 21-1 of memory cell A1.
and is incremented again.

In addition, the human buffer 72 receives a write enable signal V.
At the same time, a write clock \VC+ (is supplied), and n-bit data D11 to Dn are sequentially supplied to the memory cell array l via a large-power buffer 72.

As a result, n-bit data Dil to Din are sequentially written into the memory cell array l from the address rXJ.

On the other hand, reading from the memory cell array 1 is performed as follows, similar to the example in FIG.

That is, the read reset signal WmiTi (shown at No. 511B) is supplied to the read atosis generation circuit 5, and the counter therein is reset to "rQ", and the read atsis generation circuit 5 is supplied with the read clock RCK.
(, shown in FIG. 5A) is supplied, and the read address is sequentially incremented (shown in FIG. 5C).

The output buffer 74 also has a read enable signal R.
At the same time as E is supplied, a read clock PCI (is supplied), and n pieces of data Doi to Don from the memory cell 7 ray 1 are output 111α times via the output sofa 4.

As a result, from memory cell array 1, address “0” is sent from memory cell array 1.
”, the n pit data Do1 to Don are sequentially read out.

As described above, according to this example, data Dil to Din of f1 bits are sequentially written from address "x" to memory cell array 1, and data [)ol to Since Don is read out sequentially, the period value A1 that specifies the address "xJ" is read out sequentially.
By changing ˜Am, it is possible to obtain data in which the left and right sides are swapped by cutting off the data for one horizontal scanning period of image (No. 3) by the portion of sweat I.

It is clear that if x=O is set, the same operation as in the example in FIG. 3 will occur.

[Effects of the Invention] As explained above, this invention allows the start address to be externally set in the 1M write address generation circuit by the start address setting means, so it is possible to set the start address from the outside using the start address setting means. You can start writing. Therefore, by changing the start address, data for one horizontal scanning interval of the video signal can be arbitrarily cut off to obtain data with the plastering replaced.1 For example, it can be used to scramble the video signal in pay broadcasting. This makes it suitable.

The drawings, FIGS. 4 and 5 are diagrams for explaining the same.

Reference memory selfie 9 person hippo sofa ・Blue color atsis generation circuit Bone output buff 7 ◆Read address generation circuit

Claims (1)

[Claims] (1) In a line memory comprising a write address generation circuit, a read address generation circuit, and a memory cell array capable of storing data for one horizontal scanning period of a video signal, an external signal is input to the write address generation circuit. A line memory characterized in that a start address setting means for setting an address is provided.