JPS61234474A - Picture image storage device - Google Patents

Abstract

PURPOSE:To eliminate a complicated logic circuit for hardware by keeping n-bit of selected data for the one period of a clock signal, generating n-set of output control signals and providing the second buffer means which supplies the signal to n-set of buffer means, respectively. CONSTITUTION:N-set of picture image data which are read out of n-set of picture image memories 20a-20n are supplied to n-set of buffer means 25a-25n and to n-set of discrimination means 24a-24n. The n-set of means 24a-24n discriminate whether the n-set of picture image data are transparent or opaque, respectively, and generate n-set of discriminating signals. A priority memory 27 is accessed by the n-set of discrimination signals and reads out n-set of selected data. the n-set of selected data are kept for the one clock period by the second buffer means 28 and n-set of output control signals are generated. The n-set of output control signals are generated. The n-set of output control signals are supplied to the n-set of means 25a-25n where n-set of picture image data area kept for one clock period respectively and the picture image data from a single means 25a-25n are outputted to a data bus 22.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image storage device, and relates to an image storage device that generates image data for multi-layer display in which multiple images are superimposed.
Regarding IT & storage devices.

2. Description of the Related Art Conventionally, in animation, as shown in FIG. A single multilayer image as shown in FIG. 2 (8) is obtained by superimposing the images.

FIG. 3 shows a block system diagram of an example of a conventional image storage device. This device also operates on the same principle as animation, and each of the image memories 5a to 50 is
Image data corresponding to each of cell images 1a to 1n of > is stored. The image data read out synchronously from the image memories 58-5n are supplied to the data selector 6 and decoders 78-7n. The decoders 78 to 7n determine whether the image data is transparent or opaque, generate a determination signal, and supply it to the priority encoder 8. Priority encoder 8
performs a logical operation on the discrimination signals of each of the decoders 78 to 70, generates an output control signal for selecting the image data with the highest predetermined priority from among the image data indicating opaqueness, and outputs the output control signal to the data selector. Supply to 6. As a result, the data selector 6 sequentially selects and extracts the opaque image data with the highest priority. A video signal is generated based on this image data, and multiplexed ii! i-image is displayed on the monitor.

Problems to be solved by the invention For example, if a standard color video signal of the NTSC system is
When sampling at approximately 00 pixels, the image memory 58
The reading time of image data of 1 pixel of ~50 each is 1o
It is about onsec. That is, decoding, priority encoding, and data selection must be performed within '+oonsec, and in this case, the processing time of the priority encoder 8 must be approximately within 2 On5ec. Since high-speed calculation is required in this way, the priority encoder 8 is constructed of a hard logic circuit. Therefore, if the priority encoder 8 has a total of 4 priorities 5n and 4 layers, 1 of the data selector 6
− ゛ is fixed. Further, the portion of the image memory 58 to bits for image data has a configuration as shown in FIG. 4. 1-bit image data from four image memories 5a etc. is input to terminals 98 to 9b, and terminals 10a and 10 are input to terminals 98 to 9b.
A selection control signal from the priority encoder 8 is input to b, and the selected - image data is output from the terminal 11. For example, if the image data has an 8-bit configuration, eight circuits of the circuit shown in FIG. 4 are required, and if there are eight image memories 5a to 5n (eight layers), the circuit becomes even more complicated. In this way, the hard logic circuit becomes complicated with many elements, and furthermore, each of the image memories 5a to 5n is connected to the data selector 6 by a mutually independent data bus, and this data bus also has an 8-bit 8-layer structure. The problem was that it was made into a book and had little practical use.

Accordingly, the present invention provides an image storage device that solves the above problems by retaining image data from a first memory for one clock period, generating an output control signal during this period, and selectively outputting the image data. The purpose is to provide

Means for Solving the Problems In the present invention, n sets of image data are stored in each of the n sets of first memories, and the n sets of image data read out from these using a clock signal are The signals are supplied to n sets of first buffer means and n sets of discrimination means. The n sets of determination means each determine whether the n sets of image data are transparent or opaque, and generate n sets of determination signals. The second memory is accessed by n sets of discrimination signals to read n bits of selection data. This selection data of n pits is held for one clock cycle by the second buffer means, and n sets of output control signals are generated. The n sets of output control signals are supplied to the n sets of first buffer means each holding the n sets of image data for 1 to 0 cycles, and the image data from the single first buffer means is Output to the data bus.

In the present invention, the first buffer means holds the image data for one period of the clock signal, and the second buffer means holds the selected data for one period of the clock signal. This allows sufficient time from reading the image data from the first memory to outputting it to the data bus, making it possible to control the output using the selection data of the second memory.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention. In the figure, 20a, 20b, ., 2On are n(n
is an integer greater than or equal to 2) image memories (first memories). The image memories 20a to 20n are supplied with a control signal address, for example, 8-bit image data, from the computer system 21 via a bidirectional path line 22, and the image data is written therein. For example, images corresponding to cell images 18 to 10 shown in FIG. 1A are stored in each of the image memories 20a to 2On.

In addition, a clock signal and a horizontal synchronization signal (H) from the clock and synchronization signal generator 23 in which one round of the nail corresponds to one pixel are generated.
and vertical synchronization signal @(V) are respectively supplied.

FIG. 5 shows a more detailed circuit configuration of each of the image memories 20a to 2On. Addresses from the computer system 21 coming in through the path line 22 are supplied to an address buffer 40, image data is supplied to a data buffer 41, and an access request signal among the control signals is supplied to a request control circuit 42. be done. Further, the clock signal coming from the clock and synchronization signal generator 23 via the terminal 23a is supplied to the request control circuit 42 and the address generator 43, and the horizontal synchronization signal (H) and vertical synchronization signal (V ) is supplied to the address generator 43. The request control circuit 42 supplies a write request signal to the memory 44 and also supplies control signals to the data buffer 41 and data selector 45 when no clock signal is received from the terminal 23a, for example. This allows address buffer 4
Addresses starting from 0 are selected by the data selector 45 and supplied to the memory 44, image data from the data buffer 41 is supplied to the memory 44, and image data from the computer system 21 is written to the memory 44. Here, it is assumed that the image data is composed of, for example, 8 bits per pixel, and the memory 44 can be addressed for each pixel.

When a clock signal is received, request control circuit 42 supplies a read request signal to memory 44 and a control signal instructing data selector 45 to select an address from address generator 43. At this time, the address generator 43 is reset by the vertical synchronization signal (V) and the horizontal synchronization signal (H), counts the clock signal, and generates a read address. This read address is supplied to the memory 44 via the data selector 45, and the image data is read from the memory 44. The read image data is output via the read buffer 46.

Each of the image memories 20a to 20n receives a horizontal synchronization signal (H) from a clock and synchronization signal generator 23.

Synchronization is achieved by a vertical synchronization signal (V).

By the way, for example, the address generator 43 of the image memory 20a
By varying the count value reset by the horizontal synchronizing signal (H) every vertical scanning period, it is possible to move only the cell image 1a shown in the first diagram in the horizontal direction of the screen, for example. The image data output from each of the image memories 20a to 2On is transmitted to a comparator (discrimination means) 24a to 2, respectively.
4n, latch and driver circuit (first buffer means)
25a to 25n, respectively.

Data registers 26a-26n each store image data supplied from computer system 21 and supply it to comparators 24a-24n, respectively. Of course, the data registers 26a to 26n are assigned addresses, and the stored contents of any data register can be changed.

The comparator 24a compares the image data from the image memory 20a and the image data from the data register 26a, and when the two match (or when the former is larger,
(or when the former is small) outputs, for example, an H level discrimination signal indicating transparency. Here, for example, 8-bit image data "oooo oooo" is stored in the data register 26a, and the comparator 24a
Suppose that a determination signal of H level (1'') is output when the values match, then the H level (``'
1") is obtained. Comparators 24b to 2
4n similarly compares the image data of each of the image memories 20b to 2On with the image data of each of the data registers 26b to 26n. In this way, the comparator 24
The n systems of discrimination signals output from each of a to 24n are supplied to the priority memory 27.

The second memory, the priority memory 27, is the fifth memory.
Like the illustrated image memory, this memory has a dual boat structure that can be accessed in a time-division manner using two systems of addresses.

That is, a control signal is sent from the computer system 21 via the pass line 22.

It is supplied with an address and priority data (selection data) and can rewrite the priority data, and except when writing, the comparators 24a to 24a.
Priority data (selection data) is read out using n systems of discrimination signals from each of the 24n as an address. Therefore, this priority memory is required to have a capacity of at least 2T+ addresses and at least n bits of priority data per address.

Here, when there are four image memories 20a to 2On (n=4), the determination signal of the comparator 24a is the third address ADR3 (LSB), and the determination signal of the comparator 24n is the third address ADR3 (MSB). The address “0” represented by 4 bits of the 0th to 3rd addresses
” to address “15”, the priority memory 27 stores the 0th data DATA0 (
It is assumed that priority data in which only one of the four bits from DATA3 (LSB) to third data DATA3 (MSB) is set to "1" is read out.

In the priority data (selection data) shown in FIG. 6, a value of "1" indicates output of image data, and a value of "0" indicates prohibition of output of image data.
The image data from a has the lowest priority, and the image data from image memory 2
Image data from 0n has the highest priority.

In other words, address "0" is the comparator image memory 20a.
This is a case where all the image data from ~2On is opaque,
Address "1" is when only the image data in the image memory 20a is transparent, and address "3" is when the image data in the image memory 20a, 20a is transparent.
Each case where the image data of b is transparent is shown. Furthermore, the priority data of each address "0" to "7" is the third data DATA3 corresponding to the image memory 2On.
only is set to the value “1”.

This 4-bit priority data is stored in the latch circuit (
(second buffer means) 28;

The latch circuit 28 performs latching at the rising timing of the clock signal supplied from the clock and synchronization signal generator 23. The latch circuit latches the 0th data (LSB) and the driver circuit 25a.

The first data is supplied to the latch and driver circuit 25b, and the third data (MSB) is similarly supplied to the latch and driver circuit 25n as an output control signal.

A clock signal from the clock and synchronization signal generator 23 is supplied to each of the latch and driver circuits 25a to 25n, and an H level (="1") output control signal of the latch and driver circuits 25a to 25n is supplied. The one shown in FIG. 1 latches the image data from each of the image memories 20a to 2On at the rising timing of the clock signal.

In addition, the output parts of the latch and driver circuits 25a to 25n are tri-stated, and only those to which an output control signal of value 1 (111, that is, H level) is supplied from the latch circuit 28 output image data. , the other latch and driver circuits have their output terminals set to high impedance.Latch and driver circuits 25a to 25n
Each output line is connected to a single display data bus 29. A wired or is being used.

As a result, the image data read from the negative image memory among the image memories 20a to 20n is transferred to the display data bus 2.
9, a video signal is generated from this output image data, and a composite image as shown in FIG. 1(B) is displayed on the monitor (
(not shown).

Incidentally, the clock signal output from the clock and synchronization signal generator 23 has a waveform as shown in FIG. 7(A). Each of the image memories 20a to 2On is output at a timing slightly delayed from the rising timing of the clock signal as shown in FIG. 7(B).
As shown in the figure, the i-th (i is any positive integer) and i+1-th image data are sequentially read out. Comparator 24a~
24n generates and outputs a discrimination signal for the i-th and i+1-th image data at a timing slightly delayed from the rising timing of the clock signal, as shown in FIG. 7(C). The priority memory 27, which is accessed by the output discrimination signals of the comparators 24a to 24n, sets the priority values for the i-th and i+1-th image data at a timing slightly delayed from the output timing of the discrimination signals, as shown in FIG. 7(D). Output data. Furthermore, the latch circuit 28 latches and outputs the output control signal at the rising timing of the clock signal shown in FIG. 7(E). Therefore, as shown in FIG. 7(F), the latch and driver circuits 25a to 25n, which output at the rising timing of the clock signal, are delayed by approximately one clock cycle from the image data (i+1st) output from the image memories 20a to 2On. The image data (i-th) is output at the specified timing.

In other words, the readout time for one pixel of image data is 10 on.
sec, the comparators 24a to 24n.

Priority memory 27. It is good if the processing time of each latch circuit 28 is within approximately 100 nsec (because there is more time than before, the priority memory 27
It becomes possible to generate an output control signal by software as shown in FIG. Further, since the priority memory 27 is used, the priority data of each image memory 20a to 20n can be changed by rewriting the priority data, increasing the degree of freedom of the system. Furthermore, the data selector, which has a complicated structure as in the prior art, can be removed, and the circuit structure becomes simpler.

Note that two pieces of image data are stored in each of the data registers 26a to 26n, and the two image data from the image memories 20a to 2On are stored in the comparators 24a to 24n, respectively.
image data of the image memories 20a to 2On.
A discrimination signal indicating transparency (or opacity) may be generated when the image data read from each has a value within a predetermined range. Furthermore, a tag bit (T
AG BIT), the data register 26a~
Each of the data registers 26a to 26n and the comparators 24a to 24n may have a 1-bit configuration, and if the content is fixed such that when the tag pit is "'1", it indicates transparency, the data registers 26a to 26n and the comparators 24a to 24n are
It is sufficient to provide a decoder instead of 24n.

Note that if the priority order of the image memories 20a to 2On is fixed to one or more types, a ROM can be used as the priority memory 27. For example, if there are two types of priorities, select the priority pattern based on the MSB of the address, and each address has n
A ROM with a storage capacity of bits is used.

Effects of the Invention As described above, the image storage device of the present invention is configured with only a single data bus for n sets of memories, and can superimpose each pixel, and the image memory can be read from the first memory. Sufficient time for one cycle of the clock signal is allowed between the output from the first buffer means and the selection data read from the second memory. It is possible to change the priority contents of n sets of image memories, increasing the confidence of the system, eliminating the need for complex hardware logic circuits, and using a single data bus even when the number of superimposed layers increases. It has the advantage of simplifying the circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of one embodiment of the device of the present invention, and FIG.
3 is a block diagram of an example of a conventional device, FIG. 4 is a circuit diagram of an example of a partial circuit of the device shown in FIG. 3, and FIG. 1 is a detailed block system diagram of an embodiment of a partial circuit of the device shown in FIG. FIG. 3 is a diagram for explaining the operation timing of one embodiment of the apparatus shown in the first figure. 20a to 2On... Image memory, 21... Computer system, 22... Pass line, 23... Clock and four signal generators, 24a to 24n... Comparators, 25a to 25n... Latch and driver circuit, 26a-26n...data register, 27...
Priority memory, 28... latch circuit, 29
...Display data bus. Patent applicant Victor Company of Japan Co., Ltd. Figure 3 Figure 4 n Figure 6 Figure 7

Claims (1)

[Claims] n sets of first memories storing n sets of digital image data (n is an integer of 2 or more); and n sets of image data read out from the n sets of first memories at the cycle of a clock signal. n sets of buffer means that hold one period of the clock signal and output to a single data bus common to the n sets of first memories according to the output control signal; and whether each of the n sets of image data is transparent or not. n sets of discrimination means for discriminating opacity and generating n sets of discrimination signals; and n bit selection data for selecting one of the n sets of image data according to the n sets of discrimination signals. a second memory for reading the n-bit selection data for one period of the clock signal, a second buffer that generates n sets of output control signals and supplies them to each of the n sets of first buffer means. An image storage device comprising: means.