JPH02171868A - Storage device - Google Patents

Abstract

PURPOSE:To arbitrarily set a starting address, which is generated by an internal address generator, by providing a register to set an arbitrary value from an external part and connecting an output from the register to the load value input of a counter. CONSTITUTION:When a register control signal is impressed to a writing address set register 1, register input values LR1-LRn are latched by the register 1. Next, when a write control signal is impressed, a data input controller 2 is operated and an input data buffer 3 is operated by a signal which is generated by the controller 2. Then, a digital video signal is latched by the input data buffer 3. Further, the signal generated by the controller 2 is inputted to the load input of the register 1 and the set values LR1-LRn of the register 1 are set as starting addresses IA1-IAn of an address generator 4. Thus, the value of the register 1 set from the external part is read as the initial value of the generator 4 and the starting value of the internal address generated by the generator 4 can be set to the arbitrary value.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a storage device used for storing digital video signals.

2. Description of the Related Art In recent years, as video equipment has become increasingly digital, storage devices have come into use to handle digital video signals. When handling digital video signals, data needs to be accessed serially at high speed rather than randomly. Therefore, there is a demand for a dedicated storage device with specifications that are easily compatible with digital video signals.

A conventional storage device will be explained below.

FIG. 2 is a block diagram of a conventional storage device. 11 is a data input control device, 12 is an input data buffer, 13
is a write address generator, 14 is an address decoder,
15 is a memory cell array, 16 is a data output control device,
17 is a read address generator, and 18 is an output data buffer.

The operation of the storage device configured in this way will be explained.

First, when a write control signal is applied, the data input control bag f! for storing data is applied. Ill is activated. next,
The input data buffer 12 is activated by the signal generated by the data input control device 11, and the digitized video signal is latched into the input data buffer 12. Further, the write address generating device 13 is activated by a signal generated by the data input control device tll, and internally generates addresses IA, .about.IA, of memory cells to which data is to be written. The write address generator 13 resets the internally generated address to address 0 by receiving a reset signal. The address generated by write address generator 13 is input to address decoder 14, which selects which memory cell in memory cell array 15 is to store data. Then, the digital video signal latched in the input data buffer 712 is written into the selected memory cell. Further, the write address generating device 13 is constituted by a counter, and increases the address by one each time a signal generated by the data manual control device 11 is input to the clock input. This allows the digital video signals to be stored in memory cells at consecutive addresses without having to manage the addresses from the outside.

Further, when a read control signal is applied, a data output control device 16 for reading out stored data is activated. A read address generator 17 is activated by a signal generated by the data output controller 16, and internally generates addresses OA+ to OA of memory cells from which data is to be read. The read address generating device 17 resets the internally generated address to address ○ when the reset signal 2 is input. The address generated by the read address generator 17 is input to an address decoder to select a certain memory cell in the memory cell array. A signal generated by the data output controller 16 causes the output data buffer 18 to operate,
The data of the selected memory cell is sent to output data buffer 1.
8 and read out as output data. The read address generating device 17 is constituted by a counter, and increases the address by one each time a signal generated by the data input control device 11 is inputted to the clock. This allows you to manage addresses from outside (
Digital video signals can be sequentially read from memory cells at consecutive addresses.

Problems to be Solved by the Invention However, in the conventional configuration described above, the reset value of each address generator that generates a write address or a read address is fixed to a certain address, so access cannot be started from an arbitrary address.

Further, there are the following problems when using the conventional semiconductor memory device and handling digital video signals due to the above-mentioned problems.

Conventional storage devices have difficulty supporting the various video signal processing functions that have recently become highly desired as functions of digital televisions or digital video tape recorders. - An example is a function that enlarges and displays a portion of an image (hereinafter referred to as a zoom function).

Figure 3 is an outline diagram of the zoom function, (a) is the original movie, (
b) is a partially enlarged image. Each coordinate represents the horizontal and vertical coordinates when the video signal is digitized.

First, in Figure 3(a) the digital video signal is (0, O) ~ (
0,yo), (1,0)~(1,yo)---(χ
0.0) to (χo, yo) in the order of coordinates in a conventional storage device. Next, sit in Figure 3 (a)! M! (χS.

The coordinates (7m', ys') of the rectangular part whose vertices are ym) and (χEl yE) are shown in Fig. 3(b).
, (χε', y[I') to be enlarged and output to the size of a rectangle with vertices, which is impossible in conventional storage devices because the initial value of the read address is fixed to a certain value.

In addition, when repeating storage and readout of digital video signals in the horizontal direction, the coordinates (0, ys) in Figure 3 (a)
The data are sequentially read out from the coordinates (χ5'
* When the coordinates are the same as Vs'), the memorized third
Data at the coordinates (χs, Ys) in Figure (a) must be read out. To read the data at the coordinates (χs, 3/s), after resetting the address, repeat the process several times until the address generated by the read address generator is counted as the address that stores the data at the coordinates (χg, Vs). It requires gummy read cycles and is not possible to select arbitrary expansion areas.

The present invention solves the above-mentioned conventional problems, and provides a storage device in which an access address is generated from an internal address generator using a counter, and the initial value of the generated address can be set to an arbitrary address. The purpose is to provide.

Means for Solving the Problems In order to achieve this object, the storage device of the present invention connects the output from the register to the load value input of the non-counter that constitutes the internal address generator, and connects the output from the register to the load value input of the non-counter that constitutes the internal address generator. It has a configuration for setting values.

Operation: With this configuration, the value of the register set from the outside can be read as the initial value of the internal address generator, and the starting value of the internal address generated by the internal address generator can be set to an arbitrary value.

Example FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention.

1 is a write address setting register, 2 is a data manual control device, 3 is an input data buffer, 4 is a write address generator, 5 is an address decoder, 6 is a memory cell array, 7 is a read address setting register, 8 is a data output control device , 9 is a read address generator, and 10 is an output data buffer.

The operation of the storage device of this embodiment configured as described above will be explained.

First, when a register ho control signal is applied to the write address setting register 1, register input values IR+ to IR are latched into the write address setting register l. next,
Application of the write control signal activates the data input control device 2 for storing data. Data input control device 2
The input data buffer 3 is activated by the generated signal,
The digital video signal is latched into this manual data buffer 3. Further, the signal generated by the data input control device 2 is input to the load input of the write address setting register 1, and the set value IR+~ of the write address setting register 1 is input to the load input of the write address setting register 1.
IRn is the start address IA of the write address generator 4
+”lAo. The address generated by the write address generator 4 is input to the address decoder 5, which selects which memory cell in the memory cell array 6 is to store data. The digital video signal latched in is written into the selected memory cell.The write address generator 4 is composed of a counter, and the register is input every time the signal generated from the data input controller 2 is input to the clock input. The address is incremented by one from the start address set by the setting value.This allows you to set an arbitrary address as the start address and manage the address from the outside. It can be memorized.

The above is the operation when storing a digital video signal in the storage device of the present invention. The following operations are the same when reading digital video signals stored in the storage device of the present invention (first
This will be explained with reference to the figures.

First, when a register control signal is applied, the register input value O
L, ~OLn are latched in the read address setting register 7. Next, when a read control signal is applied, the data output control device 8, which generates a signal for reading the stored data, is activated. The signal generated by the data output control device 8 is input to the load input of the read address setting register 7, and the set values OR1 to O of the read address setting register 7 are input to the load input of the read address setting register 7.
R.

is the start address OA r of the read address generator 9
OA, is set as closing. The address generated by the read address generator 9 is input to an address decoder to select a certain memory cell in the memory cell array. Furthermore, the output data buffer 10 is activated by a signal generated by the data output control device 8, and the data of the selected memory cell is temporarily latched in the output data buffer 10 and read out as output data. The read address generating device 9 is constituted by a counter, and each time the signal generated from the data input control device 2 is inputted to the clock input, the read address generating device 9 increments one address from the start address set by the register setting value. As a result, digital video signals can be sequentially read from memory cells at consecutive addresses using an arbitrary address as a starting address without managing the addresses from the outside.

Next, an explanation will be given of an operation when realizing a zoom function using an embodiment of the present invention.

The method of storing digital video signals is similar to that of conventional storage devices. When reading the stored data, write the initial value of the read address generation value M9 for the data at the coordinates (0, 0) to (χ's-+, 3/s') in Figure 3(a) and generate the address. The initial value is set to be the same as that of the device 4, and data is sequentially read out. Next, after setting the address where the data of the coordinates (χs, Ys> in FIG. 3(a) are stored in the read address setting register 7, the coordinates (χs', Ys> in FIG. 3(b) are stored.
If the counter of the read address generation value c9 is initialized before reading at 3's'), the coordinates (χs, V
The data of s) is the coordinate (χ@'*'!s' in Fig. 3(b)
> is read out. Below, in the same way, the coordinates (χg
'++, ys'), (χ5yg'), (χg'+
When reading data to iYi+'), it is sufficient to set the value of the read address setting register 7 in advance, initialize the counter, and then read the data. The zoom function can be realized by the above operation.

As described above, according to this embodiment, the output from the register is connected to the load value input of the counter that constitutes the internal address generator, and by setting an arbitrary value from the outside to this register, each of the internal The start address of the write address or read address generated by the address generator can be set to any value.

Effects of the Invention According to the present invention, by providing a register that can set an arbitrary value from the outside and connecting the output from the register to the load value input of the counter, the internal address generation configured by the counter is performed. The start address generated by the device can be set arbitrarily, and an excellent storage device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional storage device, and FIG. 3 is a schematic diagram of the zoom function. 1...Write address setting register, 2...
. . . data input control device, 3 . . . input data buffer, 4 . . . write address generator,
5...Address decoder, 6...Memory cell array, 7...Read address setting register, 8...Data output control device, 9...
...Read address generator, 10...Output data buffer.

Claims (1)

[Claims] 1. A storage device comprising: an internal address generator constituted by a counter; a register whose output is connected to an initial value input of the counter; and means for externally setting the value of the register.