JPH03136585A - Picture memory control circuit - Google Patents

Abstract

PURPOSE:To realize the operation with no disturbance on a reproduced pattern at on/off of a frame still function by activating/inactivating the frame still function synchronously with the pulse of frame period. CONSTITUTION:An inverter 51, AND circuits 52, 53, a flip-flop 54, an inverter 57, and a selector 58 apply write readout for frame still operation to a field memory when a frame still function is set to constitute a 2nd control means to apply normal reproduction when the frame still function is reset. A memory still command, an ODD/EVEN signal and an output 0 of a decoder 56 are synchronized to generate FWMSTOP signal. Then the frame still function is realized by only the addition of the hardware comprising the inverter 51, the AND circuits 52, 53, the flip-flop 54, the inverter 57, and the selector 58.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an image memory control circuit used in a VTR (video tape recorder) or the like having memory for a plurality of fields.

(Prior Art) The memory built into conventional business VTRs is for time axis correction and generally has a capacity of about several dozen lines.

Furthermore, although some consumer VTRs have a built-in field memory, the capacity is about one field, and there are almost no examples of VTRs having a capacity of several fields.

However, due to the improvement in the degree of integration of semiconductor memory, for example,
There are also VTRs that are designed to have memory for several fields, such as the high-definition VTR format that uses a /2 index cassette.

In such a VTR, various functions can be added by using the field memory of the playback circuit without having a special memory for special playback.

By the way, when implementing the memory frame still function on a VTR that has memory for several fields, if the memory frame is turned on and off asynchronously, the memory still operation will be entered in the middle of writing to a certain field memory, and the rewriting will be interrupted. A problem arises in which the still image is mixed with the previous image.

Therefore, the memory still is turned on and off in synchronization with the field memory switching timing that is synchronized with the vertical synchronization pulse.
It is conceivable to turn it off. However, in this case, a problem arises in that the sequence of the odd and even fields is disrupted when the memory still is turned on and off, resulting in a playback screen that is unstable.

In addition, especially high-definition V using a 172-inch cassette
In the case of the TR format, the color signals in the field memory are arranged line-sequentially, and the addresses of the color difference signals are swapped between odd and even fields, so when the memory still is turned on and off, there is only a problem with the sequence of the field arrangement. In addition, the color difference signals recorded line-sequentially are also misaligned, resulting in a problem that the color signals on the playback screen are not reproduced correctly.

(Problem to be solved by the invention) As mentioned above, a VTR having memory for multiple fields
In particular, in the case of a high-definition VTR format using a 1/2-inch cassette, due to deviations in the sequence of odd and even fields and deviations in the arrangement of color difference signals when the frame still function is turned on and off by memory, There was a problem in that the playback screen was distorted.

Therefore, the present invention is aimed at eliminating the above-mentioned problems. In a VTR with memory equivalent to the yield,
It is an object of the present invention to provide an image memory control circuit that can realize an operation with no disturbance of the playback screen when the frame still function is turned on or off.

[Structure of the Invention (Means for Solving the Problems) The present invention has a frame still function that includes a plurality of field memories that store image data in units of fields, and that reproduces frame still image data using these field memories. an image memory control circuit configured to have a frame, the first control means sequentially accessing the plurality of field memories for loading and reading image data during normal playback; When the methyl function is turned on, the sequential writing and reading access of the plurality of field memories by the first control means is stopped in synchronization with the pulse of the frame period, and the image data for two fields stored immediately before the stopping is stopped. In order to reproduce the read frame still image data, read access is performed alternately to the two field memories.When the frame still function is off, the frames of the two field memories are accessed in synchronization with the pulse of the frame period. The apparatus is characterized by comprising a second control means for causing a transition from a still operation to a sequential access operation during normal playback by the first control means.

(Function) According to the present invention, during normal reproduction, the first control means sequentially accesses a plurality of field memories for writing and reading, and performs time axis correction, etc. on input image data. It can be processed and output. Further, the frame still function is turned on and off in synchronization with the pulse of the frame period (for example, in synchronization with the rising edge of the pulse). Therefore, when the frame still function is turned on, the operation by the first control means is stopped in synchronization with the pulse of the frame period, and image data for two fields before the stop is read out alternately from the two field memories. , frame still image data can be played back. At this time, reading is performed, and input data is written to field memories other than the other two field memories. Further, when the frame still function is turned off, the frame methyl operation can be shifted to the sequential operation during normal playback by the first control means in synchronization with the pulse of the frame period. In other words, the frame still function is turned on and off in synchronization with the pulse of the frame period, so when attempting to provide a frame still function using multiple field memories as described in this specification, , frame-by-frame still operation using a pair of odd and even fields can always be performed without causing any jitter on the playback screen. Furthermore, even in formats such as high-definition VTRs that use 1/2-inch cassettes, where the color signals in the field memory are line-sequential, and where the addresses of the color difference signals are switched between odd and even fields, when the memory still is turned on, When turned off, it is possible to operate without any disturbance in the playback screen.

(Example) Examples will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an image memory control circuit according to an embodiment of the present invention.

The embodiment shown in this figure consists of three field memories 1.2
．． This is an example of a configuration having 3. These three field memories 1.2.3 are supplied with digitized image data as input, and writing of the input data to each field memory 1.2.3 is controlled by a field memory write control circuit 4. Ru. Further, reading of output data from each field memory 1.2.3 is controlled by a field memory read control circuit 5.

That is, the write selection for each field memory 1.2.3 is determined by the write selection information ELO, WS from the circuit 4.
The readout selection is performed by ELl and WSEL2, and readout selection signals R3ELO and R3E from the circuit 5 are used.
Performed by L1, R3E 12. During normal VTR playback, writing and reading are sequentially switched to and from the field memories 1, 2, 3, and processing such as time axis correction is performed. Also, during memorization, a write stop signal is generated by the field memory read control circuit 5 based on the odd/even field signal (hereinafter referred to as ODD/EV [N signal) which is a reproduction frame pulse, the memory still command, and the O output of the decoder 56. (FHWSTOP) stops the sequential old writing control of the field memory write control circuit 4, and retrieves still data output from the field memory whose writing has been stopped under the control of the field memory read control circuit 5. It is composed of

The field memory read control circuit 5 includes an ODD.
/EVEN signal, vertical synchronization pulse (VD), and memory still command are supplied, and the read selection signal R3ELO is generated based on these signals.

R3EL1. R3EL2 and write stop signal (FH
14STOP) and output it. The field memory read control circuit is configured as follows.

The memory still command, the ODD/EVEN signal, and the 0 output signal of the decoder 56 are input to the 3-person AND circuit 52, while the signal obtained by inverting the memory still command by the inverter 51, the ODD/EVEN signal, and the 0 output signal of the decoder 56 are input to the 3-person AND circuit 52. It is input to the human input circuit 53. AND circuit 5
The output of 2 is the set input terminal (S) of the flip-flop 54.
and the output of the AND circuit 53 is input to the flip-flop 5.
A write stop signal (FHWSTOP) is output from the output terminal (Q) of the flip-flop 54 when the memory is still still. On the other hand, the vertical synchronization pulse (vO) is input to the clock input terminal of the ternary counter 55, and the output terminal (QA, QB) of the counter 55 is input to the clock input terminal of the ternary counter 55.
) (corresponding to the output terminals Q^, QB, 3
Logic outputs of the type 00, 10.01 are obtained) are applied to the inputs A, B of the decoder 56. In the decoder 56,
Three scale inputs (00, 10
, 01), output terminals 0 and 1°2 are sequentially set to high level "1". In addition, when the output of the output end 2 of the decoder 56 becomes °゛1'', the counter 55 is cleared (CLR).
Since the counter 55 is configured to start counting again after that, the counter 55 constitutes a ternary counter. The output that sequentially sets each output terminal (0, 1, 2) of the decoder 56 to "1°" in a vertical period (i.e., field period) is supplied to the input terminals (AO, AI, A2) of the selector 58. The selector 58 switches the A input terminal (AO1Δ1.A2) and the 8 input terminals (BO, B1, B2) by the select signal supplied to the select terminal (S) and connects them to the output terminals (YO, Yl, Y2>). The input terminals (AO1Δ1, A2) are always connected to the output terminals (YO, Yl, Y2), and when a select signal is given, the 8 input terminals (Bo, 81, 82)
) is the output terminal (YO, Yl.

Y2). The input terminal BO of the selector 58 is input with 0/EVEN signal, the input terminal B1 is input with a signal obtained by inverting the ODD/EVEN signal by the inverter 57, and the input IB2 is a ground level signal (GNI). Enter. Then, a read selection signal R is output from the output terminal (YO, Yl, Y2) of the selector 58.
It is designed to output 3ELO, R3ELI, and R3EL2.

In the circuit shown in FIG. 1, the field memory write control circuit 4, the ternary counter 55, and the decoder 56 constitute a first control means for performing sequential write and read operations on the field memory during normal playback. are doing. Furthermore, an inverter 51 and an AND circuit 52 .
53, a Noritsubu flop 54, an inverter 57,
The selector 58 constitutes a second control means that causes the field memory to perform writing and reading for frame still operation when the frame still function is on, and performs normal playback operation when the frame still function is off. . This second control means is a feature of the embodiment of the present invention.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

In FIG. 2, (a) shows each period of an even field (E) and an odd field (0).

(b) shows vertical synchronizing pulses VD that exist corresponding to the divisions of each field and period. (C) shows an ODD/EVEN signal q, which is a reproduction frame pulse that is l 11I in an even field period and "0" in an odd field period. (d), (e), and m indicate each output 0.1.2 of the decoder 56. (0) is the memory still command, (h) is the field memory write stop signal (
rHWsTOP). (i) , (j)
, (k) is between write selection signals 5ELO, WSELI
JSEL2 is shown. (1) , un) , (
n) are read selection signals R8ELO, R8ELI, R
8EL2 is shown. During normal playback, the memory still command is not input, so the Noritsubu flop 5
Field memory write stop No. 15 (
FHWSTOP) is "O", and in this state, the field memory write control circuit 4 sequentially sends write selection signals -8[1, 0, WSELl, WSEL2 to each field memory 1, 2.3 every field period.
is given, and the input data is updated sequentially. At this time, the FHWSTOP signal “0” is set to selector 5.
8 select terminals (S), thereby causing the selector 58 to select six inputs (AO, AI, A2). During normal reproduction, the vertical synchronizing pulse VD is supplied to the output terminal of the ternary counter 55, and the output of the counter 55 is decoded by the decoder 56.
Each output 0, 1.2 is input to the selector 58 (AOA
l, A2) through the read selection signal R8ELO, R8
ELIR3EL2 becomes field memory 1.2.3
will be accessed sequentially. Therefore,
During normal playback, (d) and (e) are shown in Figure 2.
.

Each output of the decoder 50 of (') 0.1.2, and (1).

(1), (n) each read selection signal R8ELO,
R8ELI and R3EL2 match.

Here, when the memory still command shown in FIG. 2 (Q) is input, the AND circuits 52 and 53
4, (c) (7) ODD/EVEN (i) In synchronization with the rising edge of (7) and the rising edge of the decoder output O in (d), the output of the flip 70 knob 54, that is, FHWSTO
The P signal becomes high level "1". As a result, the field memory write control circuit 4 writes data to each field memory 1.
, 2.3, the field memory 3 In addition, as the FHWSTOP signal becomes ``1'', the selector 58 selects the B inputs (BO, Bl,
Select B2). B input (BO, Bl) is ODD/E
VEN (No. 5 and its inverted signal, 8-man power B
Since read selection signals R3ELO, R3EL1 . R3EL2 is shown in Figure 2 (
+), (Ill).

The result is as shown in (n). Read selection signal R3ELO
Since R3ELI alternately goes to the high level "1" for each field, the field memories 1.2, which are in the write-stopped state, are alternately accessed.

This access operation causes the frame still operation by field memory 1 and field memory 2 to continue until the memory methyl command is released.

When the memory still command goes low level, ODD/
In synchronization with the rise of the EVEN signal and the rise of the output 0 of the decoder 56, the FHWSTOP signal becomes low level. This cancels the memory still command and returns to the sequential access mode for the field memories 1, 2, and 3 during normal playback.

As described above, in this embodiment, the FHWSTOP signal is generated by synchronizing the memory still command, the ODD/EV[:N signal, and the output O of the decoder 56.

The frame still function is realized only by adding hardware such as an inverter 51, AND circuits 52 and 53, a flip-flop 54, an inverter 57, and a selector 58.

Although the above embodiment describes an image memory control circuit in a VTR, the present invention is not limited to VTRs, and can be applied to devices that perform digital image processing (for example, digital televisions, personal computers, electronic cameras, etc.). It is possible.

[Effects of the Invention] As described above, according to the present invention, for example, in a VTR (especially a high-definition VTR using a 1/2-inch cassette) that has memory for multiple fields, with only a very small addition of hardware, It becomes possible to add a frame methyl function.

Moreover, since the still function is turned on and off in synchronization with the pulse of the frame period, there is no disturbance in the playback screen caused by misalignment of odd and even fields or color difference signals. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an image memory control circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. 1.2.3...Field memory, 4...Field memory write control circuit, 51.5
7... Inverter, 52.53... AND circuit, 54... Flip-flop, 55... Ternary counter, 56... Decoder, 58...
··selector. 52

Claims (1)

[Scope of Claims] An image memory control circuit comprising a plurality of field memories for storing image data in units of fields, and configured to have a frame still function for reproducing frame still image data using these field memories. a first control means for sequentially writing and reading image data to and from the plurality of field memories during normal playback; , the sequential writing and reading accesses of the plurality of field memories by the first control means are stopped, two fields of image data stored immediately before the stop are read out, and the two field memories are read out to reproduce the frame still image data. On the other hand, when the frame still function is off, the frame still operation of the two field memories is changed from the frame still operation of the two field memories during normal playback by the first control means in synchronization with the pulse of the frame period when the frame still function is off. An image memory control circuit comprising: second control means for shifting to sequential access operation.