JP3158561B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device ,
More specifically, the present invention relates to a data processing device that processes data having different data rates such as video and audio.

[0002]

2. Description of the Related Art A digital magnetic recording / reproducing apparatus, a so-called digital video tape recorder (VTR), develops data to be recorded or reproduced data into a frame memory in order to reduce continuous errors. Interleaved or deinterleaved.

FIG. 2 is a block diagram showing a configuration of a storage circuit in a conventional digital magnetic recording apparatus. The A / D converter 12 converts a video signal input from the video input terminal 10 into a digital signal at a predetermined sampling rate.
A / D converter 16 converts an audio signal input from audio input terminal 14 into a digital signal at a predetermined sampling rate, and these digital data are
8 is sent out. The video address generation circuit 20 generates an address indicating the storage position of the video data output from the A / D converter 12, and outputs an audio address generation circuit 22.
Generates addresses indicating storage locations of audio data output from the A / D converter 16, and these addresses are sent out on an address bus 24.

The data on the data bus 18 is sent to the field memory 30 or 32 via the write switch 26.
The address on the address bus 24 is applied to the field memory 30 or 32 via the address switch 28. Field memories 30, 32
Have a storage capacity for one field, and together form a frame memory with a storage capacity for one frame.
As will be described in detail later, the switching control circuit 38 switches the write switch 26 and the address switch 28 for each field. As a result, odd (or even) field data is written to the field memory 30 and even (or odd) field data is written to the field memory 32.

[0005] In this case, the field memory 3
0 and 32 are not physically separated, and may be a memory space defined by the upper bits of the address in accordance with the frame memory. In this case, the control signals of the switches 26 and 28 are the upper bits of the address.

The data read from the memories 30 and 32 is output to an output terminal 36 via a read switch 34. The readout switch 34 is also alternately switched by the switching control circuit 38 for each field. Thus, the odd field and the even field are alternately output from the output terminal 36.

[0007] The video address generation circuit 20 applies a video reset signal to the switching control circuit 38 for each field break. The switching control circuit 38 is composed of a frequency dividing circuit using a D flip-flop, and generates a field switching control signal. By the generated field switching control signal,
Switches 26, 28 and 34 are switched for each field.

FIG. 3 shows a timing chart of FIG. 3A shows video data output from the A / D converter 12, FIG. 3B shows a video address, FIG. 3C shows a video RST signal applied to the switching control circuit 38 by the video address generation circuit 20, and FIG. (D) is a switching signal output from the switching control circuit 38.

[0009]

In the prior art, as described above, writing and reading of video data and audio data to and from the field memories 30 and 32 are switched according to the video signal, that is, for each field of the video signal. However, the audio signal is a continuous signal and has nothing to do with the video field. In addition, since the video data and the audio data have different data rates, the audio data may be lost due to the switching on a field basis.

[0010] The present invention is, de to solve such problems
The purpose is to present a data processing device .

[0011]

Means for Solving the Problems Data processing according to the present invention
The apparatus has an input unit for inputting video data and audio data, a storage unit having a plurality of memory units, and storing image data and audio data input by the input unit,
Means for generating a first switching signal for switching the memory means to which the image data is to be written among the plurality of memory means, means for generating a timing signal synchronized with audio data input by the input means, Means for generating a second switching signal for switching a memory means to which the audio data is to be written, among the plurality of memory means, according to the first switching signal and the timing signal; And a control unit for switching the memory unit to which the image data is to be written in accordance with the signal and the memory unit to which the audio data is to be written in accordance with the second switching signal.

[0012]

According to the above means, both the first and second data are
The data can be developed and read out from the memory without loss.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Components having the same functions as those in FIG. 2 are denoted by the same reference numerals. The audio address generation circuit 40 outputs an audio RST signal for each audio data number corresponding to one field, in addition to the audio address. In other words, the audio address generation circuit 40 outputs the audio RST signal at a timing close to the video RST signal. The switching control circuit 42 switches the switches 26, 28 and 34 according to the video RST signal from the video address generation circuit 20 and the audio RST signal from the audio address generation circuit 40.

In order to synchronize the switching between the video system and the audio system, the switching control circuit 42 according to the present embodiment uses the video RST signal as a reference in accordance with the audio RST signal before or after the video system switching. Changed audio system. As a result, audio data is not lost.

FIG. 4 shows a circuit configuration example of the switching control circuit 42. A video RST signal is input to the input terminal 50,
It is applied to the clock input of flip-flop 54. D
The flip-flop 54 divides the video RST signal to generate a switching signal for each field, and outputs the switching signal to the output terminal 64 as a video-based write / read switching signal.

The audio RST input to the input terminal 52
The signal is applied to the clock input of the D flip-flop 62, and the exclusive OR circuit 56 performs an exclusive OR operation on the Q output of the D flip-flop 62 and the video system switching signal (Q output of the D flip-flop 54). The inverter 58 inverts the output of the exclusive OR circuit 56, and the exclusive OR circuit 60 takes the exclusive OR of the output of the inverter 58 and the video system switching signal, and the output is input to the D input of the D flip-flop 62. Applied. These exclusive OR circuits 56,
60 and the inverter 58, the D flip-flop 6
The output of 2 is a signal synchronized with the audio RST signal and inverted similarly to the video switching signal, and is output from the output terminal 66 as an audio switching signal.

FIG. 5 shows the timing chart of FIGS. 5A shows video data output from the A / D converter 12, FIG. 5B shows a video address, FIG. 5C shows a video RST signal applied to the switching control circuit 42 by the video address generation circuit 20, and FIG. (D) is a video system switching signal, (e) is audio data output from the A / D converter 16,
(F) is an audio address, (g) is an audio RST signal applied to the switching control circuit 42 by the audio address generation circuit 40 when preceding the video RST signal, and (h) is
(G) an audio system switching signal for the audio RST signal;
(I) is the audio RST when it is behind the video RST signal
The signal (j) is an audio system switching signal for the signal (i).

In this embodiment, the field memory 3
If 0 and 32 are the address areas in the frame memory where the upper bits of the address are different, the control signal of the switch 26 corresponds to the highest bit of the video address and the control signal of the switch 28 corresponds to the highest bit of the audio address.

Although the case of video and audio has been described, the present invention can be generally applied to a case where a plurality of types of signals having different data rates are written to and read from a memory.

[0021]

As can be easily understood from the above description, according to the present invention, a plurality of types of data having different data rates such as video and audio are developed on the same memory,
It can be read without missing.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional example.

FIG. 3 is a timing chart of a conventional example.

FIG. 4 is a circuit configuration example of a switching control circuit 42 of FIG. 1;

FIG. 5 is a timing chart of the present embodiment.

[Explanation of symbols]

10: Video input terminal 12: A / D converter 14: Audio input terminal 16: A / D converter 18: Data bus
20: Video address generation circuit 22: Audio address generation circuit 24: Address bus 26: Write switch
28: Address switch 30, 32: Field switch
Memory 34: Readout switch 36: Output terminal 3
8: Switching control circuit 40: Voice address generation circuit 4
2: Switching control circuit 50: Video RST signal input terminal
52: audio RST signal input terminal 54: D flip-flop 56: exclusive OR circuit 58: inverter 6
0: Exclusive OR circuit 62: D flip-flop 6
4: Video system switching signal output terminal

Claims (1)

(57) [Claims] An input unit for inputting video data and audio data; a storage unit having a plurality of memory units for storing image data and audio data input by the input unit; A means for generating a first switching signal for switching a memory means to which the image data is to be written; a means for generating a timing signal synchronized with audio data input by the input means; and the first switching signal. Means for generating a second switching signal for switching a memory means to which the audio data is to be written, among the plurality of memory means, in accordance with the timing signal, and the image processing means in response to the first switching signal. Switching the memory means to which data is to be written, and writing the audio data in response to the second switching signal. Data processing apparatus, characterized in that it comprises a control means for switching Mbeki memory means.