JPS58195340A - Synchronism detecting circuit - Google Patents

Abstract

PURPOSE:To minimize information losses and to simplify the circuit constitution, by utilizing a digital data signal when a syncrhonizing signal is obtained with a probability, even if the synchornizing signal is not completely obtained from the digital data signal. CONSTITUTION:A synchronism detecting signal is applied to a decision by majority circuit 11 and written one by one in (N-1)-set of synchornizing memories 121-12N-1 sequentially. When the number of signals is a number M of decision by majority, the majority circuit 11 outputs a synchronism detecting signal and a switch 3 is grounded. The majority circuit 11 generates a detection output when the number of synchronizing signals is the number M(<N) of decisions by majority or over, stops disable signal and applies a synchronizing signal to an output terminal 17. A reference synchronizing signal is generated from the output at a control circuit 15 and a counter 16 and the number M of decisions by majority is changed into a smaller value M'. When the number of synchronism detecting signal is more than the number M' of decision by majority, the synchronizing signals are applied continuously, the detection-disable signal is outputted when the number is the M' or below, and the number of decisions by majority is restored to the M.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization detection path for outputting a synchronization signal ValE of a predetermined period contained therein from a digital data signal such as a digital video signal or a digital audio signal.

Conventional digital VTRs perform code conversion to prevent synchronization signal patterns from occurring [and are configured to facilitate synchronization detection, which not only results in a single circuit configuration being cumbersome and large-scale, but also causes problems during playback. During the reset period after sending a message, the digital video signal must be discarded until the synchronization detection circuit reliably detects the block synchronization signal from the reproduced digital video signal, which reduces the amount of information in the data. The loss was huge.

In view of the sticking point Fcwti, the present invention is a synchronization detection method that can minimize the loss of information amount of digital data obtained during reproduction from a digital data recording/reproducing device, etc., and has a simple and small-scale circuit configuration. The purpose is to propose a circuit.

The present invention includes a synchronization pattern detection circuit that is supplied with a digital data signal containing a synchronization signal of a predetermined period and detects its synchronization pattern, and stores the synchronization pattern * synchronization detection signal from the output circuit one by one. Synchronization detection signals from N-1 synchronous memories, a synchronous pattern detection circuit, and N-1 synchronous memories are supplied, and the number of supplied synchronous detections o1 is determined by majority decision to be 11 [M (<N) or more]. When the majority circuit outputs the synchronization signal, and the synchronization detection circuit 1611 supplied to the majority circuit when the synchronization signal is obtained from the majority circuit for the first time, the maximum possible number of synchronization detection circuits 1611 is changed to be larger than N, or the majority number is set to M. This includes a control circuit that controls the majority circuit so as to change it to a smaller value.

An embodiment in which the present invention is applied to a digital VTR will be described in detail below with reference to FIG. +1) is an input terminal to which a parallel 8-bit NRZii1 digital video signal (including a block synchronization signal of a predetermined precision) is supplied during playback in the digital VTR. The l block is 216 bits long. The reproduced digital video signal from the input terminal (1) is supplied to the data memory (2), where it is written and stored. From data memory (2) lol
The output digital video signal is transferred to the selector switch t3)
[is supplied to the output terminal (4) via []. Changeover switch (
In 3), its movable contact is connected to the output terminal (4)K, one fixed contact is connected to the output side of the data memory cage 2), and the other fixed contact is connected to W! It is grounded.

tbr and (7) are write and read address counters, respectively, the outputs of which are supplied to the data memory (2)K via the address switch (5). 0 is a reset signal generation circuit that generates a reset signal when the power is turned on, and the reset signal from this is sent to the counter (6),
Q4) and (lt9).In addition, the counter (6)
, +7) and the synchronization pattern detection circuit (
Starting from 1G [Number of stitches of clock signal when a synchronization pattern is detected '4I: Starts.

The reproduced digital video signal supplied to the input terminal (l) is written to the address determined by the counter (6) of the data memory (2). Also, this
:.

The address signal from the response counter (6) is synthesized! (8
3, a predetermined atlus number K from the constant circuit (9) is subtracted from this, and the address signal as the subtraction output is supplied to the offset address counter (7). This k is determined to be a value corresponding to the number of tumbles corresponding to the amount of delay with respect to the synchronization signal in the digital video signal supplied to the input terminal 11) of the synchronization signal from the majority circuit t1υ, which will be described later. Also, the M protruding address counter (
7) is supplied with the synchronizing signal obtained from the majority decision path aD, and the counter (7) is set.

The address signal from the synthesizer (8) at that time is taken as the start address □ of the counter (7).

The digital video signal from the input terminal (1) is supplied to the synchronization pattern detector mmα to detect the synchronization signal.

Wholesale is a 16-bit block synchronization signal lWIM pattern (including noise of the same pattern as the synchronization pattern)
is detected, and its synchronization detection signal (the hook is a 1-bit signal) is supplied to the majority circuit αυ, and N-1 synchronous memories' (therefore, the memory capacity only needs to be 1 bit) (
121) to (12N-5)K are supplied and stored one by one. αhiro provides address signals to these IWIM'(:su(121) to (12N-1)).
This is an address counter that controls these offsets and writing. Synchronized memo! J (12t) ~
(12N-1), the synchronization detection signal is extracted and supplied to the majority circuit aυ.

When the number of synchronization detection signals supplied to it is less than the majority vote MK, the majority circuit aυ outputs a synchronization detection impossible signal, and from this the contact of switch (3) is connected to the ground side fixed contact. be done.

The majority decision circuit Qυ generates a detection output when the number of synchronization detection signals from the synchronization pattern detection circuit (11 and the four rules (121) to (12N-1) becomes greater than the majority number M (<N) for the first time. , stops the generation of the synchronization detection impossible signal, and supplies the synchronization signal to the output terminal a'0.

This detection output causes [counting start and stop control circuit a- to become 1].
This control output causes a counter as a reference synchronization signal generation circuit to start counting clock signals, and from this, a reference synchronization signal (without a synchronization pattern) is generated.
is generated and supplied to the majority circuit aυ, and the majority circuit a
The majority vote M4 of υ is changed to a smaller value M/K. In addition, due to the stop of generating the synchronization detection impossible signal, the switch (
The movable contact point 3) is switched to the fixed point of the data memory +2)@, and the digital data signal from the data memory (2) is supplied to the output adder (4).

When the number of synchronization detection signals supplied to the majority circuit Uυ is greater than the changed majority number M', the synchronization signal is continuously supplied from the majority circuit aυ to the output terminal 07).

The number of synchronization detection signals manually input to the next w1aυ is the same as the above change l! When the majority voting number M' is not reached, the majority voting circuit Ql) outputs a synchronization detection failure signal,
As a result, counting start/stop control - path αcJ is controlled,
1ht Stop the generation of the reference synchronization signal from the JIA synchronization signal generation circuit ae [majority number of majority circuit Qυ & MK
At the same time, switch the movable contact of the selector switch (3) that was on the data memory (2) side to the ground side.

□ I can't get a digital video signal at the output terminal (4)5
Niichi 1'6. In the above description, a digital video signal is used as the digital data signal, but other digital data signals such as a digital audio signal are also possible.

According to the above-mentioned synchronization detection circuit of the present invention, even if a complete synchronization signal cannot be obtained from the digital data signal obtained during reproduction from a digital data recording/reproduction device, etc., it can be detected with a probability higher than a certain probability. When a synchronization signal is obtained, the digital data signal is utilized, so that the information loss of digital data can be kept as small as possible, and the single circuit configuration is simple and small-scale.

[Brief explanation of the drawing]

The figure is a block diagram showing one implementation of the present invention f'1lt-1, (2) is a data memo 9. (6) and (7) are write and offset address counters, respectively, Ql) is a synchronization pattern detection circuit, aυ is a majority decision circuit, (IJl) to (1
2N) is - period memory, aJ is reset: tto number generation circuit, (1$ is counting work □0...: □'ass* a□
, □□11'i.

Claims (1)

[Claims] An iWI period pattern detection circuit to which a digital signal including a synchronization signal of a predetermined cycle is supplied and the synchronization pattern is detected, and a synchronization detection signal from the synchronization pattern detection circuit is N-1 synchronous memories that are individually updated;
The synchronization detection signals from the synchronization pattern detection circuit and the N-1m synchronization memories are supplied, and when the number of the supplied synchronization detection signals is greater than or equal to the majority decision number M (<N), a majority decision is made to output a 1tfl1 period signal. circuit, and when a synchronization signal is obtained from the majority circuit for the first time, change 1 to the maximum possible number of synchronization detection (i-8) supplied to the majority circuit, or change the maximum possible number of i-8 from the above M to the majority circuit. (2) A control circuit for controlling the majority circuit so as to change the number to 1%;