JP2687428B2 - Image memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a time base collector, a frame synchronizer, other image processing devices, an image memory device used in a VTR (video tape recorder), a television receiver, or the like. In particular, the present invention relates to a so-called dual port type image memory device having an input buffer unit and an output buffer unit.

[Summary of the Invention]

The present invention has an input buffer means to which a video signal is supplied, a memory means, and an output buffer means for outputting the memory means. Based on a write transfer signal and a read transfer signal, the buffer means and the memory means are connected to each other. In the image memory device in which the input / output control is performed, by providing an overtaking detection circuit that detects an overtaking by the order of the write transfer signal and the read transfer signal and the match of the write address and the read address, the disorder of the demodulated image is prevented. To prevent it.

[Conventional technology]

As an image memory device, a frame memory has been proposed which includes an input / output buffer and stores one frame of image information. This image memory device is provided with a memory cell array in which cells are arranged in a matrix, and one line of image data (for example, 960 dots) is stored in each word direction.

By the way, as an input / output buffer, a plurality of buffers each having a capacity smaller than the number of image information corresponding to one line are provided,
There is an image memory device that transfers data between each buffer and a memory cell array while switching these. For example, such an image memory device is described in JP-A-62-256300. In such an image memory device, the transfer between the input buffer and the memory cell array is controlled by the write transfer signal T _W , and the transfer between the output buffer and the memory cell array is controlled by the read transfer signal T _R. That is, the pulses of the transfer signals T _W and T _R are generated for each line according to the number of divided buffers, and the input / output transfer is performed at that timing. These transfer signals T _W and T _R are generated inside the memory device by a required clear signal or the like, and are not supplied as signals from the outside.

It is known that some image memory devices perform writing and reading in parallel with respect to the memory cell array, and do not synchronize the write transfer signal T _W and the read transfer signal T _R. In the image memory device that generates the asynchronous transfer signals T _W and T _R , the cycle of the write transfer signal T _W is longer than the cycle of the read transfer signal T _R. Then, the transfer signal asynchronous as shown in FIG. 6 T _W, an image memory apparatus for generating T _R, the respective transfer signal T _W, has arisen when the timing of T _R match. The timing is indicated by time Tc in FIG. Thus each pulse T _W , T
Malfunctions generally occur in memory devices when _R is sent at the same time. Therefore, in the conventional image memory device, the asynchronous write transfer signal T _W and the asynchronous read transfer signal T _R are temporally shifted back and forth. In Figure 6, the read transfer signal P _R1 at time T _C temporally in front, the read transfer signal P _R2
Is shown.

[Problems to be solved by the invention]

By the way, when one of the transfer signals T _W and T _R as described above is shifted in time, if the write and read addresses match, so-called “overtaking” occurs.

FIG. 7 is an explanatory diagram of the “overtaking”, in which the solid line shows the change of the write address with respect to time and the broken line shows the change of the read address with respect to time. The cycle of the write address is longer than the cycle of the read address, and the read field N means that the data of the write field n is read. However, at the writing field n + 1, "passing" occurs at the point Pa, and at the reading field N + 1 after the point Pa at time T ₁ , the data of the field n which is the previous field before writing is read again. As a result, in the image signal transfer method in which the phase is inverted for each field, a hue error as shown in FIG. 8 occurs after "overtaking", and the demodulated image is disturbed.

As a technique for solving such a problem, the applicant of the present application has previously proposed a related technique of discriminating a hue error by using status information in data (Japanese Patent Laid-Open No. 63-63160).
−7594). However, a technique for separating the video signal and the status information is required instead of the technique using the asynchronous transfer signals T _W and T _R.

Therefore, the present invention utilizes each transfer signal T _W , T _R ,
An object of the present invention is to provide an image memory device that prevents image distortion and the like.

[Means for solving the problem]

To achieve the above object, an image memory device of the present invention is provided with an input buffer means to which a video signal is supplied, a memory means to which an output of the input buffer means is supplied, and an output of the memory means. Output buffer means,
A write transfer signal that controls the timing of supplying the output of the input buffer means to the memory means, and a read transfer signal that is asynchronous with the write transfer signal and that controls the timing of supplying the output of the memory means to the output buffer means. The control means for generating a signal, the write transfer address of the memory means to which the output of the input buffer means is written, and the read transfer address of the memory means to which the output is read to the output buffer means are respectively counted, and the write transfer is performed. Address match detection means for detecting a match between the address and the read transfer address, order determination means for detecting that either one of the write transfer signal and the read transfer signal is continuously generated, and the address match The detection means is a write transfer address. And the read transfer address are detected to coincide with each other, and when the order determining means detects that either one of the write transfer signal and the read transfer signal is continuously pulsed, an overtaking detection signal is generated. It is characterized by having an overtaking detection signal generating means.

In this invention, the structure of the memory means is DRAM, S
It doesn't matter RAM. The number of divisions of the input buffer means and the output buffer means is an integer of 1 or 2 or more and is not particularly limited. There may be a plurality of input / output buffer means. For example, as an example of the input / output buffer means, a SAM (serial accelerator memory) can be used. The image memory device according to the present invention may have a configuration capable of random access as well as serial access.

In addition, the fact that one of the pulses of the write transfer signal or the read transfer signal is repeated means that two or more pulses of the read transfer signal are generated in the time between an arbitrary pulse of the write transfer signal and the next pulse. Is continuously generated, or two or more pulses of the write transfer signal are continuously generated in the time between an arbitrary pulse of the read transfer signal and the next pulse.

[Action]

In a memory in which the write transfer signal and the read transfer signal are asynchronous, "passing" occurs when either one of the pulses of the transfer signal is repeated and the write transfer address and the read transfer address match. Therefore, by providing the overtaking detection signal generating means for detecting these, the overtaking detection is effectively performed.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

The image memory device of the present embodiment, as shown in FIG.
The memory body is composed of an input buffer 11, a memory cell array 12, an output buffer 13 and a controller circuit 14, and an overtaking detection circuit 1 surrounded by a broken line in the figure is connected to the memory body.

First, the video input signal D _IN which is serial data is input to the input buffer 11 of the memory body, which is converted into parallel data and output to the memory cell array 12. The input buffer 11 is composed of, for example, two SAMs (serial access memories). Then, for example, by the write transfer signal T _W having N ₂ pulse for each line, each SA
M is switched, and N ₁ dot data is sequentially sent to the memory cell array 12.

In the memory cell array 12, one line has N ₁ (for example, 6
The DRAM has 0) × N ₂ (for example, 16) dots of data and has a required number of lines (for example, 306). The controller circuit 14 controls the line selection and the like.

The output buffer 13 of the memory body is the memory cell array 12
Receives parallel output data from the two SAs
Outputs serially as output signal D _OUT while switching M. Signal used to switch between these two SAM is read transfer signal T _R.

The controller circuit 14 of the memory body is supplied with a required clear signal or the like and controls the memory cell array 12. In the controller circuit 14, the write transfer signal T _{W and the} read transfer signal T _R are formed. Then, each of these transfer signals T _W and T _R is used for control of transfer and, at the same time, is output to the overtaking detection circuit 1 for detecting overtaking.

The outpacing detection circuit 1 is composed of a write transfer address counter circuit 2, a read transfer address counter circuit 3, an address match detection circuit 4, an order discrimination circuit 5 and an AND circuit 6. The overtaking detection circuit 1 may be inside or outside the chip.

The write transfer address counter circuit 2 receives the write transfer signal T _{W and} counts the write transfer address. Write transfer address AD that is counted
_W consists of a vertical address such as (v, h) and a horizontal address.

Likewise read transfer address counter circuit 3, the read transfer signal T _R is inputted, the read transfer address AD
_R is counted. Read transfer address is the count AD _R also write transfer address AD _W as well as (v,
It consists of vertical address and horizontal address as shown in h).

The address match detection circuit 4 inputs the write transfer address AD _W of the write transfer address counter circuit 2 and the read transfer address AD _R of the read transfer address counter circuit 3, compares them, and when they match, , Set its output to "H" level. When they do not match, the output is set to "L" level.

The order determination circuit 5 receives the transfer signals T _W and T _R ,
The order of the pulses of the transfer signals T _W and T _R is determined. The write transfer signal T _W and the read transfer signal T _R have their pulses alternately generated in normal times without overtaking, but the order is out of order when the transfer pulses are controlled to avoid overlapping of the pulses. , One pulse is repeated. Thus any pulse of the write transfer signal T _W to the time between the next pulse, when two or more pulses of the read transfer signal T _R is generated continuously, or, any of the read transfer signals T _R By detecting the case where two or more pulses of the write transfer signal T _W occur consecutively in the time between one pulse and the next pulse, the write transfer signal T _W and the read transfer signal T _W which are asynchronous are detected. _{The operation in which R} is shifted back and forth in time is determined.

The AND circuit 6 receives the outputs from the address coincidence detection circuit 4 and the order determination circuit 5, respectively. “Overtaking” occurs when one of the transfer signals T _W and T _R as described above is repeatedly generated and the write transfer address AD _W and the read transfer address AD _R are the same address. Therefore, when the outputs of the address coincidence detection circuit 4 and the order discrimination circuit 5 are at the "H" level, it is determined that "overtaking" has occurred and the "H" level is output.

FIG. 2 shows the image memory device of this embodiment connected to the chroma inverter 22.
Is output via the chroma inverter 22, and when the "passing" is performed by the chroma inverter 22, the output signal from the overtaking detection circuit 1 controls the phase in accordance with the field. Therefore, the demodulated signal from the image memory device of the present embodiment does not have the disturbance of the removed image such as the hue shift.

Figure 3 is "overtaking" the transfer signal T _W when, T _R and the transfer address AD _W, is a time chart of the AD _R. When the pulse of the write transfer signal T _W is input at time t ₁ , the address of the write transfer address counter circuit 2 is advanced by 1, and the write transfer address AD _W is changed from (h, v−1) to (h, v).
Becomes Then, enter the pulses of the read transfer signals T _R at time t _2, the address of the read transfer address counter circuit 3 advances one, the read transfer address AD _R, (h, v
From (-1) to (h, v). Then, at this time, the respective addresses of the write transfer address AD _W and the read transfer address AD _R match each other, and the address match detection circuit 4 outputs "H" level.

After the read transfer signal T _R pulse is generated, the write transfer signal T _W is normally output from the memory body, but when passing, the same read transfer signal T _R pulse is repeatedly issued (time t ₃ ). . When such a pulse of one transfer signal is repeatedly generated, the output of the order discrimination circuit 5 becomes "H" level. Then, in the AND circuit 6,
Both of the two input signals become "H" level, and a signal indicating that overtaking has occurred is output. Then, the output signal is supplied to the chroma inverter 22 as shown in FIG. 2 to prevent the image distortion.

Next, another example of the overtaking detection circuit in the image memory device of this embodiment will be described with reference to FIGS. 4 and 5.

As shown in FIG. 4, this overtaking detection circuit includes a pair of counter circuits 41, 45 and latch circuits 42, 43, 44, 46, 47, 48.
And a pair of coincidence detection circuits 49, 50 and an OR circuit 51.

The write transfer signal T _W is clocked into the counter circuit 41 and the latch circuits 42, 47, 48. Further, the read transfer signal T _R is the clock input to the counter circuit 45 and latch circuit 46,43,44.

The output signal A ₁ of the counter circuit 41 is supplied to the latch circuits 42 and 43. The output signal A ₂ of the latch circuit 42 is supplied to the coincidence detection circuit 50. The output signal A ₃ of the latch circuit 43 is supplied to the coincidence detection circuit 49 and the latch circuit 44. The output signal A ₄ of the latch circuit 44 is supplied to the coincidence detection circuit 49. Further, the output signal B ₁ of the counter circuit 45 is supplied to the latch circuits 46 and 47. Output signal B of the latch circuit 46
₂ is supplied to the match detection circuit 49. The output signal B ₃ of the latch circuit 47 is supplied to the coincidence detection circuit 50 and the latch circuit 48. The output signal B ₄ of the latch circuit 48 is supplied to the coincidence detection circuit 50.

Then, the output signals P, Q of the coincidence detection circuits 49, 50 are
It is supplied to the OR circuit 51, and the output of the OR circuit 51 becomes the output of the overtaking detection circuit. That is, as shown in FIG. 2, for example, the chroma inverter 22 is controlled.

Next, the operation of this overtaking detection circuit will be described with reference to FIG. The output signals A _{1 to} A ₄ are applied to the data on the write transfer address AD _W side, and the output signal B ₁
.About.B ₄ is according to the read transfer address AD _R-side data.

First, from time t ₁₀ to time t ₁₃ , normal operation without “overtaking” is performed. At time t ₁₀ , the pulse of the write transfer signal T _W is input, and the counter circuit 41 advances the value of the write transfer address AD _W by one. At the same time, the latch circuit 42 latches the output signal A ₁ . That is, the output signal A ₂ of the latch circuit 42 becomes the signal one clock before the counter circuit 41. Also, at this time t ₁₀ , the latch circuit 4
7,48 also works. The latch circuits 47 and 48 are write transfer signals T
At the timing of the _W of the pulse going to latch the read transfer address AD _R. The latch circuit 48 uses the output signal B ₃ one clock before the latch circuit 47 as the output signal B ₄ .

At time t _11, the operation occurs at the read transfer signal T _R side of the system. That is, in the counter circuit 45, read transfer
The value of AD _R advances one output signal B ₂ of the latch circuit 46 becomes one clock signal before the output signal B ₁ of the counter circuit 45. The latch circuits 43 and 44 are going to latch the write transfer address AD _W at the timing of the pulses of the read transfer signals T _R. The latch circuit 44 uses the output signal A ₃ one clock before the latch circuit 43 as the output signal A ₄ .

At time t ₁₂ , the output signal A ₁ of the counter circuit 41 is (v, h)
It is assumed that At this time, the output signal of the latch circuit 42
A ₂ is one clock before (v, h-1) a and, the output signals B _3, B ₄ of the latch circuits 47 and 48 to continue to latch the read transfer address AD _R are each (v, h- 1), (v, h-
2).

Next, at time t ₁₃ , the output signal B ₁ of the counter circuit 45 is assumed to be (v, h). This means that the write transfer address AD _W and the read transfer address AD _R match. At this time, the output signal B of the latch circuit 46
₂ is (v, h-1), and the output signals A ₃ and 4 of the latch circuits 43 and 44 for latching the write transfer address AD _W are latched.
Since the output signal A ₁ is already (v, h), A ₄ becomes (v, h) and (v, h−1), respectively.

When overtaking occurs, the same transfer pulse is repeated. That is, at time t _13, it generates a pulse of the read transfer signals T _R, a pulsed read transfer signal T _R is generated again (time t _14). Then, first, the output signal B ₁ of the counter circuit 45 becomes (v, h + 1), and the output signal B ₂ of the latch circuit 46 delayed by 1 clock becomes (v, h + 1).
h). This output signal B ₂ is the read transfer address A
Input to the matching circuit 49 for referencing D _R. This time t
_{With the 14} pulses of the read transfer signal T _R , the clock input latch circuits 43 and 44 also operate. However, the output signal A of the counter circuit 43 which is the input signal of the latch circuit 43
_{In 1} there is no data change because there is no clock input after time t ₁₂ . Therefore, even if the latch circuit 43 operates at time t ₁₄ , only the same (v, h) as the previous clock (v, h) is latched again, and the output signal A ₃ of the latch circuit 43 is It remains (v, h). On the other hand, in the latch circuit 44, the data of (v, h) one clock before becomes the output signal A ₄ . Therefore, the output signals A ₃ and A ₄ of the latch circuits 43 and 44 coincide with each other due to the pulse generation at the time t ₁₄ .

Here, after time t ₁₄ , the signal A ₃ input to the matching circuit 49,
A ₄ and B ₂ all match (v, h). Signal A ₃ , A ₄
It matches to the output signal B ₂ not only means that also agreed to read transfer address AD _R for write transfer address AD _W. This match makes the match circuit
The output P of 49 becomes "H" level, which means overtaking,
It is output via the OR circuit 51. Then, the disorder of the image is corrected.

Hereinafter, the time t _15, the time t _16, ... to come to the input pulse is overtaking detecting circuit one after another, but because there is no barrage and match address pulse, the OR circuit 51 becomes "H" level Absent.

Note that when the pulses of the write transfer signal T _W are repeated, the address data of the output signals B ₃ and B ₄ of the latch circuits 47 and 48 are in symmetry, which is symmetrical with the above example. data read transfer address AD _R at this time is supplied from the latch circuit 42. And the matching circuit 50
It is determined whether or not they match, and when they match, that is, when overtaking, the output signal Q becomes "H" level, and the OR circuit 51
Will produce the required output.

As described above, in the outpacing detection circuit shown in FIG. 4, the write transfer address AD _W side uses the pulse timing of the read transfer signal T _R as a clock in the circuit configuration for detecting the address match, and the transfer address AD _R side, utilize the timing of the pulses of the write transfer signal T _W as a clock. Therefore, when one pulse is repeatedly generated, it is detected by the coincidence circuits 49 and 50 in the form of address coincidence, and a reliable "overtaking" is detected.

The image memory device of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

〔The invention's effect〕

The image memory device of the present invention is provided with the overtaking detection signal generating means that operates by the pulse of each transfer signal. Therefore, the detection of overtaking prevents the image from being disturbed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an image memory device of the present invention, FIG. 2 is a block diagram for explaining an application example thereof,
FIG. 3 is a time chart for explaining the operation at the time of overtaking, FIG. 4 is a circuit diagram showing another example of the overtaking detection circuit according to the image memory device of the present invention, and FIG. 5 is overtaking of FIG. A time chart for explaining the operation of the detection circuit, FIG. 6 is a time chart for explaining each transfer signal, FIG. 7 is an explanatory diagram for explaining overtaking, and FIG.
The figure is a schematic diagram for explaining a screen when a hue error occurs. 1 ... Overtaking detection circuit 2 ... Write transfer address counter circuit 3 ... Read transfer address counter circuit 4 ... Address match detection circuit 5 ... Sequence detection circuit

Claims (1)

(57) [Claims] 1. An input buffer means to which a video signal is supplied, a memory means to which an output of the input buffer means is supplied, an output buffer means to which an output of the memory means is supplied, and an output of the input buffer means. Control means for generating a write transfer signal for controlling the timing for supplying the memory means to the memory means, and a read transfer signal for controlling the timing for supplying the output of the memory means to the output buffer means asynchronously with the write transfer signal. And the write transfer address of the memory means to which the output of the input buffer means is written and the read transfer address of the memory means from which the output is read to the output buffer means are respectively counted, and the write transfer address and the read transfer address are counted. Address match detection method to detect that and match Stage, sequence determination means for detecting that either one of the write transfer signal and the read transfer signal is continuously pulsed, and the address matching detection means for detecting that the write transfer address and the read transfer address match. And
And an overtaking detection signal generating means for generating an overtaking detection signal when the sequence determining means detects that either one of the write transfer signal and the read transfer signal is continuously pulsed.