JPH0348518B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] In order to convert digital data in non-interlace format after image processing to interlace format for the purpose of outputting to a TV monitor, etc., a single frame memory is used and the read data to the memory is /Write is performed at the same address, and the line address is determined according to the line address stored in the previous frame. [Industrial Application Field] The present invention relates to an image signal format conversion method. Generally, non-interlaced data is output as sequence data after image processing, and in order to display the sequence data on a television monitor, it must be converted to interlace format. The present invention attempts to continuously perform this non-interlace/interlace conversion using a single frame memory. [Prior Art] FIG. 4 shows an outline of a conventional video rate non-interlace format conversion device. As shown in this figure, the conventional device has two frame memories, in which non-interlaced data can be written, and addresses are given from a read address generation circuit 10 or a write address generation circuit 11 via a switch 12, and read (Read) data is output via the selector 15. Frame memory 13
When the address of the frame memory 14 is given from the circuit 10, the address of the frame memory 14 is given from the circuit 11, and at this time, the selector 15 selects the address of the frame memory 1.
The read output of No. 3 (non-interlace data written in the previous cycle) is output as interlace data, and the non-interlace data currently being input is written into the frame memory 14. Since the write side is non-interlaced, the write address generation circuit 11 outputs 0, 1, 2, 3, . . .
(2N-1) and an address (line address) that increases sequentially by 1. Since the read side is interlace, the read address generation circuit 10 generates 0, 2, 4, ...... (2N-1) for even fields. 2),
1, 3, 5, ... (2N-
1) Generate an address (line address). In this way, in this device, while writing to one memory in a non-interlaced manner, reading from the other memory in an interlaced manner is possible, and the write/write for one frame is performed.
When reading is completed, switching is made so that one side is set as the reading side and the other side is set as the writing side, and this process is repeated thereafter to perform continuous writing/reading and non-interlace/interlace conversion. [Problems to be Solved by the Invention] However, in this conventional device, since the read frame memory and the line frame memory are separate, there is a problem in that two frame memories of the same capacity are required. The present invention attempts to improve this point and perform the same continuous writing/reading and non-interlace/interlace conversion as described above in one frame memory. [Means for Solving the Problems] As shown in FIG. 1, the frame memory is one of the memories (RAM) 8 in the present invention. In a semiconductor memory, when a word line is selected, the stored data of the memory cells belonging to the selected word line appears on each bit line all at once, and if this data is taken out through the data bus, it means that reading has been performed. Once the potential of the data bus is determined, it is transmitted to the memory cell through the bit line, and writing has been performed to the memory cell. In this way, the first half of one memory cycle is read and the second half is written, so that reading/writing to the memory can be performed almost simultaneously. However, the read address and write address will be the same. Assuming that the read address and write address are the same, and the write is non-interlaced and the read is interlaced, some ingenuity is required to generate the memory access address. The cyclic upper address generation circuit 6 is an address generation circuit designed in this way. The intra-line lower address generation circuit 7 generates an address for each pixel on the line. When one line corresponds to one word line, circuit 6 is a word line address generation circuit, and circuit 7 is a bit line address generation circuit. If the memory 8 is accessed using the combination of the upper and lower addresses from these circuits 6 and 7 (word line and bit line addresses),
Interlaced reading and non-interlaced writing can be performed simultaneously and continuously in pixel units. [Operation] In the present invention, certain pixel data is read out from the memory and output, and the pixel data input at that time is written to the same address in the memory. The image is a line Y
(vertical) direction, each line is divided into pixels (horizontal)
The number of lines in one frame (one image) is 2N (N is the number of lines in one field), and the first line, second line, ...(2N-1)th line, and 2N lines are in the same order 1, 2, ... (2N-
1), 2N, and the interlace signal is 1, 3, 5, ... (2N - 1), 2, 4, ... 2N
are output in this order. Therefore, in a certain frame, suppose that the hth pixel data of the k line is written to a certain address in the memory, and in the next frame, it is read out and the hth pixel data of the l line is written.The correspondence between k and l is as shown above. That is, k 1, 2, 3, 4, ... 2N-1, 2N l 1, N+1, 2, N+2, ... N, 2N. That is, if l is an odd number, k = (l +
1)/2, and if l is an even number, there is a relationship of k=N+l/2. In this relationship, if the memory write address of each pixel of a certain frame is determined, the write address of each pixel of the next frame is determined, and from the write address of the next frame, the write address of the next next frame is determined,
The write addresses of the following frames are determined in the same way. The write address of each frame is not all different,
It has synchronicity and repeats after one cycle.
The maximum value of the period is (2N-2). For example, if one frame has 6 lines (actually it is a large number such as 512), the period will be 4 frames as shown in the following table. Here, F1, F2, ... indicate the first frame, second frame, ..., and L1, L2, ... indicate 1
A line, two lines, . . . are shown.

〔Example〕

An example is shown in FIG. The signals input to this memory device are non-interlaced data output from an image processing device (not shown), a frame synchronization pulse FS that occurs once between each frame, and a line (horizontal) that occurs once between each line. ) synchronous pulse
LS, and a clock CLK which is generated once for each read/write of one pixel. Here, the above 1
Explaining this as a memory device for an image of frame 6 lines, since the period of the upper address is 4 frames as mentioned above, the frame period pulse FS
The counter 1 that counts is 2 bits. The counter for counting the line synchronization pulses LS is 3 bits, and is reset by the frame synchronization pulse FS to generate a line number. Write addresses A4, A2, . . . in the table below into ROM4.

〔Effect of the invention〕

As explained above, according to the present invention, sequence data after image processing, which is non-interlaced, can be continuously converted into an interlaced signal, which is a video signal format, using a single frame memory. It is valid.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the principle of the present invention, Figure 2 is a block diagram showing the principle of the present invention.
FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 3 is an explanatory diagram of upper addresses given to the memory, and FIG. 4 is a block diagram showing a conventional example. In Figures 1 and 2, 8 is a frame memory;
6 and 4 are upper address generation circuits.

Claims (1)

[Claims] 1. An image signal format conversion method for writing a non-interlaced image signal into a frame memory, reading it out, and converting it into an interlaced image signal, using a single frame memory, generating an upper address for the data of each line of the first frame of the image signal so that there is a one-to-one correspondence between the line and the memory upper address, and storing the data in the memory at the address; , the step of reading the memory address storing the lth line of the first frame and then writing the kth line of the second frame to the address, where k and l satisfy non-interlaced writing and interlaced reading. Assuming that the number of lines in one frame is 2N,
Similarly, in the m-th frame, reading the memory address storing the l-line of the m-1-th frame, and then storing the k-th line of the m-th frame at the address. An image signal format conversion method characterized by: