JPH10232662A - Number of scanning lines transformation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a number of scanning lines transformation device capable of miniaturizing a circuit scale and capable of suppressing a manufacturing cost. SOLUTION: When the writing of a first line is completed, a first changeover circuit 1 is set to a terminal (b). Then, the video signal of a second line is written in a line memory 3 in synchronization with a write clock WCK. When it becomes a time t1 , a second changeover circuit 10 is set to a terminal (d). In a line memory 2, a written video signal is read out in synchronization with a read clock RCK. The read video signal is supplied to a line memory 5 and also is outputted via the terminal (d) of the second changeover circuit 10. At this time, since the video signal Sd to be outputted via the terminal (d) of the circuit 10 is synchronized with the read clock RCK, the video signal Sd is outputted in the period of 3/4H.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning line number converter for converting the number of scanning lines of a video signal.

[0002]

2. Description of the Related Art Conventionally, for example, an LCD (Liquid Crystal Display) having a 16: 9 aspect ratio or a CRT (Cathode
Display devices such as Ray Tube) have an aspect ratio of 4: 3 N
When a video signal of the TSC (National Television System Committee) or the PAL (Phase Alternation by Line) system is supplied, a portion where no video is displayed occurs unless the number of scanning lines is converted. Therefore, in order to convert the number of scanning lines, the video signal is converted into a digital signal,
After accumulating the video signal for one field, the operation between the scanning lines is performed to interpolate the scanning lines.

[0003]

However, in the conventional conversion processing of the number of scanning lines, the video signal for one field is stored in a field memory, the video signal is weighted, and the scanning line is interpolated. I have. However, when a field memory is used, the circuit scale becomes large, and the device cannot be downsized. The field memory is
It is a relatively expensive device, causing an increase in production costs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a scanning line number conversion apparatus capable of reducing the circuit size and suppressing the production cost. .

[0005]

In order to solve the above-mentioned problems, a scanning line number conversion apparatus according to the present invention is capable of switching a video signal composed of m scanning lines for each scanning line and outputting the video signal. Switching means, a storage means for storing the video signal from the first switching means for each scanning line, and an interpolation signal to be generated and a video signal read from the storage means adjacent thereto. Interpolation signal generating means for weighting the video signal based on the distance to generate an interpolation signal, and switching between the video signal from the storage means and the interpolation signal from the interpolation signal generation means every (m / n) horizontal period A second switching means for outputting a video signal composed of n scanning lines.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. According to the present invention, the number of scanning lines can be converted using a line memory, which is a relatively inexpensive device.

As shown in FIG. 1, a scanning line number conversion apparatus according to a first embodiment of the present invention includes a first switching circuit 1 for performing switching setting for each line of a video signal, Line memories 2, 3, and 4 for storing one line of the video signal from the switching circuit 1 of the above, line memories 5, 6, 7 for storing the video signals from the line memories 2 to 4, respectively, and line memories 3, 5 An arithmetic circuit 8 for performing an arithmetic operation on the video signal from the line memories 4, an arithmetic circuit 9 for performing an arithmetic operation on the video signal from the line memories 4 and 6, and The apparatus includes a second switching circuit 10 for selecting and outputting a video signal, and a timing generation unit 11 for generating a predetermined signal based on a horizontal synchronization signal and a vertical synchronization signal of the video signal.

In order to increase the number of scanning lines of a video signal by, for example, 4/3, the scanning line number conversion apparatus weights the video signals of adjacent scanning lines as shown in FIG. Is increasing.

Here, the timing generator 11 generates a first switching signal for performing switching setting for each line of the video signal based on the horizontal synchronization signal and the vertical synchronization signal, and generates the first switching signal. A switching signal is supplied to the first switching circuit 1. Further, the timing generator 11 generates a second switching signal for performing switching setting four times in three horizontal scanning periods (hereinafter, referred to as 3H period) based on the horizontal synchronizing signal and the like. Is supplied to the second switching circuit 10.

[0010] The timing generator 11 is provided with a line memory 2
A read clock RCK having a clock rate 4/3 times as high as the write clock WCK is generated, and the read clock RCK is supplied to each line memory 2 and the like. The timing generator 11 supplies an independent read clock RCK to each line memory 2 and the like.

The first switching circuit 1 includes a timing generator 1
Terminals a, b, and c are set for each line (1H period) based on the first switching signal generated in step S1. The first switching circuit 1 supplies the video signal S _{3k + 1} to the line memory 2 via the terminal a, supplies the video signal S _{3k + 2} to the line memory 3 via the terminal b, and supplies the video signal S _{3k + 2} via the terminal c. Then, the video signal S _{3k + 3} is supplied to the line memory 4 (k = 0, 1, 2,...).

When the first switching circuit 1 is set to the terminal a in the line memory 2, the video signal is supplied to the write clock WC.
The data is written in synchronization with K. Further, the video signal is read out in synchronization with the readout clock RCK from the timing generator 11. The line memory 2 supplies the read video signal to the terminal d of the second switching circuit 10 and the line memory 5.

When the first switching circuit 1 is set to the terminal b in the line memory 3, a video signal is applied to the write clock WC.
The data is written in synchronization with K. The line memory 3 reads the video signal in synchronization with the read clock RCK from the timing generator 11. The line memory 3 supplies the read video signal to the arithmetic circuit 8 and the line memory 6.

When the first switching circuit 1 is set to the terminal c in the line memory 4, a video signal is written to the write clock WC.
The data is written in synchronization with K. Further, in the line memory 3, the video signal is read out in synchronization with the read clock RCK from the timing generator 11. The line memory 4 supplies the read video signal to the arithmetic circuit 9 and the line memory 7.

In the line memories 5, 6, and 7, the video signals from the line memories 2, 3, and 4 are written in synchronization with the write clock WCK, and the video signals are read in synchronization with the read clock RCK. It has become.
The line memory 5 supplies the read video signal to the arithmetic circuit 8, the line memory 6 supplies the read video signal to the arithmetic circuit 9, and the line memory 7 supplies the read video signal to the terminal g of the second switching circuit 10. To supply.

The arithmetic circuit 8 performs a weighting operation based on the video signal S _{3k + 1} from the line memory 5 and the video signal S _{3k + 2} from the line memory 3, and outputs an interpolation signal S1. Specifically, the arithmetic circuit 8 calculates Expression (1).

S1 = (１ ／) × S _{3k + 1} + (2/3) × S _{3k + 2} (1) The arithmetic circuit 8 calculates the video signal (interpolated signal) S1 is supplied to the terminal e of the second switching circuit 10.

The arithmetic circuit 9 performs the calculation of the weighting processing based on the image signal S _{3k + 3} from the video signal S _{3k + 2} and the line memory 4 from the line memory 6, and outputs the interpolated signal S2. Specifically, the arithmetic circuit 8 calculates Expression (2).

S2 = (2/3) × S _{3k + 2} + (1/3) × S _{3k + 3} (2) The arithmetic circuit 9 calculates the video signal (interpolated signal) S2 is supplied to the terminal f of the second switching circuit 10.

The second switching circuit 10 is switched and set to terminals d to g based on the above-mentioned second switching signal, and outputs a video signal S _{3k + 1} from the line memory 2 via the terminal d. The video signal S1 from the arithmetic circuit 8 is output via the terminal e,
The video signal S2 from the arithmetic circuit 9 is output via the terminal f, and the video signal S2 from the line memory 7 via the terminal g.
_It outputs _{3k + 3} .

Therefore, when a video signal is supplied to the scanning line number converter having such a configuration, the video signal is written or read in each line memory according to the timing chart shown in FIG.

More specifically, when a video signal is supplied to the scanning line number converter, the first switching circuit 1 is set to the terminal a, and the video signal of the first line is written to the line memory 2 by the write clock WCK. Is written in synchronization with.

When the writing of the first line is completed, the first switching circuit 1 is set to the terminal b. Then, the video signal of the second line is written into the line memory 3 in synchronization with the write clock WCK. At time t _1, the second switching circuit 10 is set to the terminal d. In the line memory 2, the written video signal is output from the read clock R
Read out in synchronization with CK. The read video signal is supplied to the line memory 5 and the second switching circuit 10
Is output via the terminal d. At this time, since the video signal Sd output via the terminal d of the second switching circuit 10 is synchronized with the read clock RCK, it is output in a ／ H period.

When the writing of the second line is completed, the first switching circuit 1 is set to the terminal c. Then, the video signal of the third line is written into the line memory 4 in synchronization with the write clock WCK. Becomes a time t _2, the second switching circuit 10 is set to the terminal e. In the line memories 3 and 5, the written video signals are respectively read out in synchronization with the read clock RCK.
The arithmetic circuit 8 converts the video signal from the line memory 5 into 1/3
Is added to the video signal from the line memory 3 by 2/3.
And outputs the calculation result via the terminal e of the second switching circuit 10. At this time, the video signal Se output via the terminal e of the second switching circuit 10
Are synchronized with the read clock RCK,
Output during H period.

When the writing of the third line is completed, the first switching circuit 1 is set to the terminal a. Then, the video signal of the fourth line is written into the line memory 2. At time t _3, the second switching circuit 10 is set to the terminal f. In the line memories 4 and 6, the written video signals are read out in synchronization with the read clock RCK. The arithmetic circuit 9 weights the video signal from the line memory 6 by ／ and weights the video signal from the line memory 4 by ３, and outputs the calculation result to the second switching circuit 10. Output via terminal f.
At this time, since the video signal Sf output via the terminal f of the second switching circuit 10 is synchronized with the read clock RCK, it is output in a ＨH period.

When the writing of the fourth line is completed, the first switching circuit 1 is set to the terminal b. Then, the video signal of the fifth line is written into the line memory 3. At time t _4, the second switching circuit 10 is set to the terminal g. In the line memory 7, the written video signal is read out in synchronization with the read clock RCK, and this video signal is output via the terminal g of the second switching circuit 10. At this time, since the video signal Sg output via the terminal g of the second switching circuit 10 is synchronized with the read clock RCK, it is output in a ／ H period.

As described above, the scanning line number conversion apparatus according to the first embodiment writes the video signals for three lines into each line memory for each line, and then applies the read video signals to the line memories. On the other hand, by performing the weighting process for four lines, the conversion process of the number of scanning lines can be performed without using a field memory, so that the circuit size can be reduced. In addition, since a relatively expensive device, ie, a field memory, is not used, production costs can be reduced.

Next, a second embodiment of the present invention will be described. The same circuits and the like as those in the first embodiment are denoted by the same reference numerals, and the detailed description is omitted.

As shown in FIG. 4, the scanning line number converter according to the second embodiment includes switching circuits 12, 13, and 14,
Line memories 2, 3, and 4 and operation circuits 8 and 9 are provided.

Here, the switching circuit 12 outputs a signal to the terminal i during the 1H period based on the switching signal from the timing generator 11.
In addition, the terminal is switched to the terminal h during the 2H period. Switching circuit 12
Represents the video signal from the terminal i or the terminal h in the line memory 2
To supply.

The switching circuit 13 is set to switch to the terminal k during the 1H period and to the terminal j during the 2H period based on the switching signal from the timing generator 11. The switching circuit 13
When the switching circuit 12 is set from the terminal i to the terminal h,
The terminal j is switched to the terminal k.
Then, the switching circuit 13 supplies the video signal from the terminal j or the terminal k to the line memory 3.

The switching circuit 14 is set to switch to the terminal n during the 1H period and to the terminal m during the 2H period, based on the switching signal from the timing generator 11. The switching circuit 14
When the switching circuit 13 is set from the terminal k to the terminal j,
The terminal m is switched to the terminal n.
Then, the switching circuit 14 supplies the video signal from the terminal m or the terminal n to the line memory 4.

In the line memory 2, the read clock RC
When the video signal is read out in synchronization with K, the video signal is supplied to the terminal h of the switching circuit 12, the terminal d of the second switching circuit 10, or the arithmetic circuit 8. In the line memory 3,
When the video signal is read out in synchronization with the read clock RCK, this video signal is supplied to the terminal j of the switching circuit 13, the arithmetic circuit 8, and the arithmetic circuit 9. In the line memory 4, when the video signal is read in synchronization with the read clock RCK,
This video signal is supplied to the terminal m of the switching circuit 14, the arithmetic circuit 9, and the terminal g of the second switching circuit 10.

The second switching circuit 10 is switched and set to the terminals d to g in the 3H period based on the above-mentioned second switching signal from the timing generator 11.

When a video signal is supplied to the scanning line number conversion device having the above configuration, the video signal is written or read in each line memory according to the timing chart shown in FIG.

Specifically, when a video signal is input, the switching circuit 12 is set to the terminal i, and a video signal for one line is written in the line memory 2 in synchronization with the write clock WCK.

When the writing of the first line is completed, the switching circuit 12 is set to the terminal h, and the switching circuit 13 is set to the terminal k. The video signal of the second line is written to the line memory 3 in synchronization with the write clock WCK.

At time t ₁ , the second switching circuit 10 is set to the terminal d. In the line memory 2, the video signal is read in synchronization with the read clock RCK. The read video signal is written into the line memory 2 again via the terminal h of the switching circuit 12 and output via the terminal d of the second switching circuit 10. At this time, the video signal Sd output via the terminal d of the second switching circuit 10
Is the read clock RCK, as in the first embodiment.
Are output in a 3 / 4H period.

When the writing of the second line is completed, the switching circuit 13 is set to the terminal j, and the switching circuit 14 is set to the terminal n. Then, the video signal of the third line is written into the line memory 4 in synchronization with the write clock WCK.

At time t ₂ , the second switching circuit 10 is set to the terminal e. In the line memory 2, the rewritten video signal is read again in synchronization with the read clock RCK. In the line memory 3, the written video signal is read in synchronization with the read clock RCK.
The read video signal is written into the line memory 3 again via the terminal j of the switching circuit 13 and supplied to the arithmetic circuit 8. The arithmetic circuit 8 performs an operation of weighting the video signal from the line memory 2 by ３ and weighting the video signal from the line memory 3 by ／, and outputs the calculation result to the second switching circuit 10. Output via terminal e.
At this time, since the video signal Se output via the terminal e of the second switching circuit 10 is synchronized with the read clock RCK, it is output in a ／ H period.

When the writing of the third line is completed, at time t
₃ , the switching circuit 14 is set to the terminal m, and the switching circuit 12 is set to the terminal i. Then, in the line memory 2, the video signal of the fourth line is supplied with the write clock WCK.
Is written in synchronization with.

At the same time, at the time t ₃ , the second switching circuit 10 is set to the terminal f. In the line memory 4, the written video signal is read out in synchronization with the read clock RCK. The read video signal is written into the line memory 4 again via the terminal j of the switching circuit 13 and supplied to the arithmetic circuit 8. In the line memory 3, the written video signal is read out in synchronization with the read clock RCK. The arithmetic circuit 8 performs an operation of weighting the video signal from the line memory 2 by ３ and weighting the video signal from the line memory 3 by ／, and outputs the calculation result to the second switching circuit 10. Output via terminal e. At this time, since the video signal Se output via the terminal e of the second switching circuit 10 is synchronized with the read clock RCK, it is output in a ／ H period.

At time t ₄ , the second switching circuit 10 is set to the terminal g. In the line memory 4, the rewritten video signal is read again in synchronization with the read clock RCK, and output via the terminal g of the second switching circuit 10. Since the video signal Sg output at this time is synchronized with the read clock RCK, it is output in a ／ H period.

As described above, in the scanning line number conversion device according to the second embodiment, as in the first embodiment, video signals for three lines are written into each line memory for each line. Thereafter, by performing a weighting process on the read video signal for four lines, a conversion process of the number of scanning lines can be performed without using a field memory, so that the circuit size can be reduced. be able to. In addition, since a relatively expensive device, ie, a field memory, is not used, production costs can be reduced. Furthermore, the production cost can be significantly reduced by halving the line memory used in comparison with the first embodiment.

It should be noted that the present invention is not limited to the above embodiment, and the number of scanning lines can be converted to an arbitrary number. For example, when converting the number of m scanning lines into n lines, a switching means for switching and supplying the video signal of each line is provided in the m line memories, and the video signal read from each line memory is provided. By weighting video signals adjacent to each other between lines to generate an interpolation signal, the conversion processing of the number of scanning lines can be realized.

[0046]

As described above in detail, according to the scanning line number conversion apparatus of the present invention, the distance between the interpolation signal to be generated and the video signal read from the storage means adjacent to the interpolation signal is determined. An interpolation signal is generated by weighting the video signal based on the above, and the video signal from the storage means and the interpolation signal from the interpolation signal generation means are switched every (m / n) horizontal periods, and the n scanning lines are used. By outputting such a video signal, the number of scanning lines can be converted without using a field memory, so that the circuit size can be reduced and the production cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a specific configuration of a scanning line number conversion device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the concept of scanning line number conversion.

FIG. 3 is a timing chart showing a state of writing and reading of a video signal of each line memory.

FIG. 4 is a block diagram showing a specific configuration of a scanning line number conversion device according to a second embodiment of the present invention.

[Explanation of symbols]

1 first switching circuit, 2, 3, 4 line memory, 8,
9 arithmetic circuit, 10 second switching circuit

Claims (3)

[Claims] 1. A first switching means for switching and outputting a video signal composed of m scanning lines for each scanning line, and storing the video signal from the first switching means for each scanning line. Storage means, interpolation signal generation means for generating an interpolation signal by weighting the video signal based on the distance between the interpolation signal to be generated and the video signal read from the storage means adjacent thereto, A second switching unit that switches a video signal from the storage unit and an interpolation signal from the interpolation signal generation unit every (m / n) horizontal period, and outputs a video signal composed of n scanning lines. Characteristic scanning line conversion device. 2. The image processing apparatus according to claim 1, wherein the storage unit stores a video signal from the first switching unit for each line, and stores a video signal from the first to m-th line memories. And (m + 1) th to (2m) th line memories for storing the image signals. The interpolation signal generation means weights the video signals read from the second and (m + 1) th line memories, respectively, and , A second interpolation signal generation unit that weights the video signals read from the third and (m + 2) th line memories to generate an interpolation signal, and .., the m-th and (2m
-1) an (n-1) th interpolation signal generation unit for generating an interpolation signal by weighting the video signal read from the line memory, and wherein the second switching means comprises: The video signal read from the first line memory, the interpolation signal from the first to (n-1) th interpolation signal generators, and the video signal read from the second line memory are divided into (m / n) horizontal periods. 2. The scanning line number conversion device according to claim 1, wherein the switching is performed every time and a video signal composed of n scanning lines is output. 3. The storage means includes first to m-th line memories for storing a video signal from the first switching means for each scanning line, and the first switching means includes: The video signals are switched and output to the first to m-th line memories for each scanning line. When the video signals are not output to the first to m-th line memories, the video signals are read out from the first to m-th line memories. The interpolated signal is output to the first to m-th line memories again, and the interpolated signal generation means weights the video signals read from the first and second line memories, respectively, and A first interpolation signal generation unit for generating, a second interpolation signal generation unit for generating an interpolation signal by weighting each of the video signals read from the second and third line memories, ... The (m-1) and m-th An (n-1) -th interpolation signal generating unit for generating an interpolation signal by weighting the video signals read from the in-memory, respectively, wherein the second switching means comprises a first line memory. , The interpolation signal from the first through (n-1) th interpolation signal generators, and the video signal read from the m-th line memory are switched every (m / n) horizontal periods. 2. The scanning line number conversion device according to claim 1, wherein a video signal comprising n scanning lines is output.