JPH01166269A - Image memory - Google Patents

Abstract

PURPOSE:To easily set an optional delay time without increasing the number of terminals of an image memory device by detecting the rise and fall edges of a control signal inputted from the outside and initializing write and read addresses at both edges. CONSTITUTION:The fall edge of a reset signal 1b received from an input terminal 9 is detected by a fall detecting circuit 4; while the rise edge of the signal 1b is detected by a rise detecting circuit 5. Both circuits 4 and 5 produce timing pulses 1d and 1c respectively. A write address generating circuit 2 works at the rise of a clock signal 1a and resets a write address 1e to be given to a memory part 1 with the pulse 1c detected by the circuit 5 for initialization of the address 1e. Furthermore, a read address generating circuit 3 works in the rise timing of the signal 1a and resets a read address 1f to be given to the part 1 with the pulse 1d detected by the circuit 4 for initialization of the address 1f. Then a video signal 1g inputted to an input terminal 6 is written in the part 1 and read out after an optional delay. Then a video signal 1h is outputted to an output terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image-only memory suitable for performing five-image signal processing.

[Conventional technology]

In digital video equipment 1. Line memory and field memory are important devices used in image signal processing (such as rectangular filters and spatial filters). N0j87.P
P, 92 to 94 KN [Dynamic memory dedicated to images of approximately IK 88 bits for use in standard television formats]
Discussed in the paper titled NTSC: line memory IC dedicated to the system.

There is a line memory IC dedicated to the 1'AL method. Each can store one horizontal scanning line of video signal sampled at a resolution of 8 bits and a sampling frequency of 4/sc (/sc is the frequency of the color subcarrier), and the memory capacity of each is as follows:
f3 x 910 bits and 8 x 1135 bits. Serial data is input asynchronously, and address generation circuits are built in for inserting and starting. In this address generation circuit, the write address and read address are initialized by externally applied write reset and read reset signals, respectively, and the values are updated by externally applied write clock and read clock signals. The delay time is the time it takes to input data to a certain address in memory and then read that address, so it is possible to set a delay time for this write reset and read reset. .

[The problem that the invention attempts to solve]

In the above-mentioned conventional technology, it is necessary to control two signals, write reset and read reset, in order to set the data delay time, resulting in an increase in the number of terminals of the memory IJIC.

An object of the present invention is to provide an image memory 1 in which delay time can be easily controlled without increasing the number of terminals of the memory device.

[Ninth way to solve problems]

In order to achieve the above object, the image memory of the present invention includes:
It detects the rising edge and falling edge of a control signal input from the outside, and generates a write address and a read address generation circuit at both edges.

[Effect]

With the above technical means, after the write address is initialized at the timing of the rising (or falling edge) of the control signal, input data is written to the memory according to the sequentially generated write addresses. After the read address is initialized at the timing of the falling edge (or rising edge) of the control signal, data is read out according to the sequentially generated read addresses. Therefore, from the rising edge (or falling edge) of the control signal The delay time of data in the image memory can be controlled by changing the period up to (lower) (or rising edge), that is, the pulse width of the control signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the first @, 1 is a memory section, 2 is a write address generation circuit, sr4 is a read address generation circuit, 4 is a falling edge detection circuit, 5 is a rising edge detection circuit, 6 is an input terminal for video data 1f, and 7 is video data 1j output terminal, 8
is the input terminal of the clock signal 1a, and 9 is the reset signal 14.
This is the input terminal of Here, it is assumed that the memory unit 1 can independently write and read data. The operation of this embodiment will be explained using the timing chart of FIG. Fifth
In the figure, 1a is the clock signal from the input terminal 8, 1 is the reset signal from the input terminal 9, lc is the output signal of the rising edge detection circuit 5, and 1d is the falling edge detection circuit 4.
14 is a write address from the write address generation circuit 2, a read address from the 1fB read address generation circuit 3, 1-inch image input data, and IJ is video output data.

The rising edge of the reset signal 1 from the input terminal 9 of the rising edge detection circuit 5 and the falling edge detection circuit 4μ, respectively.

and 1c and 1 in the 5th prisoner, respectively, detecting the falling edge.
Pulses are generated at the timing shown in d.

The write address generation circuit 2 operates at the rising timing of the clock signal 1tL, and the write address 14 is generated by the rising edge detection pulse IO of the reset signal 1tL as shown in FIG.
K is initialized to the seat address value AO, and thereafter the values are updated as At, A2, A3, . . . each time the clock signal 1G is input. In addition, the read address generation circuit 5 operates at the rising timing of the clock signal 1a, and the read address 1f is initialized to the sear address value 0 by the falling detection pulse 1d and Vc of the reset signal 14 as shown in the 5th @. , thereafter each time the clock signal 1a is input.

AI, A2. The value is updated as A5... ate data input 1t input from input terminal 6? To the area of memory unit 1 specified by write address 14! It's crowded. The data stored in this iF is read at address 1f.
y - Extracts the bladder from the area of the memory unit 1 specified by the direction. This timing chart shows the input catheter 1t and output data 1m. In the example of FIG.

The nine hours indicated by a in FIG. 5 from the writing of the data L)0 in the image input catheter 1 until the reading of the data LIO in the output data 1A is the data delay time. In the example of FIG. 6, a delay of four cycles of the clock signal 1a is obtained. That is, the time from initializing the write address 14 at the timing of the rising edge of the reset signal 14 to initializing the read address 1f at the timing of the falling edge of the reset signal 1b is the data delay time. Follow ℃.

In this embodiment, it is possible to control the data delay time by changing the pulse width of the reset signal 1, which is indicated by A.

FIG. 2 shows another embodiment of the invention. In Figure 2, 1
0 is the write data register. 11ij read data register, 12 is a switching circuit, 15 is a write clock signal 1A
The input terminal 14 is the input terminal for the read clock signal 1J-, and the other parts are the same as the embodiment shown in FIG. In the process shown in FIG. 2, it is assumed that the memory unit 1 cannot be filled in and read out at the same time, and that the memory access time is longer than the input/output data cycle time. In the embodiment of FIG. 2, video input data 1t from the input terminal 6
is led to the write data register 10, serial-to-halal conversion of the data is performed, and the actual cycle time is lengthened (
Then, this parallel data 1L is written into the memory section 1 all at once. Also, parallel data 1 read from memory section 1
j are collectively led to the read register 11, which is converted from parallel to serial to become the signal 1 at the original sampling rate.
A and output to output terminal 7. The switching circuit 12 switches between the write address 14 and the read address 1t and outputs it to the memory section 1.

This switching is performed by loading the video input data into the memory section 1 after the desired bits of video input data have been stored in the write data register 10, and after all the video output data in the read register 11 has been output from the memory section 1. Controls reading of the next parallel data. In the embodiment shown in FIG. 2, separate clock systems are used for reading and writing, so asynchronous input/output of data is possible.

Examples of both edge detection circuits are shown in FIGS. 4 and 5. In Figure 4 8 and 5th prisoner, 41 smoked inverter, 42 is A
NL) circuit, 46 is a NOR circuit, 44 is an output terminal for a rising υ edge detection signal, 45 is an output terminal for a falling υ edge detection signal, and 51 is a latch circuit.

In FIG. 4, reset signals 1-8 from input terminal 9
The output terminal 44K outputs the rising edge detection signal 1 of the reset signal 1 by ANDing the output of the inverter 41 and the reset signal 16.
You can get more. Further, by performing a NOR operation on both signals, a falling edge detection signal 1d is obtained at the output terminal 45.

The delay time of the inverter 41 is detected by the detection signals 1G and 1tt.
The detection pulse width is .

The example in Figure 5 is in Figure 4? The latch circuit 51 latches the reset signal 1k at the rising edge of the clock signal 1α. By ANDing and NORing the reset signal 1 and the inverted output of the latch circuit 51, the rising detection signal 1 is generated.
G and a falling edge detection signal 1d are obtained. In the example of FIG. 5, since both edge detection signals 1G and 1d are synchronized with the clock signal 1a, it is possible to synchronously reset the addresses in address generation circuits 2 and 6 in FIG. 1, for example. In the circuit shown in FIG. 5, the latch circuit 51 includes a rising edge detection circuit and a falling edge detection circuit.
However, when different clocks are used for writing and reading as in the embodiment shown in FIG.

It is necessary to use separate edge detection circuits for rising edges and falling edges, and to perform edge detection using a write clock or a read clock, respectively.

FIG. 6 shows another embodiment according to the present invention. 8 in FIG. 6, 61 is an input/output circuit that divides input/output data 1P into input data 1t and output data 1A and inputs/outputs them, 62 is a latch circuit, and other parts are implementations of FIGS. 1 and 2. The same parts as in the example are given the same reference numerals. FIG. 7 is a timing chart showing the circuit operation of the embodiment shown in FIG.

In FIG. 6, it is assumed that the memory 1 is of a type in which data cannot be written and read at the same time. The write address generation circuit 2 and the read address generation circuit 5 generate a clock signal 1 at 5 as shown in the timing chart of the seventh prisoner.
write address 14 at the startup timing of a.
and updates the value of read address 1f. Switching circuit 12)
j, one period of the clock signal 1a is divided into two periods, and the read address 1f and the write address 14 are switched in this order and outputted to the memory 1. This address output 1? L
A read-modify-write operation is performed by reading and writing one data according to the value of . In the embodiment of FIG. 6, the amount of delay becomes maximum when both the read address 1f and the write address 14 are reset at the timing shown in (a) in FIG. 7 as shown in the timing chart of FIG. In the embodiments shown in FIGS. 1 and 2, it is impossible to reset both read and write addresses at the same timing, but in the embodiment shown in FIG. Launch circuit 6
By providing 2, simultaneous reset is possible. A 1-clock width reset signal 14 shown in FIG. 7 inputted from the input terminal 9 is guided to the falling edge detection circuit 4 and the rising edge detection circuit 5, respectively, to generate a falling edge detection signal 1d.
and a rising edge detection signal 1G are outputted at the timing shown in FIG. This falling edge detection signal 1tt is latched by the latch circuit 62, and a signal 1m delayed by one clock is applied to the serial address 1/! Reset. In addition, the write address 1 is reset by the rising edge detection signal 1G. As described above, since the latch circuit 62 delays the falling edge detection signal 1et by one clock, in order to reset the write and read addresses at the same time and obtain the maximum amount of delay, the pulse width of one clock must be The signal may be input as the reset signal 14. In this embodiment, it is impossible to read the data written in a certain write cycle in the immediately following read cycle, that is, to reset the timing at which the amount of delay becomes the minimum, but this is not a practical problem as a delay element. do not have.

In the above embodiments, all the circuits are operated by timing the rising edge of the clock, but the present invention is not limited to this. No problem.

Also, although the explanation has been made assuming that the rising edge of the reset signal 14 initializes the write address and the falling edge initializes the read address, conversely, the falling edge initializes the write address and the rising edge initializes the IJ-address. There is no problem even if it is initialized (although the present invention includes this).

The invention is not limited to one or more embodiments, but includes an image memory device having an address generation circuit dedicated to read and write signals.

Includes all features that initialize read and write addresses on rising and falling edges. Although not particularly explained in the embodiments of the present invention.

Video data input terminal 6. Video data output terminal 7゜Memory section 1. Write data register 10. There is no problem even if the read data register 11 has an n-bit configuration (1 is a natural number) and inputs and outputs n-bit video data. Furthermore, when a dynamic memory is used as the memory section 1, a refresh circuit is required. In this case, for example, in the embodiment shown in FIG. 2, a refresh address generation circuit is added, and the output of this circuit and write and read addresses are switched and applied to the memory section 1.

The refresh operation may be performed during a period when writing and reading are not performed. Further, the clock signal may be the same for writing and reading as in the embodiment of FIG. 1, or different clocks may be used as in the embodiment of FIG.

〔Effect of the invention〕

According to the present invention, write and read addresses can be initialized with one signal, so any delay time can be easily set without increasing the number of terminals of the device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing another embodiment of the present invention. FIG. 3 is a timing chart for explaining the embodiment of FIG. 1, FIGS. 4 and 5 are circuit diagrams showing an embodiment of the edge detection circuit, and FIG. 6 shows another embodiment of the present invention. The block diagram, FIG. 7, is a timing chart for explaining the embodiment of FIG. 1...Memory part. 2...Write address generation circuit. 3...Read address generation circuit. 4... Falling edge detection circuit. 5...Rising edge detection circuit. Part 1 Zukka 4 Zuman 6 Mouth

Claims (1)

[Claims] 1. A storage means for storing video data, a video data input terminal, a video data output terminal, a reset signal input terminal, an address generation circuit for generating an address when writing data, and an address generation circuit for reading data. A read address generation circuit that generates an address, and a rising edge detection circuit and a falling edge detection circuit that detect a rising edge and a falling edge of a reset signal from the reset signal input terminal, the rising edge detection circuit and the An image memory characterized in that the detection output of one of the falling edge detection circuits initializes the write address in the write address generation circuit, and the detection output of the other one initializes the read address in the read address generation circuit.