JP2731192B2 - Digital scan converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention converts a signal of an ultrasonic image or the like by a predetermined television system, for example, a scanning system different from a standard television system, into a signal of a standard television system. To a digital scan converter (hereinafter abbreviated as DSC).

[Conventional technology]

2. Description of the Related Art Conventionally, various image processing apparatuses for simultaneously processing a plurality of types of images have been proposed as disclosed in JP-A-61-115548 and JP-A-63-99843.

FIG. 10 shows the configuration of a conventional image processing apparatus for processing two types of image signals. The sensors 1-1 and 1-2 have different scanning methods and are different from the standard television method, for example, an image sensor and an ultrasonic probe, and a signal detected by the sensor 1-1 is amplified by a receiving circuit 2-1. After such processing is performed, the signal is converted into a digital signal by the A / D converter 3-1. This digital signal is converted into a standard television scanning method by the DSC 4-1 and then converted into an analog signal by the D / A converter 5-1 and displayed on the display device 6-1 as a visible image. Similarly, the signal sensed by the sensor 1-2 is received by the receiving circuit 2-2, the A / D converter 3-2, the DSC 4-2, and the D
Although a visible image is displayed on the display device 6-2 by the standard television system via the / A converter 5-2, the sensors 1-1 and 1-2 have different scanning systems, so that the DSCs 4-1 and 4-2 have different scanning systems. The timing of the input signal is different.

In FIG. 10, the output signals of the sensors 1-1 and 1-2 are displayed independently on the display devices 6-1 and 6-2.
As shown in the figure, the D / A converters 5-1 and 5-2 may be selected by the switching circuit 7 and displayed on a single display device 6.

FIG. 12 shows a conventional DS used in the above-described image processing apparatus.
3 shows the configuration of C. The DSC 4 includes a line buffer 8, a frame memory 9, a write address generator 10, and a read address generator 11. Line buffer 8 is configured with a for example first-in-first-out can be carried out and writing 7 read asynchronously (FIFO), in the frame memory 9 of the input signal D ₂₁ from the A / D converter as shown in FIG. 13 output to the frame memory 9 as a signal D ₂₂ in synchronism with the write timing. Frame memory 9 sequentially stores the line buffer 8 in the corresponding area according to the write address WA generated from the address generator 10 to write the signal D ₂₂ which are read, reads the stored information address generator 11
After reading in accordance with the read address RA is generated corresponding to a standard television system, the output signal D ₂₃ D
/ A converter.

In this manner, the output signals of the sensors 1-1 and 1-2 by the scanning method different from the standard television method are output to the DSCs 4-1, 4-1.
At -2, the signal is converted into a signal of the standard television system.

[Problems to be solved by the invention]

However, with the improvement of integrated circuit technology in recent years, a RAM with a large storage capacity has become available as a rewritable frame memory used for DSC. Some have a storage capacity greater than the number of pixels. For example, a 1-Mbit RAM or the like has a storage capacity equivalent to four screens in an image of 512 pixels vertically and 512 pixels horizontally. For this reason, the above-described conventional
If the frame memory is adapted to only one type of input signal as in the case of DSC, unnecessary space is generated in the frame memory, and the number of frame memories corresponding to the type of input signal is required, resulting in cost reduction. There is a problem of becoming high.

The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a DSC appropriately configured so that a frame memory can be used effectively and inexpensively.

[Means and actions for solving the problem]

In order to achieve the above object, the present invention has a plurality of line buffers respectively storing a plurality of input signals, a signal switching circuit for selecting these line buffers, and a capacity for storing a plurality of screens of a predetermined television system. A frame memory, a plurality of write address generation circuits corresponding to the plurality of line buffers, and a plurality of write address generation circuits for generating a write address for storing a signal stored in each line buffer in a predetermined area of the frame memory; A write address switching circuit for selecting a generation circuit in synchronization with selection of the line buffer in the signal switching circuit, and storing the plurality of input signals corresponding to the signal switching circuit and the write address switching circuit in the frame memory. It is configured to be able to do.

〔Example〕

FIG. 1 is a block diagram showing a first embodiment of the present invention. In this embodiment, two sensors 21-1 and 21-1 having different scanning methods and different from the standard television method are used.
The two signals obtained from 21-2 are selectively converted into standard television signals and displayed on one display device 22. The signals sensed by the sensors 21-1 and 21-2 are received by receiving circuits 23-1 and 23-2, respectively.
After performing processing such as amplification in the corresponding A / D converter 24-
1 and 24-2 convert to a digital signal and use a single DSC25
The signal is selectively converted into a standard television signal, then converted into an analog signal by the D / A converter 26, and displayed on the display device 22.

As shown in detail in FIG. 2, the DSC 25 includes an A / D converter 24-
Line buffers 27-1 and 27-2 for inputting signals D ₁ and D ₂ from the lines ₁ and 24-2, respectively, and these line buffers 27-1 and 27-2.
An input signal switching circuit 28 for selecting the read signals D ₃ and D ₄ from the line buffer 2 and a selected line buffer having a storage capacity of at least the number of pixels for two screens of the standard television system.
A read signal D ₃ or the frame memory 29 for storing the D ₄ in the corresponding address area of from 27-1 or 27-2, the line buffer for the frame memory 29 27-1,27-
A read signal D _3, the write address generating circuit 30-1 and 30-2 for generating a write address A _1, A ₂ of the D ₄ from 2, the write address from these write address generator circuit 30-1 and 30-2 A write address switching circuit 31 for selecting A ₁ and A ₂ in synchronization with the selection of the line buffers 27-1 and 27-2 in the input signal switching circuit 28, and read signals D ₃ and D ₄ stored in the frame memory 29. selectively configuring with a the read address generating circuit 32 for generating a read address a ₃ for reading out is converted into a standard television signal DD _5. The line buffers 27-1 and 27-2 receive the input signals D ₁ and D
It is composed of, for example, a FIFO capable of asynchronously performing writing and reading of No. ₂ . Also, the write address generated from the write address generation circuits 30-1 and 30-2.
A _1, A ₂ is made to correspond to different regions 29-1 and 29-2 in the frame memory 29 as shown in FIG. 3, the write address A ₁
By storing the read signal D ₃ of the line buffer 27-1 in the region 29-1, so as to store the read signal D ₄ of the line buffer 27-2 in the region 29-2 by the write address A _2.

Hereinafter, the operation of this embodiment will be described with reference to the timing chart shown in FIG.

The line buffers 27-1, 27-2 have A / D converters 24-1, 2
Signals D ₁ and D ₂ asynchronous with each other and different from the standard television system are input from 4-2. The input signals D ₁ and D ₂ stored in the line buffers 27-1 and 27-2 are converted into read signals D ₃ and D ₄ synchronized with the write timing of the frame memory 29 and read. as signal D _3, D ₄ are read out at a timing that does not overlap, when reading the line buffer 27-1 by the switching signal a / the input signal switching circuit 28 is selected the read signal D _3, line buffer the Ki is reading 27-2 is supplied to the frame memory 29 the read signal D ₄ is selected. Write address generating circuit 30-1 and 30-2, and when the input signal switching circuit 28 and the read signal D ₃ from the line buffer 27-1 Similarly switching signal a / by being output in the write address switching circuit 31 the write address a ₁ is supplied to the frame memory 29 is selected or write address generating circuit 30-1, and the write address generating circuit 30-2 when the read signal D ₄ from the line buffer 27-2 is output
The write address A ₂ is a frame memory but is selected
Supplied to 29. As a result, the read signals D ₃ and D ₄ corresponding to the sensors 21-1 and 21-2 are stored in the corresponding areas 29-1 and 29-2 of the frame memory 29 and read from the read address generating circuit 32 in the standard television system. Area 29-1 corresponding to
By generates a read address A ₃ of that supplied to the frame memory 29, the sensor from the frame memory 29 21-
Signal by 1 is output after being converted into a standard television signal D _5, is displayed on the display device 22 through the D / A converter 26.
Further, the read address by supplying a read address A ₃ frame memory 29 by generating a region 29-2 corresponding to the standard television system from the generation circuit 32, the signal from the sensor 21-2 from the frame memory 29 is a standard television which is output is converted into a television signal D _5, it is displayed on the display device 22 through the D / a converter 26.

As described above, according to this embodiment, the signals output from the two sensors 21-1 and 21-2 can be converted into standard television signals by one DSC 25 and switched to one display device 22 for display. Since the signals output from the two sensors 21-1 and 21-2 are stored in the frame memory 29, any two
It is possible to freeze and switch between two images, and obtain exactly the same effect as switching the output using two DSCs. Further, by switching the read address A ₃ of the frame memory 29 in the image display may be divided into two parts the screen vertically or horizontally to display an image of the sensor 21-1 and 21-2 at the same time.

FIG. 5 shows a second embodiment of the present invention. In this embodiment, two signals obtained from two sensors 21-1 and 21-2 whose scanning methods are different from each other and which are different from the standard television system are respectively converted into standard television signals and the two display devices 22 are converted. -1, 22-2 are displayed separately. The signals sensed by the sensors 21-1 and 21-2 are processed by the receiving circuits 23-1 and 23-2 and the A / D converters 24-1 and 24-2 in the same manner as in the first embodiment, and are sent to the DSC 35. Supply. In this embodiment, the A / D converter 24 is used in the DSC 35.
-1, 24-2, are simultaneously converted into signals corresponding to the standard television system, and these are converted to the corresponding D / A converter 2
The data is displayed on the display devices 22-1 and 22-2 via 6-1 and 26-2.

FIG. 6 shows the configuration of the DSC 35. This DSC35
Are similar line buffers 27-1, 27- in FIG.
2. Input signal switching circuit 28, write address generation circuit 30
-1, 30-2, a write address switching circuit 31 and a read address generation circuit 32, and a line buffer 27-
A frame memory 37 for alternately storing read signals from the frame memories 1 and 27-2; a signal read from the frame memory 37 being separated into signals corresponding to the sensors 21-1 and 21-2; Output signal separation circuit
With 38.

FIG. 7 shows a frame memory 37 and an output signal separating circuit 38.
1 shows an example of the configuration. The frame memory 37 comprises a dual-port RAM including a RAM 41 having a storage capacity of at least two screens of pixels of a standard television system and a silica access memory (SAM) 42 capable of high-speed serial access. The circuit 38 includes latches 43-1 and 43-2 that receive the output of the SAM 42 in parallel.

In this embodiment, the signal a ₁₁ ~a _mn Oyo signal b ₁₁ ~b _mn read out from the line buffer 27-2, the column address direction C as shown in FIG. 8 in RAM41 read out from the line buffer 27-1 _{1 to} C _2m , the read operation in the line buffers 27-1, 27-2, the write address generation operation in the write address generation circuits 30-1, 30-2, the input signal switching circuit 28 and The write address switching operation is controlled. The data stored in the RAM 41 is sent from the read address generation circuit 32 to the row address.
By supplying r _x (x = 1, 2,..., n), as shown in FIG. 8, data a _1x , b _1x , b _1x , b _1x , c _2m of the column addresses C _{1 to} C _2m designated by the row address r _x a _2x , b _2x , ..., a _mx , b _mx are transferred to the SAM 42 at one time. The data transferred to SAM42 reads at high speed half period of the clock SCK of the read period T _p of pixels in a standard television system as shown in FIG. 9, the read signal D ₁₀ an output signal separation circuit 3
The data is supplied to the eight latches 43-1 and 43-2 in parallel. Latch 43−
In 1,43-2, a read signal D ₁₀ cycle phase latches respectively 180 ° different clock CK _1, CK ₂ at T _p from SAM42, thereby each standard from the latch 43-1 and 43-2 Sensors 21-1, 21-2 converted into television signals
Signals D ₁₁ (a _{1x to} a _mx ) and D ₁₂ (b _{1x to} b _mx ) of the display device 22-1, Display separately in 22-2.

As described above, according to this embodiment, one DSC 35 converts the scanning system of the signals from the two sensors 21-1 and 21-2 into the standard television system and separates the display units 22-1 and 22-2. Not only achieves exactly the same effect as having two DSCs, but also controls the phases of the clocks CK ₁ and CK ₂ supplied to the latches 43-1 and 43-2. Images of the same sensor can be simultaneously displayed on the devices 22-1 and 22-2.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications or changes can be made. For example, in each of the above-described embodiments, the signals from two sensors are converted from the scanning system to the standard television system and output, but the signals from three or more sensors are similarly standardized by one DSC. It is also possible to output by converting to a television system, and the television system to be converted is not limited to the standard television system, but may be any predetermined system. In the second embodiment, the frame memory 37 is constituted by a dual-port RAM. However, when two types of image signals are handled, the frame memory 37 has a cycle of 1/2 of the read cycle of the pixel of the television system to be converted, and 3 frames. When handling different types of image signals, an arbitrary RAM that can be read at a 1/3 cycle can be used.

[Effects of the Invention] As described above, according to the present invention, a single DSC converts a signal of a scanning method different from a predetermined television method output from a plurality of sensors into a predetermined television signal. Therefore, if large-capacity RAM is used for DSC,
Free space can be used effectively, so that the number of RAMs can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a DSC shown in FIG. 1, FIG. 3 is a diagram showing an area of a frame memory shown in FIG. 4 is a timing chart showing the operation of the DSC shown in FIG. 2, FIG. 5 is a block diagram showing a second embodiment of the present invention, FIG. 6 is a block diagram showing the configuration of the DSC shown in FIG. FIG. 7 is a block diagram showing an example of the configuration of the frame memory and output signal separation circuit shown in FIG. 6, FIGS. 8 and 9 are diagrams for explaining the operation of the DSC shown in FIG. 6, and FIG. , FIG. 11, FIG. 12, and FIG. 13 are diagrams for explaining a conventional technique. 21-1, 21-2: Sensor, 22, 22-1, 22-2: Display device 23-1, 23-2: Receiving circuit, 24-1, 24-2: A / D converter 25, 35 DSC 26, 26-1, 26-2 D / A converter 27-1, 27-2 Line buffer 28 Input signal switching circuit 29, 37 Frame memory 30 1, 30-2: Write address generation circuit 31: Write address switching circuit 32: Read address generation circuit 38: Output signal separation circuit, 41: RAM 42: SAM, 43-1, 43-2 …latch

Claims (1)

(57) [Claims] 1. A plurality of line buffers respectively storing a plurality of input signals, a signal switching circuit for selecting these line buffers, a frame memory having a capacity for storing a plurality of screens of a predetermined television system, A plurality of write address generation circuits corresponding to a plurality of line buffers and generating write addresses for storing signals stored in each line buffer in a predetermined area of the frame memory; A write address switching circuit for selecting in synchronization with the selection of the line buffer in the switching circuit, wherein the plurality of input signals corresponding to the plurality of input signals can be stored in the frame memory by the signal switching circuit and the write address switching circuit. Digital ski Free converter.