JPS62208766A - Video synthesizer - Google Patents

Abstract

PURPOSE:To display other picture while it is inserted in one picture without using a memory element other than a field memory by using a dual port memory as the field memory. CONSTITUTION:The 1st synchronizing pulse generating circuit 4 outputs the 1st clock signal H and the 2nd synchronizing pulse generating circuit 9 outputs the 2nd clock signal I respectively. A selection means 14 has one fixed contact 14a and two moving contacts 14b, 14c, the moving contact 14b is connected to a serial port 12b, and the other moving contact 14c is connected to an output of the 1st A/D converter 5 and the contacts are changed over by using a switching signal from a memory control circuit 13. The 2nd digital picture signal F is written in a dual port memory 12 by a memory cell array control signal from the control circuit 13 and an address signal. Further, the content of the memory 12 is read and outputted sequentially by the 1st clock signal H.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to an image compositing bag W, in particular, which uses a dual port memory or a multi-port memory to process a video signal and combine different signals into one image. This relates to an image that is inserted and displayed.

[Conventional technology]

FIG. 6 is a diagram showing an example of the configuration of a conventional video synthesis device of this type installed in a television receiver. In the figure, 18 and 19 are selection means, and 2.7 is the first selection means. A second decoder, 10 is an A/D converter, 20 is a 1-line buffer, 21 is a field memory, 15 is a D/A converter, 22 is a color signal processing circuit, 23 is a selection means, and 16 is an encoder.

Next, the operation will be explained. The selection means 18 is the fixed contact 1
8a and movable contacts 18b and 18c, and when one movable contact 18b is electrically connected to the fixed contact 18a, the information from the first input end 1 for inputting the first image information is transferred to the subsequent stage. The composite signal is supplied to a first decoder 2 in which the composite signal is converted into component signals. When the other movable contact 18c is electrically connected to the fixed contact 18a, information from the second input terminal 6, which inputs the second image information, is supplied to the first decoder 2.

Further, the selection means 19 has a fixed contact 19a, a movable contact 19b,
19C, and when one movable contact 19b is electrically connected to the fixed contact 19a, the information from the second input terminal 6 is supplied to the second decoder 7, which is different from the first decoder 2. In the decoder 7, the composite signal is converted into component signals. Conversely, when the other movable contact 19c is electrically connected to the fixed contact 19a, information from the first input terminal 1 is supplied to the second decoder 7.

Note that the movable contact 18b of the selection means 18 is the fixed contact 18a.
If the movable contact 19b of the selection means 19 is electrically connected to
is electrically connected to the fixed contact 19a, and conversely, when the movable contact 18c of the selection means 18 is electrically connected to the fixed contact 18a, the movable contact 19c of the selection means 19 is controlled to be electrically connected to the fixed contact 19a.

The A/D converter 10 converts the analog output of the second decoder 7 into digital information, and stores it in a 1-line buffer 20 at the subsequent stage. , is output to the field memory 21.

The D/A converter 15 converts the digital information in the field memory 21 into analog information and outputs it to the subsequent color signal processing circuit 22. The 0 selection means 23 has a fixed contact 23a.
and movable contacts 23b and 23c, the fixed contact 23a is connected to the encoder 16, one movable contact 23b is connected to the output of the first decoder 2, and the other movable contact 23c is connected to the output of the color signal processing circuit 22. It is connected to the. Further, the output terminal 17 is connected to the output of the encoder 16, and the component signal from the first decoder 2 or the color signal processing circuit 22 is converted into a composite signal by the encoder 16 and output from the output terminal 13.

[Problem that the invention seeks to solve]

Conventional video compositing devices are configured as described above, and the field memory has only one type of random boat as an output, so when inserting and displaying another image within one image, the first The need to synchronize the image and the second image results in a complex configuration including a one-line buffer as shown in Figure 6, and also requires complicated operations when writing the contents of the one-line buffer to the field memory. Ta.

In addition, since switching between the first image and the second image is performed using an analog signal, waveform distortion at the time of switching poses a problem.

The present invention has been made in order to solve the problems of the conventional ones as described above, and it is possible to easily configure a device for inserting and displaying another image within one image. It is an object of the present invention to provide a video synthesizing device that can switch between a first image and a second image with easy operation without causing waveform distortion.

[Means for solving problems]

A video synthesis device according to the present invention uses a dual port memory or a multi-port memory as a field memory.

Also number 1. The switching of the second image is performed at the stage of the digital image signal.

[Effect]

In the present invention, a dual-port memory (or multi-port memory) is used as the field memory, and since the dual-port memory can read and write data asynchronously, it is possible to continuously write data to one image in real time. You can insert and display images.

Furthermore, since image switching is performed at the digital image signal stage, there is no fear of waveform distortion occurring due to switching.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

First, in FIG. 1 showing the overall configuration of a video synthesis apparatus according to an embodiment of the present invention, the same reference numerals as in FIG. Second synchronous separation circuit, 4
．． 9 is the first. The second synchronous clock generation circuit 5.10 is the first synchronous clock generation circuit. In the second A/D converter, 1) is an oscillator, 12 is a dual port memory, 13 is a memory control circuit (control means), and 14 is a selection means (switching means).

Next, the operation will be explained. Information input from a first input terminal 1 that inputs first image information is supplied to a first decoder 2 that converts a composite signal into a component signal. The first synchronization separation circuit 3 separates the output of the first decoder 2 into a first synchronization signal A and a first image information symbol B, and the first synchronization signal A is sent to the first synchronization clock generation circuit 4 and The first image information body B is outputted to the first A/D converter 5 to become the first digital image signal C.

On the other hand, information inputted from a second input terminal 6 that inputs second image information is supplied to a second decoder 7 that converts a composite signal into a component signal. A second synchronization separation circuit 8 converts the output of the second decoder 7 into a second synchronization signal and a second synchronization signal.
The image information body number E is separated into two, and the second synchronization signal is the second
The second image information body E is outputted to the synchronous clock generation circuit 9 and to the second A/D converter 10 to be converted into a second digital image signal F.

The first synchronization clock generation circuit 4 and the second synchronization clock generation circuit 9 are signals synchronized with the output G from the oscillator 1) and the first synchronization signal A or the second synchronization signal, that is, the first synchronization signal. The pulse generating circuit 4 receives the first clock signal H.
The second synchronizing pulse generating circuit 9 outputs the second clock signal I, respectively. Next, the dual port memory 12 has a write port 12a to which the second digital image signal F is input and a serial port 12b for output, and a memory control circuit that operates in response to the second clock signal I. 13.

The selection means 14 has one fixed contact 14a and two movable contacts 14b, 14c, one movable contact 14b is connected to the serial port 12b, and the other movable contact 14c is connected to the first A/D converter 5. The selection means 14 is connected to the output terminal, and the selection means 14 is switched by the switching signal J from the memory control circuit 13, and the fixed contact 14a is connected to the input of the D/A converter 15 operated by the first clock (H). The encoder 16 converts the component signal from the D/A converter 15 into a composite signal and transmits it to the output end 17.

Next, the image synthesis process in the circuit shown in FIG. 1 will be described, taking as an example the case where pixels are arranged in a matrix of 8 rows and 8 columns as shown in FIG. 2(a).

For the pixels in 8 rows and 8 columns, the 1st row, 2nd row, etc. from the top.
..., the 8th row, and the 1st column from the left.

The second column..., will be referred to as the eighth column, and will be referred to as the i-th row and j-th column of the first image (however, ""LL..., 8. j-1゜2
, . . . , 8), and the pixel at row 1 and column j of the second image is represented by Bij. Now, Figure 2 (
Insert a second image smaller than the first image as shown in Figure 2 ('b) into the first image shown in a) at the bottom right of the first image as shown in Figure 2 (C1). Consider the case where it is displayed as shown below.

In this case, the dual port memory 12 and the memory control circuit 13 have a configuration as shown in FIG. First, the dual port memory 12 is roughly divided into a memory cell array section 12c and a serial output section 12d constituted by a shift register that stores information for one row of the memory cell array for serial output.

The memory cell array section 12C receives a memory cell array control signal from the control circuit 13 and an address signal Ko,
+, Kt (Ko is the lowest address signal, K,
is the highest address signal), the second digital image signal F is written from the write port 12a. Further, the serial output section 12d sequentially reads out the contents of the serial output section 12d in response to the first clock signal H and outputs them to the serial port 12b.

Further, the memory control circuit 13 includes a memory array control section 13a that generates the memory array control signal a from the second clock signal (2), counts the second clock signal I, and outputs Ma, M+, Mt( MO is the lowest signal and Mt is the highest signal).
3b and the above-mentioned signals Mo, M+, and Mz, the addressee name Ko is generated.

an address generating circuit 13c that generates 2 at Kl, an insertion point indicating section 13d that indicates a position where another image is to be inserted, a first counter t3e that counts the first clock signal H, and an insertion position and the first counter 13c. and a switching signal generating section 13f that compares the output of the switching signal 13e with the switching signal J and outputs the switching signal J.

In particular, when inserting another image at a position such as that shown in FIG. ,
This is possible by configuring it to connect.

In the above case, the above-mentioned second
The digital image signal F is compressed as shown in FIG. 5('b) and written into the memory cell array section 12c. Here, φ in the figure indicates an unmanned state.Next, the information shown in FIG. The switching signal J is read out using the first clock signal H. However, when the switching signal J is used to read out pixels in the fourth row or later and in the fourth column or later, the movable contact 14b of the selection means 14 is electrically connected to the fixed contact 14a, and otherwise. In this case, the movable contact 14c of the selection means 14 is controlled to conduct to the fixed contact 14a, and by this switching control n, the output end 17 selects the first image as shown in FIG. 5(C). A signal with the second image inserted therein is output.

In the above example, the number of pixels in the image was set to 8 rows and 8 columns, but
This configuration is arbitrary, and the inserted images need not be limited to 4 rows and 4 columns.

Further, in the above embodiment, the second image is displayed so as to be inserted at the lower right of the first image, but it is not necessary to limit it to this position.

Further, in the above embodiment, the address generation circuit 13c is constructed by wiring as shown in FIG. 4, but the address generation circuit 13c may be constructed using the method of connecting memory elements.

Furthermore, in the above embodiment, a compressed image is inserted as shown in FIG.

Further, in the above embodiment, the first image information, the second image information, and the composite output are all composite signals, but some or all of these may be component signals.

Further, in the above embodiment, switching between the first image and the second image is performed using digital signals, but the switching operation may also be performed using analog signals as shown in FIG.

Furthermore, although the above embodiments have been described with respect to reading out recorded information, the present invention can also be applied when recording images. In this case, a signal is recorded in which another image is inserted into one image (the state shown in FIG. 5 fcl).

〔Effect of the invention〕

As described above, according to the video composition device according to the present invention, since the dual port memory is used as the field memory, it is possible to combine other images in one image without using any storage element other than the field memory. Images can be inserted and displayed, and since two images are switched in the digital signal state, there is no need to worry about waveform distortion when switching.

[Brief explanation of drawings]

Fig. 1 is an overall configuration diagram of a video synthesis device according to an embodiment of the present invention, Fig. 2 (al to (C) are explanatory diagrams of image information,
1m is a detailed explanatory diagram of the dual port memory and memory control circuit of FIG. 1, FIG. 4 is a diagram showing an example of the address generation circuit of FIG. 1, and FIGS. 5(a) to tc+ are inserted. FIG. 6 is an explanatory diagram of image information, FIG. 6 is a diagram for explaining a conventional technique, and FIG. 7 is a diagram showing an image synthesizing apparatus constructed by applying the basic principle of the present invention. In the figure, 2 is a first decoder, 5 is a first A/D converter, 7 is a second decoder, 10 is a second A/D converter, 12 is a dual port memory, 13 is a memory control circuit (controller vJl), 14 is a selection means (switching means). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A field memory for storing a second digital image signal among the digital image signals of the first and second images to be combined; and a field memory for storing the second digital image signal from the field memory and the first image signal. a switching means for switching and outputting a digital image signal, and a control means for controlling the field memory and the switching means so that a second image is inserted and displayed in the first image; A video synthesis device characterized in that a dual-port memory or a multi-port memory is used as a memory.