JPH0273293A - Scan converter circuit - Google Patents

Abstract

PURPOSE:To simultaneously display plural input images by providing a constitution to plural input images and instructing an area to be outputted from a display instruction memory at every constitution. CONSTITUTION:To a display instruction memory 1i and a drawing memory 3i of a constitution 100i corresponding to an input image signal (i), an address is sent from a read-out address 9. The signal (i) is separated as to a synchronizing signal by a synchronizing signal separating means 5i, and a write address to the memory 3i is generated by a write address generating means 6i. The memory 3i writes in the signal (i) from a buffer means 2i in accordance with the write address. In this case, a write timing control means 4i executes a control so that signal output timings of the means 2i, 6i are not overlapped on an address application timing of the means 9. In this state, the memory 1i instructs an area to be outputted of the signal (i), and the signal (i) passes through a display area gate means 7i and outputted from an output means 8. In such a way, prescribed areas of plural signals (i) can be displayed simultaneously on one display.

Description

[Detailed Description of the Invention] 1. Requirements Regarding a scan converter circuit that outputs human-generated image signals at different scanning frequencies, A display instruction memory, a buffer means, a screen memory, and a display instruction memory, a buffer means, and a screen memory for each of the plurality of input image signals, the purpose of which is to enable simultaneous display on one display device of a scanning frequency.
A write timing control means, a synchronization signal separation means, a write address generation means, and a display area gate means are provided, and a read address generation means and a composite image output means are provided in common for the plurality of input image signals. The readout address generation means, which is provided in common for the plurality of input image signals, simultaneously performs a common readout at a predetermined timing for all of the display instruction memories and all of the screen memories. address is applied, the composite image output means outputs the sum of the outputs of all the display area gate means as an output image signal, and for each of the plurality of input image signals, the synchronization signal separation means respectively separating a synchronization signal from a corresponding input image signal, and the write address generating means generates a write address to the screen memory at the timing of each corresponding synchronization signal,
The buffer means is provided upstream of the corresponding screen memory and temporarily holds the input image signal,
The screen memories write input image signals outputted from the corresponding buffer means according to the write addresses, and the write timing control means apply the write addresses from the corresponding write address generation means to the screen memory. and the timing of the output of the input image signal from the buffer means are controlled so that they do not overlap with the timing of the read address, and the display instruction memory is configured to select one of the corresponding input image signals as an output image. An area to be displayed is specified, and the display area gate means is configured to control application of output from each address of the screen memory to a subsequent stage based on instructions of the corresponding display instruction memory.

[Industrial application field]

The present invention relates to a scan conversion circuit that outputs manually input image signals at different scanning frequencies.

2. Description of the Related Art With the diversification of visual devices, image display devices with different scanning frequencies have come into existence. For example, regular TV (NTSC system), personal
The scanning frequency of the image signal is different from that of a computer.

On the other hand, it is also practiced to divide the screen area of one display device to display a plurality of images simultaneously.

In this way, in general, when the scanning frequencies of a plurality of input image signals to be displayed are different from each other, it is possible to further divide the area on the screen of the display device whose scanning frequency is different from that of the input image signals. , there has been a demand for displaying the plurality of input images simultaneously.

[Prior art and problems to be solved by the invention]

Conventionally, a scan conversion circuit that makes it possible to display an output image at a scanning frequency different from that of the input image signal uses two systems of 1-line memories that alternately hold data for each line of the input image signal. On the other hand, a horizontal synchronizing signal is separated from the input image signal, an output horizontal synchronizing signal having twice the frequency is generated in synchronization with the synchronizing signal by a PLL circuit, and the two systems are controlled by this output horizontal synchronizing signal. Among the 1-line memories, image data of the same line is read twice from the 1-line memory in which no write operation is being performed. Note that in this case, the vertical synchronization signal is not converted.

However, in the conventional scan conversion method, when the scanning frequencies of a plurality of input image signals to be displayed are different from each other (generally, both the horizontal synchronization signal and the vertical synchronization signal are different from each other),
A scanning frequency different from the scanning frequency of these input image signals (
Similarly, it has been impossible to divide the area on the screen of a display device (generally with different horizontal and vertical synchronizing signals) and display the plurality of input images at the same time.

The present invention has been made in view of the above-mentioned problems.
It is an object of the present invention to provide a scan conversion circuit that can simultaneously display predetermined areas on one display device with different scanning frequencies.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of the present invention. In the configuration shown in this figure, a configuration indicated by a broken line 10L (+=1 to n) is provided corresponding to each of the plurality of input image signals 1=1 to n having respective independent scanning frequencies. ing.

The configurations within the broken line 10 (L (i=1 to n) respectively input corresponding ones of the plurality of input image signals i=l to n, and each of the configurations includes a display instruction memory 1
i, buffer means 2i% screen memory 3I, write timing control means information, synchronous output separation means 5i, write address generation means 6i, and display area gate means 71.

The outputs of these configurations 100I (1=1 to n) are all applied to the composite image output means 8.

The read address generating means 9, which is provided in common for the plurality of input image signals (1=1 to n), generates all of the display instruction memories 18, 1□, . . . l, and the screen. A common read address is simultaneously applied to all the memories 31n3□, .
The sum of the outputs of 1, 7□, . . . 7ゎ is output as an output image signal.

In the configuration provided corresponding to each of the above input image signals i (i=l to n), the synchronization signal separation means 5i separates the synchronization signal from the corresponding input image signal l,
The write address generation means 6i generates a write address to the screen memory 31 at the timing of the output of the corresponding synchronization signal, that is, the synchronization signal separation means 5i.

The buffer means 2i each have a corresponding screen memory 31.
is provided at the front stage of the input image signal to temporarily hold the input image signal;
The screen memory 3I writes the input image signals outputted from the corresponding buffer means 2i according to the write address.

The write timing control means 4i controls the timing of applying the write address from the corresponding write address generation means 6i to the screen memory 3i and the timing of outputting the input image signal from the buffer means 2i. , is controlled so as not to overlap with the timing of application of the read address.

The display instruction memory II instructs the area to be displayed as an output image in the corresponding input image signal 1, and the display area gate means 71 controls the area of the screen memory 31 based on the instruction of the corresponding display instruction memory h. Controls the application of output from each address to the subsequent stage.

[For production]

In each of the configurations 100I in FIG.
The input image signal i is written into the screen memory 3I via the buffer means 2s, and the input image signal i is written into the screen memory 3I at the timing of application of the readout address generated by the readout address generation means 9.
The image data written in is read out as an output image signal.

Incidentally, the writing timing of the input image signal l is normally determined from the synchronization signal separating means 5 from the input image signal i.
The write address outputted from the write address generating means 6i at a timing synchronized with the synchronization signal separated by 1 is applied to the screen memory 3□. When the timing coincides with the application of the address, the write timing control means 4i controls the timing of application of the write address to the screen memory 31 and the buffer means 2. Controls the timing of application of the corresponding input image signal l to the screen memory 3I to be outputted next from the screen memory 3I of the write address.
The timing of application to n does not overlap with the timing of application of the read address to the screen memory 31.

On the other hand, the readout address is applied from the display instruction memory 1i at the same time as the application to the screen memory 3i, and in response, the display instruction memory 1 receives the subsequent address output from the screen memory 3i. A display instruction indicating whether or not the image data should be displayed as an output image is output, and an area of the image data to be displayed as the output image is specified. The display area gate means 7i is
Using the display instruction output from the display instruction memory lt as a control signal, application of the image data at the read address simultaneously output from the screen memory 31 to the subsequent stage is controlled.

As a result, only the image signal of the area designated by the display instruction memory 11 is outputted from the display area gate means 71 at the timing of the output of the read address generation means 9. In this way, the output image is a composite of these multiple input image signals.

FIG. 2 is a diagram for explaining the function of combining and displaying a plurality of images on a display screen by the screen memory, display instruction memory, display area gate means 71%, and composite image output means 8 in the present invention. It is.

Image data based on the input image signal 1 is written on the screen memory 31, as indicated by A in FIG. Display instruction data is written on the display instruction memory 1 to instruct which part of the image data is to be shown on the display screen. In FIG. 2, a portion indicated by α indicates an area where the display instruction data is valid data.

On the other hand, image data based on the input image signal 2 is written on the screen memory 2□, as shown by B in FIG. Display instruction data that instructs which part of the image data is to be shown on the display screen is written on the display instruction memory 22. A portion indicated by β indicates an area where the display instruction data is valid data.

In the configuration for the input image signal l, the contents of each address of the screen memory 31 and the display instruction memory 1 are
1 are applied at the same time, and of the input image data indicated by A in the screen memory 31, only the data of the portion that overlaps with the area indicated by α of the display instruction memory 11 is displayed. Area gate means 71
The signal passes through and becomes an effective input to the OR circuit 8 at the next stage.

Similarly, in the configuration for the input image signal 2, the contents of each address of the screen memory 32 and the display instruction memory 1
The contents of the corresponding addresses of □ are applied at the same time, and of the input image data indicated by B in the screen memory 3 □, only the data of the portion that overlaps with the area indicated by β of the display instruction memory 12 is applied. Display area gate means 72
It passes through and becomes effective human power for the OR circuit 8 at the next stage.

In this way, if the display instruction data to be written into the display instruction memories 1n and 1□ is appropriately determined in advance, the corresponding OR
Output image data obtained by suitably combining the input image data 1 and 2 is obtained from the circuit 8 in accordance with the display instruction data.

Incidentally, the output of the read address generation means 9, that is, the read address is common and simultaneous to all of the configurations 100+ (1=1 to n) for a plurality of input image signals, and the read address The timing of the output of is unrelated to the timing of the plurality of input image signals.

Among the plurality of input image signals, for an input image signal whose scanning frequency is relatively higher than the scanning frequency of the output image signal determined by the output timing of the read address, the data on the time axis in the output image is On the contrary, for an input image signal whose scanning frequency is relatively lower than the scanning frequency of the output image signal determined by the output timing of the read address, the input image signal is thinned out in the output image signal. Some parts will be repeated.

〔Example〕

FIG. 3 shows the configuration of an embodiment of the present invention.

In FIG. 3, 1001 corresponds to the configuration within the broken line 100 in FIG. 1, 11O is an A/D converter, 20 is a FIFO memory, 30 and 32 are shift registers, 31 is a screen memory, 33 and 34 is a 1/4 frequency divider circuit, 40 is an address selector, 4i is an AND circuit,
70 is an AND circuit, 50 is a synchronization signal separation circuit, 60 is a write synchronization signal output circuit, and 6i is a write pixel counter.

In the above configuration, the A/D converter 110 samples a television image signal (input image signal) input as an analog signal at a timing synchronized with a write dot clock DCK output from a write synchronization signal output circuit 60, which will be described later. It converts the signal into a digital signal and outputs it serially.

The FIFO memory 20 is a buffer means 2 having the configuration shown in FIG.
i, which sequentially stores the input image digital signals serially output from the A/D converter 110 in synchronization with the write dot clock DCK output from the write synchronization signal output circuit 60, and The stored contents are serially output in the order in which they were stored, in synchronization with a FIFO read signal FRD output by an AND circuit 4i, which will be described later.

Screen memory 31 and shift registers 30 and 32
This configuration corresponds to the screen memory 3i having the configuration shown in FIG. Among these, the screen memory 31 is
It has an address area for the entire display screen that displays the output image, and in particular, the screen memory 31 of this embodiment has four dual
It consists of DRAM.

Each dual port DRAM has two mutually independent data input/output ports, and in the configuration shown in FIG.
Of the two mutually independent data input/output ports in each AM, one is used only for writing, and the other is used only for reading.

The shift register 30 sequentially stores the input image digital signals serially output from the FIFO memory 20 in synchronization with the write dot clock DCK, and further stores the input image digital signals serially outputted from the FIFO memory 20, and further stores the input image digital signals serially outputted from the FIFO memory 20, and further stores the input image digital signals serially outputted from the FIFO memory 20.
In response to O, the input image digital signals stored in sequence as described above are output in parallel in 4-bit units.

Each of the 4-bit outputs is serially applied to the write-only data input/output port in the corresponding one of the four dual-boat DRAMs of the screen memory 31, and the applied 4-bit output Each of the above four dual ports is selected by the address selector 40, which will be described later, at the write timing, which will be described later.
The data is written to the address AD to be output for each of M.

From each of the four dual-port DRAMs, the data of the line specified by the address AD output by the address selector 40 is further processed by the 1/4 frequency divider circuit 34, which will be described later, at the timing of reading, which will be described later. It is read out at the timing of the read clock RDCK4 whose frequency is divided by 1/4 to be output.

The shift register 32 provided on the output side of the screen memory 31 has a 4-bit parallel input port and a serial output port.
The 4-bit output from the read-only data input/output port in each of the two dual-port DRAMs is programmed according to the read clock RDCK4 whose frequency is divided by 1/4, and this is also described later. (Horizontal pixel) Serially outputs one bit at a time according to the read clock RDCK.

The above-mentioned configuration consisting of four dual-port DRAM1 shift registers 30 and 32 is one of the large-capacity dual-port DRAMs available at the time of filing of the present invention that can be used as screen memory. This is because the time required to write data is approximately four times longer than the time required to read (in other words, display) the data of one pixel on a personal computer display, etc. Dual baud) DR that satisfies write time requirements corresponding to the time required to read or display data
If AM is available, the screen memory 31 in FIG.
can be configured with only one dual-port DRAM,
Shift registers 30 and 32 are no longer needed.

By the way, the synchronizing signal separating circuit 50 includes the synchronizing signal separating means 5. having the configuration shown in FIG. , the raw water rate synchronization signal H1 and the raw vertical synchronization signal V1 included in the television image signal are separated from the television image signal.

The raw water rate synchronization signal H1 and the raw vertical synchronization signal V1 are applied to the write synchronization signal output circuit 60.

The write synchronization signal output circuit 60 is a P
It has a configuration of a LL circuit, generates the write dot clock DCK in synchronization with the raw water rate synchronization signal H1, and generates a horizontal synchronization signal SHI whose phase is precisely synchronized with the write dot clock DCK, and a vertical synchronization signal SHI. Outputs synchronization signal SVI.

The write dot clock DCK, horizontal synchronization signal SHI and vertical synchronization signal SVI are supplied to an address selector 40 (to be described later) and are also applied to a write pixel counter 6i, which controls the horizontal line write to the pixel memory 31. Address WHAD and vertical line write address WVAD are output, and these horizontal line write address 'vV HAD and vertical line write address WVAD are applied to address selector 40.

The write synchronization signal output circuit 60 and the write pixel counter 6i in the configuration of FIG. 3 are similar to the write address generation means 6. FIG. 4 shows a configuration example of the write synchronization signal output circuit 60 and the write pixel counter 6i.

In FIG. 4, a write synchronization signal output circuit 60 includes a write pixel clock generation section 62, a frequency dividing circuit 63, and a comparison circuit 64. In addition, the writing pixel counter 6i
has an AND circuit 65, a 67n horizontal address counter 66, and a vertical address counter 68.

Write pixel clock generator 62, frequency divider circuit 63, and comparator circuit 6 in the write synchronization signal output circuit 60 described above
4 constitutes a PLL circuit as described above, and uses the raw water rate synchronization signal H1 outputted from the synchronization signal separation circuit 50 as a comparison clock, and operates the write dot clock DCK in phase synchronization with the raw water rate synchronization signal H1. Output. The frequency dividing ratio of the frequency dividing circuit 63 is equal to the number of pixels in one line of the input image signal, and is 640 if the number of pixels in one line of the input image signal is 640, for example. Therefore, the period of the write dot clock DCK is 1/640 of the period of the raw water rate synchronization signal H1.

The output of the frequency dividing circuit 63 is a horizontal synchronization signal S whose phase is accurately synchronized with the write dot clock DCK.
Output as HI.

In the write synchronization signal output circuit 60 of FIG. 4, the original vertical synchronization signal V1 is output as is as the vertical synchronization signal SVI.

In the write pixel counter 6i of FIG. 4, the horizontal synchronization signal SHI and a horizontal write period designation signal, which will be described later, are input to an AND circuit 65, and the AND circuit 65 increments the count of the horizontal address counter 66. Output clock. Further, the vertical synchronizing signal SVI and a vertical write section designation signal to be described later are input to an AND circuit 67, and the AND circuit 67 outputs a clock for incrementing the count of the vertical address counter 68.

The horizontal write interval designation signal and the vertical write interval designation signal indicate the address intervals in the horizontal and vertical directions in which valid image data exists in the input image signal. For example, in the example shown in FIG. 6A, , the input image signal is 640 dots in the horizontal direction and 48 dots in the vertical direction.
Accordingly, the horizontal write section designation signal has a region of 0 line, and the write dot clock has a range of 1 to 64.
It is controlled to be valid during 0 dots.

The vertical write section designation signal is a vertical synchronization signal SV
For each output of I, that is, for each field, the horizontal synchronizing signal SHI is controlled to be valid while it is output 1 to 480 times.

The horizontal synchronization signal SHI also serves as an initial value load control input for the horizontal address counter 66, and the vertical synchronization signal SVI serves as an initial value load control input for the vertical address counter 68. For the horizontal address counter 66 and vertical address counter 68, the initial value I of the address output by each counter,
and I2 are applied, and in each counter, the above-mentioned load control manual power becomes effective, so that
The initial value is set. This initial value is, for example, the 6th B
As shown by I and I2 in the figure, the position on the display screen at which the data of the input image signal is shown is set.

With the above configuration, from the horizontal address counter 66 of the write pixel counter 6i in FIG.
(4 dual baud) common to DRAM)
A horizontal line write address WHAD is outputted from the vertical address counter 68, and a vertical line write address WVAD (also common to the four dual baud DRAMs) for the screen memory 31 is outputted.

Read address generating means 9 in the configuration shown in FIG. 1 described above
This configuration is realized by the synchronization signal separation circuit 90, the readout synchronization signal output circuit 91, and the successive pixel counter 92 shown in FIG.

A video signal from a display device, such as a personal computer, on which a read image is to be displayed is supplied to the synchronization signal separation circuit 90 in order to extract the timing of the synchronization signal. In this way, the synchronization signal separation circuit 9
0 separates the raw water rate synchronization signal H2 and the original vertical synchronization signal V2 included in the video signal from the video signal from the personal computer.

The raw water rate synchronization signal H2 and the raw vertical synchronization signal V2 are provided in the configuration 10 provided corresponding to each of the above-mentioned television signal inputs i.
It is supplied as a timing signal to an address selector 12 (described later) in 0I, and is also applied to a read synchronization signal output circuit 91.

The read synchronization signal output circuit 91, as described later,
It has the same PLL circuit configuration as the write synchronization signal output circuit 60, generates the read dot clock RDCK in synchronization with the raw water rate synchronization signal H2, and is accurate to the successive dot clock RDCK. horizontal synchronization signal SH2 that is phase-synchronized with, and vertical synchronization signal SV
Outputs 2.

The read dot clock RDCK, horizontal synchronization signal SH2
and the vertical synchronization signal SV2 is sent to the read pixel counter 92.
The successive pixel counter 92 outputs the read dot clock RDCK as a horizontal pixel read clock, and further outputs a vertical line read address RVAD as an output of the vertical address counter.

The vertical line read address RVAD is applied to the address selector 12.

FIG. 5 shows a configuration example of the readout synchronization signal output circuit 91 and the readout pixel counter 92 in the configuration of FIG. 3.

In FIG. 5, a readout synchronization signal output circuit 91 includes a readout pixel clock generation section 93, a frequency dividing circuit 94, and a comparison circuit 95. In addition, the read pixel counter 92
has AND circuits 96 and 97n and a vertical address counter 98.

The read pixel clock generation section 93, the frequency divider circuit 94, and the comparison circuit 9 in the above read synchronization signal output circuit 91
5 constitutes a PLL circuit as described above, and uses the raw water rate synchronization signal H2 outputted from the synchronization signal separation circuit 90 as a comparison clock, and reads out the dot so as to be phase-synchronized with the raw water rate synchronization signal H2. Outputs clock RDCK. The frequency division ratio of the frequency dividing circuit 94 is equal to the number of pixels in one line of the output image signal, that is, the number of pixels in one line of the screen to be displayed.For example, the number of pixels in one line of the screen to be displayed is 1.
If it is 024, then it is 1024. Therefore, the period of the successive dot clock RDCK is equal to the raw water rate synchronization signal H2.
This is 1/1024 of the period of .

The output of the frequency divider circuit 94 is outputted as a horizontal synchronizing signal SH2 whose phase is precisely synchronized with the read dot clock RDCK.

In the read synchronization signal output circuit 91 of FIG. 5, the original vertical synchronization signal V2 is output as is as the vertical synchronization signal SV2.

In the read pixel counter 92 of FIG. 5, an AND circuit 96 inputs the horizontal synchronizing signal SH2 and a horizontal write section designation signal, which will be described later, and outputs the horizontal pixel read clock RDCK. Also, A
The ND circuit 97 manually inputs the vertical synchronizing signal SV2 and a vertical read section designation signal, which will be described later, and outputs the AND circuit 97.
outputs a clock that increments the count of the vertical address selector.

Further, the vertical synchronization signal SV2 serves as a reset input for the vertical address counter 98.

A configuration 1001 in which the successive address generation means 9 of FIG. 1 according to the present invention is provided for all input image signals 1 to n.
~100. Corresponding to the fact that it is common to ,
The horizontal write section designation signal and the vertical write section designation signal indicate the address sections in the horizontal and vertical directions in which valid image data exists on the entire display screen.

For example, as shown in FIG. 6B, the horizontal write interval designation signal and the vertical write interval designation signal indicate an area of 1024 dots in the horizontal direction and 768 lines in the vertical direction, which corresponds to the entire display screen of the personal computer. , that is, the horizontal write section designation signal is
When the write dot clock is between 1 and 1024 dots,
The vertical write section designation signal is controlled to be valid for each field, that is, for each output of the vertical synchronization signal SV2, when the horizontal synchronization signal SH2 is 1 to 76.
It is controlled to remain valid while it is output eight times.

With the above configuration, the read pixel counter 92 in FIG. 5 outputs the horizontal pixel read clock RDCK, and the vertical address counter 98 outputs the vertical line read address RVAD.

Now, in the configuration of FIG. 3, the display instruction memory lO, the shift register 11n address selector 12, and the
The divide-by-8 circuit 13 corresponds to the display instruction memory II in the configuration shown in FIG. That is, it has a memory area corresponding to the entire display screen of the output image.

In addition, the bus 200 shown in FIG.
A bus 200 and an 8-bit signal line are connected to the display instruction memory 10 of each of the configurations 100t provided for each of the television signal inputs 1 to n from the CPU. If the input image data of the corresponding address is to be displayed, "1" is written, and if it is not to be displayed, "0" is written.

By the way, the display instruction memory 10, like the screen memory 31, is composed of a plurality of dual port DRAMs.
The time required to write to M is longer than the shift register 3 described above.
The display instruction memory 10 consists of eight dual-port DRAMs because the time required to write from 0 to the screen memory 31 is longer. The 8-bit signal lines are connected to the data ports of these eight dual-port DRAMs, respectively.

In addition, the write address (horizontal line write address DIWHA) for the above-mentioned plurality of dual port DRAMs
D and vertical line write address DIWVAD) are also applied from the CPU via the bus 200 and the address selector 12, which will be described later.

In addition, the display instruction memory IO is 8 dual port D
The display instruction memory 10 corresponds to the fact that it consists of a RAM.
An 8-bit shift register 11 is provided on the output side of the dual-port DRAM.
As the clock applied to M, the horizontal pixel readout tally RDCK from the readout pixel counter 92 is 1/
Clock RDC whose frequency is divided by 1/8 by the 8 frequency divider circuit 13
K8 is used.

Here, the address selector 12, on the other hand,
At the same time, the horizontal line write address DIWHAD and the vertical line write address DIWVAD from the read pixel counter 92 are input manually, and the read synchronization signal output circuit 91 inputs the vertical line read address RVAD from the read pixel counter 92 as a timing signal. The horizontal synchronizing signal SH2 and vertical synchronizing signal SV2 outputted by the controller are manually generated. Then, at the readout timing in the display instruction memory IO, the address selector 12 selects and outputs the vertical line readout address RVAD from the readout pixel counter 92 out of the above two types of manual input, and outputs the vertical line readout address RVAD to instruct the display. The address DIAD is applied to the memory 10, and when it is not the read timing, the horizontal line write address DIWHAD and the vertical line write address DIWVAD from the CPU are selected and output and applied to the display instruction memory 10 as the address DIAD.

Furthermore, when it is not the read timing, the address selector 12 sends a data write response signal to the CPU when 8-bit display instruction data is written from the CPU at the address selected by the address selector 12 as described above. Send. In response, the CPU sends out the next 8-bit display instruction data and their write addresses (horizontal line write address DIWHAD and vertical line write address DIWVAD).

However, the address selector 12
At the timing of reading 0, the data write response signal is not sent to the CPU, so the next display instruction data is not sent from the CPU at this time.
Conflict between writing and reading in the display instruction memory IO can be avoided.

8 dual port DRAMs with display instruction memory 10
The data read from the 1/8 frequency dividing circuit 13 is input into the shift register 11 in parallel at the timing of the 1/8 frequency-divided read clock RDCK8. This 8-bit display instruction data is not frequency-divided by 1/8 (
(horizontal pixel) is serially output at the timing of the readout clock RDCK, and is applied as one input of the AND circuit 70 having the configuration shown in FIG. Note that this AND circuit 70 is similar to the display area gate means 71 in the configuration shown in FIG.
This is to realize the following.

Now, returning to the explanation of the configuration on the screen memory 31 side, the address selector 40 receives the horizontal line write address 'vV' from the write pixel counter 6i.
HA D and the vertical line write address WVAD, and also input the vertical line read address RVAD from the read pixel counter 92, and the horizontal synchronization signal outputted by the write synchronization signal output circuit 60 as a timing signal. Input SHI and vertical synchronization signal SV1. Then, at the timing of reading from the screen memory 31, the address selector 40 selects and outputs the vertical line read address RVAD from the read pixel counter 92 from among the above two types of inputs, and outputs the vertical line read address RVAD to the display instruction memory. 31 as the address AD, and when it is not the read timing, the horizontal line write address WHΔD and the vertical line write address WVAD from the write pixel counter 6i are selected and output and applied to the screen memory 31 as the address AD.

A clock RDCK4 obtained by dividing the horizontal pixel readout clock RDCK from the readout pixel counter 92 by 1/4 in the 1/4 frequency divider circuit 34 is applied to the screen memory 31 as a readout timing clock of serial data. At the read timing, the input image data of the line specified by the vertical line read address RVAD is clocked by the 1/4 frequency divided clock RDCK4.
At the timing of , the four dual boat DRAMs
are output from each in parallel and applied to the shift register 32. The shift register 32 receives the 1/4 frequency-divided read clock RDCK4 as a load control signal.
is applied, and these 4-bit data are directly input to the shift register 32. A horizontal pixel readout clock RDCK from the readout pixel counter 92 is also applied to the shift register 32 as a clock that provides timing for serial data readout, and the above 4-bit data is applied to the horizontal pixel readout clock RDCK. It is output serially at the RDCK timing.

The shift register 30 includes the write pixel counter 6
A clock obtained by dividing the write dot clock DCK output by i in a 1/4 frequency dividing circuit 33 to 1/4 is received as a parallel output control signal LO, and when writing to the screen memory 31, the timing of this output control signal LO is The 4-bit input image data held in the shift register 30 is transferred to the write address (horizontal line write address W) output from the address selector 40.
HAD and the vertical line write address (WVAD).

Furthermore, in the case where there is a conflict between writing and successive reading in the screen memory 31, the address selector 40 gives priority to reading and applies the read address (vertical line read address RVAD) to the screen memory 31. . Furthermore, an ineffective (“0”) signal is applied to one of the AND circuits 4i. The AND circuit 4i
As mentioned above, the FIFO memory 20 is
Since the O continuous signal FRD is applied, while this invalid (“0”) signal is applied, the F
New serial output from the IFO memory 20 to the shift register 30 is stopped.

In this way, the data held in the shift register 30 also remains held during the above-mentioned reading time of the screen memory 31.

As mentioned above, the readout time in the screen memory 31 is
When one read cycle is completed, which is shorter than the write time and the write operation is stopped as described above,
The output of the address selector 40 is switched to the write side, the 4-bit output from the shift register 30 is written to the screen memory 31, and the AND circuit 4
The above-mentioned manual power of i also becomes effective, and the FIFO memory 2
Serial data transfer from 0 to the shift register 30 is also started again.

At the read timing, as described above, the 4-bit output data (input image data) from each of the four dual port DRAMs of the screen memory 31 is fed to the read clock RDCK4 whose frequency is divided by 1/4. Accordingly, the 4-bit input image data is input in parallel to the shift register 32, and further, the 4-bit input image data is serially output one bit at a time in response to the horizontal pixel readout clock RDCK, and is applied as the other input of the AND circuit 70. be done.

Each bit of the display instruction data output from the shift register 11 applied to the AND circuit 70 and each bit of the input image data output from the shift register 32 correspond to the same pixel on the display screen. When the display instruction data is valid (“1”), the corresponding input image data can pass through the AND circuit 70, and when the display instruction data is not valid (“0”), the corresponding input image data can pass through the AND circuit 70. The input image data does not pass through the AND circuit 70, and the output of the corresponding AND circuit 70 becomes "0".

Although not shown, the output of the AND circuit 70 is
It is applied as one of the inputs of the OR circuit that realizes the composite image output means 8 in the configuration shown in FIG. 1 described above.

As mentioned above, the configuration of FIG. 3 has multiple input image signals (
an input image signal (TV signal) that is one of 1 to n;
Since only the configuration 100I corresponding to the television signal (TV signal) i is shown, the above-mentioned OR circuit (not shown) has the configurations 1001 to 100I corresponding to all the input image signals (TV signal) 1 to n.
100. It has n parallel inputs corresponding to the outputs of the AND circuits 70 provided therein.

Then, the output of the OR circuit becomes an image signal to be displayed on the display screen, that is, an output image signal.

〔Effect of the invention〕

According to the present invention, it is possible to simultaneously display predetermined regions of a plurality of input image signals having different scanning frequencies on one display device having further different scanning frequencies.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a functional explanatory diagram of a display instruction memory, FIG. 3 is a configuration diagram of an embodiment of the present invention, and FIG. 4 is a circuit configuration for generating a write address. FIG. 5 is a diagram showing an example of a circuit configuration for generating a read address; FIG. 6A is a diagram showing an example of an input screen; and FIG. 6B is a diagram showing an example of a display screen. It is a diagram. [Explanation of symbols] 1□, 1□, ~1n. ...Display instruction memory, 2i, 2
□, ~2°...buffer means, 3□, 32. ~3o・
...Screen memory, 4i. 4□, ~4n...Write timing control means, 51°5i, ~Milk...Synchronized output separation means, 6. , 62. ~6h...Write address generation means, ? ,, 72. ~7o...Display area gate means,
8... Composite image output means, 9... Read address generation means, 10... Display instruction memory, 11... Shift register, 12... Address selector, 13... 1
I8 frequency divider circuit, 20...FIFO memory, 30.32
...Shift register, 31...Screen memory, 33n
34... 1I4 frequency divider circuit, 40... Address selector, 4i... AND circuit, 50... Synchronous signal separation circuit, 60... Synchronous signal output circuit for writing, 6i...
Write pixel counter, 62... Write pixel clock generation section, 63... Frequency divider circuit, 64... Comparison circuit, 65
゜67...AND circuit, 66...Horizontal address counter, 68...Vertical address counter, 70...A
ND circuit, 90... Synchronization signal separation circuit, 91... Readout synchronization signal output circuit, 92... Readout pixel counter, 93... Readout pixel clock generation section, 94...
Frequency dividing circuit, 95... Comparison circuit, 96.97... AN
D circuit, 98... Vertical address counter, 110...
・A/D converter, 200...bus. Figure 6A shows an example of a graphical display screen (reading screen) showing one message on the vertical input screen (writing screen) during the vertical input period Figure 6B

Claims (1)

[Claims] 1. For each (i) of a plurality of input image signals, a display instruction memory (1_i), a screen memory (3_i), a write timing control means (4_i), and a synchronization signal separation means ( 5
__i), a write address generation means (6_i), and a display area gate means (7_i), and a read address generation means (9) common to the plurality of input image signals.
and a composite image output means (8), and the read address generation means (9), which is provided in common for the plurality of input image signals, is configured to output a composite image from the display instruction memory (1).
_i) (1_1, 1_2, ... 1_n), and all (3_1, 3_2) of the screen memory (3_i)
, . . 3_n) at the same time at a predetermined timing, and the composite image output means (8) applies a common read address to all the display area gate means (7_1,...3_n) at a predetermined timing.
7_2, . The synchronization signal is separated from the signal, and the write address generation means (6_i) generates a write address to the screen memory (3_i) at the timing of the corresponding synchronization signal, and the buffer means (2_i) respectively It is provided before the corresponding screen memory (3_i) to temporarily hold the input image signal, and the screen memory (3_i)
i) are the respective corresponding buffer means (2_i)
The input image signal outputted from the write timing control means (4_i) is written according to the write address.
) are respectively corresponding write address generation means (6_
i) of the screen memory (3_
i) and the timing of output of the input image signal from the buffer means (2_i) are controlled so that they do not overlap with the timing of application of the read address, and the display instruction memory (1_i) , instructs an area to be displayed as an output image among the corresponding input image signals, and controls the display area gate means (7).
__i) are the corresponding display instruction memories (1_
A scan conversion circuit characterized in that it controls application of the output from each address of the screen memory (3_i) to a subsequent stage based on the instruction of (i).