JPH11112873A - Image processing method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with various applications by small-scale circuit constitution and to efficiently perform a high-grade image processing. SOLUTION: An image processor as this device is provided with an input part 40 for fetching image data from the outside, an SVP 14 for inputting, processing and outputting the image data by a scanning line unit, an image memory 50 for writing and reading the image data by the scanning line unit, an output part 70 for outputting the processed image data to the outside and a data path 72 for mutually connecting the input part 40, the SVP 14, the image memory 50 and the output part 70. A program memory 10 stores a program for the SVP 14 and an instruction generation circuit 12 supplies the control signals of a microinstruction or the like to the SVP 14. A timing control unit 74 supplies required timing control signals to the input part 40, the SVP 14, the image memory 50, the output part 7 and an IG 12. A ROM loader 76 and an I<2> C bus interface circuit 78 distribute program data through an internal bus 80 to program data holding parts (memory and register, or the like), distributed and arranged at respective parts inside the image processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0010]

The present invention relates to an image processing technique, and more particularly to an image processing method and apparatus for performing digital image processing on a video signal such as a television signal.

[0020]

2. Description of the Related Art A conventional image processing apparatus of this type is shown in FIG.
As shown in the figure, in addition to a digital signal processing circuit 200 configured to perform predetermined image processing on a video signal, one or a plurality of signals for accumulating or delaying image data by one field or one frame are provided. A field memory and / or a frame memory 202.

For example, in the case of moving image real-time processing, the frame memory 202A and the field memory 2
02B is used for motion detection, and the frame memory 202C
Are used for motion adaptive interpolation. Further, for example, another frame memory (not shown) is used for time axis conversion for converting a Hi-Vision signal into an NTSC signal.

[0040]

As described above, the conventional digital image processing circuit requires a larger number of field memories or frame memories as the number of types of required image processing increases. This is a major disadvantage in cost and equipment scale. A general field memory and a frame memory are dynamic RAMs having a capacity of 1 to 2 Mbits. Although the storage capacity is remarkably small as compared with the current mainstream 16 Mbit and 64 Mbit dynamic RAMs, they are much smaller in terms of price and chip size. No different.

On the other hand, as the number of field memories and / or frame memories increases, the number of terminal pins on the side of the digital signal processing circuit 200 increases in proportion to the number.
There is also a disadvantage that the size of the C package increases.

In addition, such a system configuration has a problem that adaptability to various applications is poor. For example, even if a system is constructed using a field memory of 1.5 Mbit capacity for NTSC signals, a field memory of about 4 Mbits is required for Hi-Vision signals, so this system cannot be applied. .

Each of these many field memories and / or frame memories has a limited or specialized application in connection with a processing section having a specific function in the digital signal processing circuit 200, and is generally used for various applications. There is a problem that it can not have.

For this reason, conventionally, if one TV receiver is intended to support various video signals such as NTSC signals, satellite broadcasts, high-definition signals, and personal computer output signals, a dedicated digital signal for each type of video signal is required. All of the processing circuits and the field / frame memory had to be built in, resulting in a very expensive and large device.

The present invention has been made in view of the above-mentioned problems, and has as its object to provide an image processing method and apparatus which can respond to various applications with a small circuit configuration.

It is another object of the present invention to provide an image processing method and apparatus capable of efficiently utilizing the resources in the apparatus and efficiently performing advanced image processing.

[0110]

In order to achieve the above object, according to the first aspect of the present invention, there is provided an input unit for receiving image data to be processed from the outside, and one pixel on a scanning line. A digital signal processing unit having a plurality of processing elements assigned in a one-to-one correspondence relationship and performing the same operation according to a common instruction, for inputting, processing, and outputting image data in units of scanning lines; An image memory having a memory area, capable of executing a write operation and a read operation in parallel and independently, inputting and outputting image data in units of scanning lines, and an output unit for outputting processed image data to the outside Data path means for interconnecting the input section, the digital signal processing section, the image memory and the output section, and the input section and the digital signal processing section. Parts, the image memory, the output section and the data paths are those related to the image processing apparatus and a control means for controlling in accordance with the desired program data.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the digital signal processing section converts one or a plurality of image data corresponding to one or a plurality of video signals in parallel. A data input unit for inputting in units of scanning lines, and a data output unit for outputting one or more image data processed in units of scanning lines by the processing element in units of scanning lines in parallel; The data input operation of each scanning line in the input unit, the processing operation of each scanning line in the processing element, and the data output operation of each scanning line in the data output unit are performed in a pipeline manner.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, the image memory includes: a data writing unit that sequentially writes input image data in the memory area at a continuous address; Data reading means for sequentially reading image data to be read from the memory area at successive addresses; and pointer control means for controlling a write pointer and a read pointer for respectively indicating a write address and a read address for the memory area in accordance with the program data. Configuration.

According to a fourth aspect of the present invention, in the image processing apparatus of the third aspect, the image memory has a plurality of input buffers including at least two input buffer units having a predetermined storage capacity. In each of the input buffers, when the first input buffer unit is filled with the image data, the writing of the input image data to the second input buffer unit is started, and the image data is transferred from the first input buffer unit. When the read data is read and written into the memory area and the second input buffer unit is filled with the image data, the writing of the input image data to the first input buffer unit is started and the second input buffer unit is started. The image data is read out and written into the memory area.

According to a fifth aspect of the present invention, in the image processing apparatus of the fourth aspect, the data rate at which image data is written from each of the input buffers to the memory area is such that the image data is written to each of the input buffers. The speed is selected to be different from the writing data rate.

According to a sixth aspect of the present invention, in the image processing apparatus of the third aspect, the image memory has a plurality of output buffers including at least two output buffer units having a predetermined storage capacity. In each of the output buffers, when the image data in the first output buffer unit becomes empty, reading of the image data from the second output buffer unit is started, and the image data read from the memory area is output. When the image data written to the first output buffer unit is emptied and the image data in the second output buffer unit becomes empty, the reading of the image data from the first output buffer unit is started and the image read from the memory area is started. Data is written to the second output buffer unit.

According to a seventh aspect of the present invention, in the image processing apparatus according to the sixth aspect, the data rate at which image data is written from the memory area to each of the output buffers is such that the image data is written from each of the output buffers. The speed is selected to be different from the read data rate.

According to an eighth aspect of the present invention, in the image processing apparatus of the first aspect, the data path means electrically connects a data output terminal of the input section and a data input terminal of the digital signal processing section. A first data path section for connection, a second data path section for electrically connecting a data output terminal of the input section and a data input terminal of the image memory, and a digital signal processing section. A third data path section for electrically connecting a data output terminal to a data input terminal of the image memory; and electrically connecting a data output terminal of the image memory and a data input terminal of the digital signal processing section. A fourth data path unit for connection, a fifth data path unit for electrically connecting a data output terminal of the input unit and a data input terminal of the output unit, A sixth data path unit for electrically connecting a data output terminal of the digital signal processing unit and a data input terminal of the output unit; and a data output terminal of the image memory and a data input terminal of the output unit. And a seventh data path section for electrical connection.

According to a ninth aspect of the present invention, in the image processing apparatus of the eighth aspect, the first to seventh data paths are all formed on the same semiconductor chip.

According to a tenth aspect of the present invention, in the image processing apparatus according to the first aspect, the control means includes the input unit, the digital signal processing unit, the image memory, the output unit, and the data path. Program data holding means distributed in each section for holding program data defining each operation mode of the means, and program data distribution for taking in desired program data from outside and distributing the program data to the program data holding means in each section Means.

[0210] According to an eleventh aspect of the present invention, in the image processing method for processing image data by the image processing apparatus of the first aspect, a step of taking in image data corresponding to one video signal into the input unit, Inputting the image data output from the input unit to the digital signal processing unit and performing a first process; and storing the image data output from the digital signal processing unit after the first process in the image memory. Writing and temporarily storing the image data; and inputting the image data read from the image memory to the digital signal processing unit again to perform a second process.

According to a twelfth aspect of the present invention, in the image processing method according to the eleventh aspect, the image data output from the digital signal processing unit after the second processing is written into the image memory to temporarily store the image data. Remembering;
Inputting the image data read from the image memory to the digital signal processing unit again to perform a third process.

According to a thirteenth aspect of the present invention, in the image processing method for processing image data by the image processing apparatus according to the first aspect, a step of taking in image data corresponding to one video signal into the input unit, Writing the image data output from the input unit to the image memory and temporarily storing the image data; and converting the image data from the input unit and the image data read from the image memory into the digital signal in parallel. Inputting to the processing unit and performing a predetermined process with the image data.

According to a fourteenth aspect of the present invention, in the image processing method of the thirteenth aspect, image data is read out from the two output ports of the image memory by shifting the time by a desired delay amount, and is read out in parallel. The digital signal processing section inputs the predetermined processing between the two image data from the image memory and the image data from the input section in the digital signal processing section.

According to a fifteenth aspect of the present invention, in the image processing method for processing image data by the image processing apparatus according to the first aspect, image data corresponding to one video signal is converted to a partial pixel on each scanning line. And / or temporarily storing only some scanning lines on each field in the image memory, and reading image data in the order of pixels and scanning lines written from the image memory.

[0260] According to a sixteenth aspect of the present invention, in the image processing method for processing image data by the image processing apparatus according to the first aspect, image data corresponding to one video signal is temporarily written to the image memory. And reading the image data intermittently from the image memory in pixel units or scan line units, and inputting the image data read from the image memory to the digital signal processing unit, Interpolating image data for pixels or scanning lines skipped at the time of intermittent reading of the image memory.

According to a seventeenth aspect of the present invention, there is provided an image processing method for processing image data by the image processing apparatus according to the first aspect, wherein the first and second image signals respectively correspond to two video signals which are not synchronized with each other. Capturing the first image data into the input unit, writing the first image data output from the input unit into the image memory and temporarily storing the first image data, and storing the second image data output from the input unit.
Simultaneously reading the first image data from the image memory in synchronization with the second image data and inputting the first image data to the digital signal processing unit; Performing predetermined processing on the first and second image data input in synchronization with each other in the processing unit.

According to an eighteenth aspect of the present invention, in the image processing method for processing image data by the image processing apparatus according to the first aspect, the first and second image signals respectively corresponding to two video signals that are not synchronized with each other. Capturing the image data into the input unit, inputting the first image data output from the input unit to the digital signal processing unit and performing predetermined processing, and outputting the image data from the digital signal processing unit. Simultaneously inputting the first image data to the image memory and inputting the second image data output from the input unit to the image memory, and excluding a synchronization signal related to the first and second image data. Reading the first and second image data from the image memory in synchronization with the synchronization signal.

According to a nineteenth aspect of the present invention, in the image processing method for processing image data by the image processing apparatus according to the first aspect, a step of inputting image data corresponding to one video signal to the input unit; Inputting the first half of the image data output from the input unit to the digital signal processing unit in a first period, writing the image data output from the input unit to the image memory, and setting a predetermined delay time Reading the image data later, and inputting the latter half of the image data read from the image memory to the digital signal processing unit in a second period.

According to a twentieth aspect of the present invention, in the image processing method according to the nineteenth aspect, the first half of the image data output from the digital signal processing section is written into the image memory and read after a predetermined delay time. Steps and
Outputting the first half of the image data read from the image memory to the outside from the output unit, outputting the second half of the image data from the digital signal processing unit, and outputting the second half of the image data from the digital signal processing unit. Connecting the second half of the image data to the first half of the image data and outputting the data to the outside from the output unit.

According to a twenty-first aspect of the present invention, in the image processing method according to the twentieth aspect, the rear end of the first half of the image data input to the digital signal processing unit during the first period is Adding a first overlap portion that overlaps the front end of the second half by a predetermined number of pixels; and the front end of the second half of image data input to the digital signal processing unit during the second period. A second portion overlapping the rear end of the first half by a predetermined number of pixels.
And a step of removing the first and second overlapped portions at the stage of outputting image data to the outside from the output unit.

According to a twenty-second aspect of the present invention, in the image processing method for processing image data by the image processing apparatus according to the first aspect, image data corresponding to one video signal is taken into the input section, and Performing a low-pass filtering process in a unit, and performing a decimation process for inputting image data output from the input unit to the digital signal processing unit or the image memory and compressing the image data. .

[0330]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a circuit configuration of an image processor according to one embodiment of the present invention.

The image processor includes an input section 40 for externally receiving a digital video signal as image data to be processed, an image data input for each scanning line,
Process and output SVP (Scan-line Video Processo)
r) 14, an image memory 50 for writing and reading image data in units of scanning lines, an output unit 70 for outputting the processed image data to the outside, and an input unit 40, SVP1
4, a data path 72 for interconnecting the image memory 50 and the output unit 70.

The image processor has an SV
P14 to SIMD (Single-Instruction Multiple-Dat
To operate as a) type digital signal processing unit,
A program memory 10 comprising a RAM for holding a program for the VP 14; and an instruction generating circuit (I) for fetching instructions one by one from the program memory 10 and providing a control signal such as a micro instruction corresponding to the instruction to the SVP 14.
G) 12 are provided.

Further, the image processor is provided with a timing control unit (TCU) 74 for supplying a required timing control signal to the input section 40, the SVP 14, the image memory 50, the output section 70 and the IG 12.

[0370] Each part in the image processor, that is, the input part 40, the SIMD type digital signal processing part (10, 12, 14), the image memory 50, the output part 70, and the program data holding part distributed in the IG12. It also includes a ROM loader 76 and an I ² C bus (Inter IC-BUS) interface circuit 78 for distributing external program data to (memory, registers, etc.) via an internal bus 80. Although not shown, a clock circuit including, for example, a PLL circuit for supplying a required clock to each unit in the processor is also included.

Here, the program data holding unit of the SIMD type digital signal processing unit is the program memory 10. The I ² C bus interface circuit 78 is connected to an external controller (not shown) according to the I ² C bus standard, receives program data from the controller by, for example, serial transmission, and transmits the received data. After the data is converted into parallel data, the corresponding program data portion is transferred to the designated destination (program holding unit).

The ROM loader 76 is connected to an external ROM (not shown). Upon receiving a desired program number from an external controller via the I ² C bus interface circuit 78, the ROM loader 76 assigns this program number. The data of the specified application program is read from the external ROM and loaded into the program data holding unit of each unit. The ROM loader 76 has an external RO
Although M is involved, there is an advantage that program data can be distributed in a much shorter required time than a method of distributing program data to each unit via an I ² C bus interface circuit 78 by an external controller.

FIG. 2 shows a specific configuration example of a data path in the image processor. As shown, SV
Multiplexers 82, 84, and 86 are arranged in front of the input terminals of the P14, the image memory 50, and the output unit 70.

In this example, the input section 40 is capable of simultaneously receiving, for example, a 16-bit digital video signal from the outside as image data SV to be processed by this processor, up to a maximum of two systems. The SVP 14 has an input port for simultaneously inputting up to three digital video signals (hereinafter referred to as image data) and a maximum of three digital video signals.
And an output port for simultaneously outputting up to three image data. The image memory 50 has three input ports and input buffers SDIA, SDIB, and SDIC for simultaneously inputting up to three image data, three output ports for simultaneously outputting up to three image data, and Output buffer SDOA, SDOB, SD
And OC.

The output ports for the two channels of the input unit 40 are connected to the input terminals of the first multiplexer 82 and to the input terminals of the second multiplexer 84. Among the output ports for the three channels of the SVP 14, first and second output ports are connected to input terminals of a second multiplexer 84, and first and third output terminals are input terminals of a third multiplexer 86. It is connected to the. Of the output ports for the three channels of the image memory 50, the first to third output ports are connected to the input terminals of the multiplexer 82, and the first and second output ports are connected to the input terminals of the multiplexer 86. ing.

From the output of the multiplexer 82, output terminals for three channels are connected to the input ports of the SVP 14. From the output of the multiplexer 84, output terminals for three channels are connected to input terminals of the image memory 50. On the output side of the multiplexer 86, output terminals for two channels are connected to input ports of the output unit 70.

In this data path structure, SVP14
The input port and the output port of the image memory 50 are connected to each other via multiplexers 82 and 84 in a cross-linked relationship. Each multiplexer 82, 8
Switching between 4,86 is controlled by a timing control signal from TCU74.

FIG. 3 shows a circuit configuration example of the input section 40.
In this example, four input sections 40A, 40A corresponding to the luminance signal (Y) and the chrominance signal (C) of the input video signals for two systems.
40B, 40C, and 40D are provided. Each input has a buffer 42, a filter 44, a multiplexer 46
And a setting value register 48 are provided. After the input image data is once taken into the buffer 42,
Depending on the switching position of the multiplexer 46, the signal is output directly through the multiplexer 46, or is output through the multiplexer 46 after being subjected to a low-pass filtering process in the filter 44, for example, for band limiting.

The switching of the multiplexer 46 and the filtering processing of the filter 44 are performed by the ROM loader 76 or the I ² C bus interface circuit 78 via the internal bus 80 as described above, and the set value register 48 of this input section is used. Is controlled by a set value input (loaded), that is, program data PD and a timing control signal TC from the TCU 74.

1 and 2, the SVP 14 has a three-layer structure of a data input register (DIR) 16, a processing element section (processing section) 18, and a data output register (DOR) 20.

[0480] Fig. 4 shows an example of the internal configuration of the SVP 14.

The DIR 16 operates in accordance with the timing control signal from the TCU 74, the clock from the clock circuit, and the address (ADDRESS) from the IG 12 and has a maximum of three.
Image data D1 to DN up to channels (for example, 48 bits) are repeatedly input in units of scanning lines.

The processing section 18 calculates the number N of pixels on one horizontal scanning line.
(For example, 864) of processing elements PE1 to PEN are arranged (connected) in parallel. These processing elements PE1, PE2,.
EN operates in parallel according to the address (ADDRESS) from the IG 12 and the microinstruction (MICROINSTRUCTION) and the clock from the clock circuit, and performs the same image processing operation for each of the corresponding pixel data D1, D2,. Run within the period.

The DOR 20 operates according to the control signal from the TCU 74, the clock from the clock circuit, and the address (ADDRESS) from the IG12, and outputs the data of the arithmetic processing results from the processing elements PE1 to PEN every horizontal scanning period. The image data is output in alignment with image data D1 'to DN' of one horizontal scanning line for up to three channels.

DIR 16, processing unit 18, and DOR 20
May be asynchronous to each other. The data transfer from the DIR 16 to the processing unit 18 and the data transfer from the processing unit 18 to the DOR 20 are performed within the horizontal blanking period.

As described above, the data input, parallel operation processing, and data output for one horizontal scanning line are executed asynchronously and in parallel by the pipeline system by the DIR 16, the processing unit 18, and the DOR 20, respectively, and real-time image processing is performed. Will be

[0540] Here, the internal operation of the SVP 14 will be schematically described with reference to FIG. The operation of each part in the SVP 14 is as follows.
As described above, it is controlled by the address (ADDRESS) from the IG 12, the micro instruction (MICROINSTRUCTION), the timing control signal from the TCU 74, the clock from the clock circuit, and the like.

In FIG. 4, the DIR 16 has a storage capacity capable of taking up to three channels of input image data VS (D1 to DN) for one line, and is divided into pixels. The input image data D1 to DN are DIR1
6, DK-2, DK-1, while the pixel data is being transferred.
DK, DK + 1, DK + 2,... Are sequentially deducted one by one so that each block of the DIR 16, K-2, K-1,.
K, K + 1, K + 2,...

Each of the processing elements PEK of the processing section 18 has a predetermined capacity (for example, 176 bits).
A pair of register files RF0, RF1 and 1
1-bit arithmetic logic unit (ALU) 24 and a plurality (for example, 4) of working registers WRs
(M, A, B, C) 26 and a plurality (for example, four on each side) of adjacent left and right processing elements (PEK-4, PK-4).
EK-3, PEK-2, PEK-1, PEK + 1, PEK + 2, PEK + 3, P
EK + 4) and an L / R (left / right) communication unit (LRCOM) 28 for exchanging data with the EK + 4).

[0570] One register file RF0 is DIR
The other register file RF1 is connected to the register group of the corresponding block of the DOR 20, and the other register file RF1 is connected to the register group of the corresponding block of the DOR20. 1 read from one or both of register files RF0 and RF1
Bit data is stored in the working registers (M, A,
B, C) and four adjacent left and right processor elements (P) via the multiplexer 30 and the latch circuit 32 of the L / R communication unit 28.
EK-4, PEK-3, PEK-2, PEK-1, PEK + 1, PEK + 2, P
EK + 3, PEK + 4).

At the same time, each processor next to them
Element (PEK-4, PEK-3, PEK-2, PEK-1, PE
K + 1, PEK + 2, PEK + 3, PEK + 4) are also sent to the multiplexers 34, 36 of the L / R communication unit 28 of the processor element PEK, and any of the data is One of them is selected and inputted to one of the working registers (M, A, B, C). In FIG. 4, the processor elements (PEK-4, PEK-3, PEK-3,
PEK-2, PEK-1) indicates that one of the data is selected and input to the working register (A).

The ALU 24 executes a required operation on the data provided from the working registers (M, A, B, C) and outputs the operation result. ALU24
The data of the operation result of register files RF0 and RF
Written to one of 1 Generally, the data of the last operation result in each horizontal scanning period is output as the final operation processing result pixel data DK ′ as the output side register file RF.
And is transferred from the register file RF to the register of the corresponding block of the DOR 20 during the horizontal blanking period immediately thereafter.

The DOR 20 outputs the output image data D1 'to DN'.
And has a capacity equal to the number of channels, the number of bits, and the number of pixels, and is divided into pixels. The pixel data VS '(D1' to DN ') resulting from the arithmetic processing sent from the processing unit 18 to the DOR 20 for each block takes the pixel data D1' at the left end at the head over one horizontal scanning period and succeeding pixel data DOR2 so that D2 ', D3', ... follow the rosary
0 is sent from each block.

The processing section 18 can store one or two lines of image data in the register files RF0 and RF1, thereby realizing the function of a line memory. Further, the processing unit 18 can also execute individual processing in a time-division manner on image data of a plurality of channels during one horizontal scanning period.

FIG. 5 shows a specific configuration example of the image memory 50. The image memory 50 is, for example, an SDRAM (Synchronous) as a high-speed memory for temporarily storing image data.
ousDynamic Random Access Memory) 52 is used. The SDRAM 52 has a storage capacity of, for example, about 16 Mbits, and a memory area is mapped in a continuous address space. During memory access, this SDRA
M52 has memory address and control signals (RAS, C
AS), a high-speed clock CK is also supplied, and SDRA
M52 strobes data at the timing of the clock CK.

In this image memory 50, SDRAM
Portions other than 52 constitute an interface unit (SDRAM interface).

Each input buffer SDIA, SDIB,
SDIC and respective output buffers SDOA, SDOB
, SDOC are provided with write (W) pointer registers 54 and 58 for giving pointing information indicating a write address (position) in each buffer, and read (W) for giving pointing information for indicating a read address (position) in the buffer. R) Pointer registers 56 and 60
And are attached. Each read pointer register 56 on the input side also has a write address generation function for SDRAM access. Each write pointer register 58 on the output side also has a read address generation function for SDRAM access.

Each input buffer SDIA, SDIB, SD
The output terminal of IC is connected to the data input terminal of SDRAM 52. The SDRAM address generated by each read pointer register 56 on the input side is applied to the address terminal of the SDRAM 52 via the multiplexer 62. The SDRAM address generated by each write pointer register 58 on the output side is output to the multiplexers 64 and 6.
2 to the address terminal of the SDRAM 52.

[0660] The control unit 66 stores the program data defining the operation mode of the image memory 50 in the ROM loader 76.
Or a setting value register received from an external controller via the I ² C interface circuit 78 and held. The control unit 66 operates the buffers and pointer registers on the input and output sides according to the program data set and input to this register and various timing control signals from the TCU 74,
2, 64 switching and memory access to the SDRAM 52 are controlled.

In the image memory 50, each of the input buffers SDIA, SDIB, and SDIC has a storage capacity of 128 pixels, for example, using 16 bits of image data of one pixel, and the storage capacity of the first and second buffers. Are divided into two.

Referring to FIG. 6, each input buffer SDIA, S
The write / read operation in DIB and SDIC will be described. First, data is written into the first (left side) input buffer in order from the head address (FIG. 6A). The write pointer PW is incremented according to a clock synchronized with the input image data VS.

When the first input buffer is filled with the input image data, the write pointer PW points to the head address of the empty second (right) input buffer, and the write pointer PW returns to the second input buffer. At the same time as the writing of the input image data is started, the read pointer PR points to the head address of the first input buffer unit, and the reading of the input image data from the first input buffer unit is started (FIG. 6). (B)).

The image data read from the input buffer is supplied to the data input terminal of the SDRAM. on the other hand,
The memory address generated by the address generation function of the read pointer register 56 is supplied to the address terminal of the SDRAM 52 via the multiplexer 62 simultaneously with the output of the image data to the data terminal of the SDRAM. The address value is incremented together. The control unit 66 selectively activates the read operation of each of the input buffers SDIA, SDIB, and SDIC by an arbitration function.

The read pointer PR is synchronized with the data write clock for the SDRAM 52. While the transmission speed of normal image data is 10 MHz, SDR
The operation clock CK of AM is several times or more, for example, 80M
Hz. Therefore, in each input buffer,
The read pointer PR is incremented at a speed several times faster than the write pointer PW, and the reading is performed at a data rate several times faster than the writing (FIG. 6C).

Therefore, before the writing to the second input buffer section is completed, the writing from the first input buffer section is completed, and the read pointer PR waits at the boundary position as it is ((D) in FIG. 6). ). Then, when the writing to the second input buffer unit is completed ((E) in FIG. 6),
The read pointer PR indicates the start address of the second input buffer unit, and starts reading from the second input buffer unit. On the other hand, the write pointer PW returns to the head position of the first input buffer unit in an empty state (a state in which all image data has been read), and restarts writing to the first input buffer unit. Thereafter, the above operation is repeated.

The read pointer PR only needs to read out all the data in the input buffer filled with data.
The reading order does not necessarily have to be the same as the write pointer PW. In this case, the write order of the write point PW in the output buffer described later follows the read order of the read pointer PR in the input buffer.

In this image memory 50, each output buffer SDOA, SDOB, and SDOC also has a pixel 128
And has a storage capacity of the first and second storage capacity.
Are divided into two output buffer units.

Referring to FIG. 7, each output buffer SDOA, S
The write / read operation in DOB and SDOC will be described. The operation of the output buffer is basically the same as the operation of the input buffer described above.

First, the data is written into the first (left) output buffer in order from the head address (FIG. 7A). here,
The data to be written is image data read from the SDRAM 52, and the write pointer PW is
Increment in synchronization with the second high-speed clock CK.

The memory address generated by the address generation function of write pointer register 58 is S
The data is supplied to the address terminal of the SDRAM 52 via the multiplexers 64 and 62 in synchronization with the read clock of the DRAM 52, and at the same time, the address value is incremented.

[0780] The control unit 66 controls each output buffer SDOA,
The write operations of SDOB and SDOC are selectively activated by an arbitration function. Further, the control unit 66 controls the output buffers SDOA, SDOB, S
Arbitration is also performed between the write operation of DOC and the read operation of each of the input buffers SDIA, SDIB, and SDIC as described above.

When the first output buffer unit is filled with the output image data, the write pointer PW stands by at the end position. When reading of the output buffer starts,
First, the read pointer PR points to the head address of the first output buffer unit, and the output image data is read from the first output buffer unit (FIG. 7B). At the same time, writing of the output image data to the second output buffer unit is started. The read pointer PR increments in synchronization with a clock corresponding to the transmission rate of the image data set or selected by the control unit 66. However, it is slower than the write pointer PW.

Therefore, before the reading from the first output buffer section is completed, the writing to the second output buffer section is completed, and the write point PW stands by at the end position ((C) in FIG. 7). , (D)).

[0810] When the reading from the first output buffer section is completed ((E) in FIG. 7), the read pointer PR is read.
Indicates the start address of the second output buffer unit,
From the output buffer unit is started. On the other hand, at this time, the write pointer PW returns to the head position of the first output buffer unit, and resumes writing to the first output buffer unit. Thereafter, the above operation is repeated.

As described above, the image memory 5 of this embodiment is
0, the image data for a plurality of channels are respectively input to a plurality of input ports or input buffers SDIA, SDIB
, SDIC can be input in parallel, synchronously or asynchronously, and image data for a plurality of channels are respectively output to a plurality of output ports or output buffers SDOA, SDOB,.
Synchronous or asynchronous parallel output from SDOC is possible.

In the memory 50, a single interface unit, in particular, the control unit 66, exchanges image data between the common SDRAM 52 and each of the input buffers SDIA, SDIB, SDIC and each of the output buffers SDOA, SDOB, SDOC. Can be efficiently controlled by unitary management in synchronization with the high-speed clock CK.

This image processor can be constructed on a single semiconductor chip. Even when the SDRAM 52 is externally mounted, the number of terminal pins is small, and the size of the device can be reduced.

[0850] Then, coupled with a plurality of input / output ports,
A plurality of write pointers and read pointers are provided, the relationship between the pointers can be set programmably, and a wide variety of memory functions can be realized.

For example, as shown in FIG. 8, image data for one channel is input to one input buffer, for example, SDI.
A is written to the SDRAM 52 via A
The first and second output buffers SDOA are obtained by shifting the image data written in the RAM 52 by a predetermined delay time.
, SDOB, it is possible to simultaneously obtain, for example, image data delayed by one field and image data delayed by two fields.

In FIG. 8, the write address (pointer) AW for the SDRAM 52 corresponds to the read pointer PR in the input buffer, and the two read addresses (pointers) ARa, ARb correspond to the output buffers SDOA,
This corresponds to the write pointer PW in SDOB.

In this embodiment, the SDRAM is stored in the image memory 50.
Although 52 is used, any other memory may be used as long as it has a memory function equivalent to this. For example, a Rambus memory of a Rambus company specification can be used. Further, the image memory 50 can be composed of a plurality of memory chips.

[0890] Fig. 9 shows a specific configuration example of the TCU 74. The TCU 74 includes a main controller (MC), a vertical timing generator (VTG), and a horizontal timing generator (H
TG), and each section in the apparatus, that is, the input section 40, the SIMD type digital signal, in response to the vertical synchronization signal, the horizontal synchronization signal, and the pixel clock extracted from the video signal (image data VS) input to the input section 40. Signal processing unit (10, 1
2, 14), a required timing control signal TC is supplied to the image memory 50, the output unit 70, the data path 72 (multiplexers 82, 84, 86) and the like.

The main controller MC comprises a program counter, a program memory, a control logic, etc., and responds to a vertical synchronizing signal by a frame-based timing control signal TC.
MC and an internal vertical timing generator V
The TG and the horizontal timing generator HTG are controlled. The vertical timing generator VTG includes a sequence memory VSM
And a line memory VLM to generate a line-based timing control signal TCVTG and an internal control signal in response to the horizontal synchronization signal. Horizontal timing generator HT
G is the sequence memory HSM and the loop memory HL
M, etc., and generates a pixel-based timing control signal TCHTG in response to the pixel clock.

[0910] Main control unit MC, vertical timing generation unit VT
Various programs such as a program memory and a sequence memory of the G and horizontal timing generator HTG store various program data supplied from the ROM loader 76 or the I ² C interface circuit 78 via the internal bus.

[0920] The output unit 70 includes an output buffer, a circuit for inserting a blanking signal into output image data, and the like. The function of this output unit 70 is also
Alternatively, control is performed according to program data provided from the I ² C interface circuit 78 via the internal bus and a timing control signal TC from the TCU 74.

Next, the overall operation of the image processor of this embodiment will be described.

[0940] Fig. 10 shows, as an example, functional blocks when a moving image real-time process is performed by this image processor.

In this moving image real-time processing system, the two field memories 90 and 92 in the input stage store 1
One frame memory. The subtracter 94 calculates a difference △ between the input image data VS and the image data output from the field memory 92, and calculates the difference △ as an absolute value circuit (A
By passing the signal through the BS) 96 and the non-linearization circuit 98, a signal △ S representing the degree of change between the current screen and the screen one frame before is obtained for each pixel.

Next, the signal $ S is transferred to the line memory 100
The signal passes through a two-dimensional averaging circuit consisting of a field memory 104 and an adder 108 and a two-dimensional averaging circuit consisting of a field memory 104 and an adder 108, thereby performing three-dimensional low-pass filtering to remove noise. Then, a motion detection signal K (0 ≦ K ≦ 1) is obtained.

On the other hand, moving image processing is performed by passing the input image data VS through a vertical averaging circuit comprising a line memory 110 and an adder 112. This video processing unit 11
4, the multipliers 116 and 118 and the coefficient converter 12
0, a motion compensation mixing circuit 124 comprising an adder 122
Is provided.

[0980] When the motion detection signal K is 1, the motion detection amount is the maximum, and the image data from the moving image processing section 114 is output as it is through the multiplier 116 and the adder 122. At this time, the image data delayed by one field from the field memory 90 is blocked by the multiplier 118.

On the other hand, when the motion detection signal K is 0, the amount of motion detection is minimum, the image data from the moving image processing section 114 is blocked by the multiplier 116,
Is output from the multiplier 118 and the adder 122 as image data subjected to the still image processing.

If the motion detection signal K has a value between 0 and 1, the image data from the moving image processing unit 114 and the image data delayed by one field from the field memory 90 are mixed with a weight according to the value. , And averaged image data is output.

[1010] In order to realize the above-described moving image real-time processing system, each part of the image processor performs the following processing or operation.

First, the field memories 90, 9 of the input stage
The function 2 is realized in the image memory 50 by the control shown in FIG. 8 as described above. Here, the input to the field memory 90 is, for example, the first input buffer SD
IA, and outputs from the field memories 90 and 92 are supplied to first and second output buffers SDOA and SDO.
Through B.

[1030] Each processing of the subtractor 94, the absolute value circuit 96 and the non-linear circuit 98 is executed by the SMID type digital signal processing section (10, 12, 14). In this case, the SVP 14 synchronizes the input image data from the input unit 40 with the image data delayed by one frame from the image memory 50 (the frame memory 92), and simultaneously takes in both image data into the DIR 16 in line units. Here, in order to synchronize the image data delayed by one frame from the image memory 50 with the input image data from the input unit 40, the read timing of the output buffer SDO in the image memory 50 may be adjusted to the input image data.

After the image data for one line is taken into the DIR 16, the SVP 14 executes all the processes of the above-mentioned units (94, 96, 98, 100, 102, 108) during the next horizontal scanning period. In the horizontal scanning period, the data of the processing result, that is, the data of the motion detection signal K
Output from one output port.

In the three-dimensional low-pass filter section, the field memory 104 is realized by the image memory 50. Therefore, the data of the motion detection signal K output from the SVP 14 as described above is written into the SDRAM 52 via the third input buffer SDIC of the image memory 50, and the third output buffer SDOC is output from the SDRAM 52 one field later. And then input to the DIR 16 of the SVP 14.

[1060] On the other hand, the moving image processing section 114 and the mixing circuit 1
The processing of each section in 24 is also executed by the SVP 14 within the same horizontal scanning period as the processing of the low-pass filter section. In this case, the SVP 14 converts the image data delayed by one field from the first output port of the image memory 50 into DI data.
Receive to the third input port of R16. Then, the image data VS ′ resulting from the processing is output from another output port of the DOR 20 and transmitted to the output unit 70 side.

[1070] As described above, in this image processor, the image data and other intermediate data for one or more channels are mainly transferred between the SVP 14 and the image memory 50 via the data path 72 several times. SVP
14 performs a required process in accordance with a program in the program memory 10, thereby realizing a moving image real-time processing system.

By increasing the number of input ports (input buffers) and output ports (output buffers) of the image memory 50, the number of field memory or frame memory functions can be increased. Therefore, for example, in the above-described moving image real-time processing system, noise reduction processing can be added by passing the image data output from the mixing circuit 124 through a low-pass filter including a field memory.

Alternatively, the input / output data rate in the SVP 14 and the image memory 50 is increased, and image data or intermediate data for a plurality of channels or a plurality of channels can be transmitted by one port within one unit period (for example, a horizontal scanning period). It is also possible to input / output in a time-sharing manner.

[1100] The moving image real-time processing described above is only an example, and the image processor can realize various image processing according to a program set and input from the outside. Hereinafter, some examples will be described.

FIG. 11 shows pointing control in the image memory 50 for dividing the screen into two parts on the left and right sides and simultaneously displaying images of different systems or channels. In this example, the first write pointer AWa is used to compress and write the image data of the first channel into the left half of each line in the SDRAM 52, and at the same time, the second write pointer AWa is used.
The image data of the second channel is compressed and written into the right half of each line using Wb. The writing of both image data may be performed asynchronously, but the leading write positions of each field are matched.

On the other hand, the image data thus written to the SDRAM 52 is read out one line at a time with a predetermined delay, for example, using the first read pointer ARa. When the read image data is sent to the display and displayed on the screen, the image of the first channel is displayed on the left half of the screen, and the image of the second channel is displayed on the right half of the screen. The parent-child screen can be realized in a similar manner.

As shown in FIG. 11, in parallel with the above-described two-screen display processing, another port and memory area of the image memory 50 are used, and another set of write / read pointers (AWc , ARc) can be used to perform any memory function, such as a field or frame memory function.

[1140] In the image memory 50, the 1
When performing a set or a plurality of sets of pointing operations, a predetermined amount of memory area may be allocated to each set, and each pointer may be turned in a loop within that area. With this, SDR
A large number of independent memory areas can be set in the memory area of the AM 52.

[1150] As another application, when writing image data to the image memory 50, by selectively writing only some pixels or scanning lines, the number of pixels and the number of scanning lines of the image can be reduced. In this case, under the condition that the data rate of the image data read from the image memory 50 and the data rate at the time of writing are set to the same value, FIG.
A reduced screen can be created as shown in FIG.

When such a thinning process is performed, it is better to first input the image data to the SVP 14, perform a low-pass filtering process thereon, and then write the image data to the image memory 50 by the above-described method to improve the reproducibility of the picture pattern of the image. It is preferable in that it is maintained.

Alternatively, when image data is read from the image memory 50, as shown in FIG. 13, each pixel or each scanning line is read out intermittently with respect to the read clock CL, as shown in FIG. The interval between each scanning line can be increased. In this case, the image data read from the image memory 50 is input to the SVP 14, where horizontal and vertical interpolation processes are performed, and pixels or scanning lines at positions skipped in the intermittent reading are indicated by dotted lines in FIG. Image data may be added or inserted as described above.

[1180] As shown in FIG. 15, two systems of image data VS1 and VS2 that are not synchronized with each other are
14 and the image memory 50, and both image data VS
The two image data VS1 and VS2 can be read from the image memory 50 in synchronization with a synchronization signal other than the synchronization signals 1 and VS2, for example, a synchronization signal on the display device 130 side. In this case, both image data VS1 and VS2 may be read as image data of two-screen synthesis as shown in FIG.

Also, in this image processor,
The number n of pixels of one line of the input image data VS is SVP1
When the number of images for one line that can be processed at one time within 4, that is, the number of processing elements PE is much larger than N (864) (for example, when n = 1600),
This can be dealt with by a method as shown in FIGS.

Conceptually, as shown in FIG. 16, input image data VS is divided into a first half VSi and a second half VSj, and an appropriate time gap td (for example, for 100 pixels) is provided therebetween. The image data of the first half VSi and the second half VSj are respectively n / 2 (800) per line.
DIR1 of SVP14 as image data having pixels of
6 is sequentially input.

The processing unit 18 in the SVP 14 has the first half VS
The same processing is repeatedly executed by allocating separate processing periods to the image data of i and the second half VSj. DO
R20 sequentially outputs the processed data.

Here, the image data of the first half VSi is delayed by the time corresponding to the above gap, and the image data of the second half VSi is output from the same port of the output unit 70 as it is (without delay). Thus, the front end of the image data of the second half VSj is connected to the rear end of the image data of the first half VSi,
As a result, processed image data having the same number n (1600) of images per line as the original input image data VS is obtained.

As described above, high-definition image data having a very large number of pixels n per line can be dealt with by dividing one line into two.

In the above series of processing, the input image data VS is divided into a first half part VSi and a second half part VSj, and a time gap td is provided therebetween, as shown in FIG. An image memory 50 as a line and a multiplexer 82 are used.

That is, the input image data VS from the input section 40 is directly applied to the first input terminal of the multiplexer 82 and is also input to the image memory 50. Then, delayed image data VSd, which is delayed from the input image data VS by a time corresponding to the fixed time td with respect to the input image data VS from one output port of the image memory 50, is output to the second input terminal of the multiplexer 82.

The multiplexer 82 receives the input image data VS according to the timing control TCM from the TCU 74.
Is switched to the first input terminal side for a certain period of time from the timing of the end, and then switched to the second input terminal side after a certain cutoff time. Thereby, the input image data V
S is divided into a first half VSi and a second half VSj with a predetermined time gap td interposed therebetween and input to the SVP 14.

By providing an appropriate time gap td between the first half VSi and the second half VSj, interference or collision between the rear end of the first half VSi and the front end of the second half VSj in the SVP 14 can be prevented. Avoiding data corruption.

After securing this gap td to an appropriate length, as shown in FIG. 17, a predetermined number of pixels (for example, 10 pixels) is added to the rear end of the front half VSi and the front end of the rear half VSj. While adding the overlapping part δ,
It is preferable to add a portion δ overlapping the rear end of the first half VSi by a predetermined number of pixels (for example, 10 pixels) at the front end of the second half VSj. Such an overlap portion is also input to the SVP 14, so that the SVP 14
The processing unit 18 in the inside is a rear end and a rear end V of the first half VSi.
High-precision processing can be performed on the front end of Sj as well as the middle part.

In the last output processing, the processing for connecting the front end of the second half VSj to the rear end of the first half VSi includes the processing shown in FIG.
7, an image memory 50 as a delay line and a multiplexer 86 are used.

Also, the image processor of this embodiment can compress the information of the image data by using the thinning function in the SVP 14 or the image memory 50 as described above. In this case, first, the input unit 40 performs low-pass filtering processing on the input image data, and then executes SVP1.
4 or input to the image memory 50, it is possible to avoid image quality deterioration such as aliasing distortion due to information compression.

FIG. 18 shows an example of a circuit configuration of a main part in a television receiver to which the image processor according to this embodiment is applied.

This receiver incorporates the image processor of this embodiment so that various video signals such as a monitor output signal PC from a personal computer, a baseband signal BB from a VTR, a high vision signal MUSE, and an NTSC signal can be obtained. Can be handled. For example, various modes such as a mode in which an NTSC signal is displayed on a screen and another arbitrary video signal is recorded on a VTR or the like, and a mode in which a high-definition signal MUSE and an NTSC signal are combined and displayed on a screen are set. When each mode is selected, predetermined program data may be loaded into each unit in the processor by the above-described download method.

FIG. 19 shows a circuit configuration example of a main part in another television receiver to which the image processor according to this embodiment is applied.

This receiver has a built-in U.S. standard ATV (advanced TV) decoder, and this ATV decoder uses, for example, 18 display formats (480 lines x 640 pixels, 600 lines x 800 pixels, 768 lines x 1024). ..) Can be decoded.

However, even if a reproduced video signal is output from any of 18 display formats from this ATV decoder, the display device (for example, CRT, LCD, plasma display, etc.) provided in this receiver is one.
Types of formats (eg, 768 lines × 1024)
The image data can be displayed on the screen only by the pixel.

Here, the image processor according to the present embodiment can convert the reproduced video signal from the ATV decoder into a display format on the display device side and then supply the converted signal to the display device.

[1370]

As described above, according to the image processing apparatus of the present invention, the SIMD type digital signal processing unit and the image memory which can execute the writing operation and the reading operation in parallel and independently are provided in the data path. Are connected to each other via a PC and each part in the device is made to operate in a programmable manner, so that it is possible to cope with various applications with a small-scale circuit configuration. Also, make effective use of the resources in the device,
Advanced image processing can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall circuit configuration of an image processor according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a data path in the image processing processor according to the embodiment.

FIG. 3 is a block diagram illustrating a circuit configuration example of an input unit in the image processing processor according to the embodiment.

FIG. 4 is a block diagram schematically illustrating a configuration example of an SVP in the image processing processor according to the embodiment;

FIG. 5 is a block diagram schematically illustrating a configuration example of an image memory in the image processor according to the embodiment;

FIG. 6 is a diagram illustrating a mechanism of a write / read operation of an input buffer in the image memory according to the embodiment.

FIG. 7 is a diagram illustrating a mechanism of a write / read operation of an output buffer in the image memory according to the embodiment.

FIG. 8 is a diagram illustrating an example of pointer control in the image memory according to the embodiment.

FIG. 9 is a block diagram illustrating a configuration example of a timing control unit in the image processor according to the embodiment;

FIG. 10 is a block diagram illustrating a functional configuration of a moving image real-time processing system that can be realized by the image processor according to the embodiment;

FIG. 11 is a diagram illustrating another example of pointer control in the image memory according to the embodiment.

FIG. 12 is a diagram illustrating an example of a pixel pattern obtained by one image processing method in the image processor according to the embodiment.

FIG. 13 is a timing chart for explaining another image processing method in the image processor of the embodiment.

FIG. 14 is a diagram showing an example of a pixel pattern obtained by the method of FIG.

FIG. 15 is a block diagram showing one application example of the image processor according to the embodiment.

FIG. 16 is a timing chart for explaining another image processing method in the image processor according to the embodiment.

FIG. 17 is a diagram showing means and operation for realizing the method of FIG. 16;

FIG. 18 is a block diagram illustrating a configuration of a main part of a television receiver to which the image processor according to the embodiment is applied.

FIG. 19 is a block diagram showing a configuration of a main part of another television receiver to which the image processor of the embodiment is applied.

FIG. 20 is a block diagram illustrating a configuration example of a conventional image processing apparatus.

[Explanation of symbols]

Reference Signs List 10 program memory 12 instruction generation circuit (IG) 14 SVP 16 data input register (DIR) 18 processing element section (processing section) 20 data output register (DIR) 40 input section 50 image memory 52 SDRAM 62, 64 multiplexer 66 control section 70 output unit 72 data path 74 timing control unit (TCU) 76 ROM loader 78 I ² C bus interface circuit 80 internal bus 82, 84, 86 multiplexer

Continued on the front page (72) Inventor Yuji Yaguchi 3-6-12 Kitaaoyama, Minato-ku, Tokyo Fuji Aoyama Building Inside Texas Instruments Japan Limited (72) Inventor Tsuyoshi Akiyama 3-6-1 Kitaaoyama, Minato-ku, Tokyo No. Fuji Aoyama Building Inside Texas Instruments Japan Co., Ltd. Inside Sangyo Co., Ltd. (72) Inventor Naoya Tokunaga 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Masahiro Tani 1006 Okadoma, Kadoma, Osaka Pref. Person Kenta Samukawa 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (22)

[Claims] An input unit for externally receiving image data to be processed; a plurality of processing elements assigned to pixels on a scanning line in a one-to-one correspondence and performing the same operation according to a common instruction A digital signal processing unit for inputting, processing, and outputting image data in units of scanning lines; and a fixed memory area, capable of executing a writing operation and a reading operation in parallel and independently. An image memory for inputting and outputting the image data in units of scanning lines; an output unit for outputting the processed image data to the outside; and data for interconnecting the input unit, the digital signal processing unit, the image memory, and the output unit. A path means, and the input section, the digital signal processing section, the image memory, the output section, and the data path to a desired program data. The image processing apparatus and a control means for controlling in accordance with data. 2. A digital signal processing unit comprising: a data input unit for inputting one or a plurality of image data corresponding to one or a plurality of video signals in parallel on a scanning line basis; A data output unit for outputting one or a plurality of image data processed in units in parallel on a scan line basis, a data input operation on a scan line basis in the data input unit, and a scan line in the processing element 2. The video processing device according to claim 1, wherein the processing operation in units and the data output operation in scanning units in the data output unit are executed in a pipeline system. 3. An image memory, comprising: a data writing means for sequentially writing input image data to the memory area at a continuous address; and a data reading means for sequentially reading image data to be output from the memory area at a continuous address. 2. The image processing apparatus according to claim 1, further comprising: pointer control means for controlling a write pointer and a read pointer for respectively indicating a write address and a read address for the memory area in accordance with the program data. 4. The image memory has a plurality of input buffers including at least two input buffer units having a predetermined storage capacity, and in each of the input buffers, a first input buffer unit is filled with image data. Then, writing of the input image data to the second input buffer unit is started, and
When the image data is read from the first input buffer unit and written into the memory area, and when the second input buffer unit is filled with the image data, the writing of the input image data to the first input buffer unit starts. The image processing apparatus according to claim 3, wherein the image data is read from the second input buffer unit and written into the memory area. 5. A data rate at which image data is written from each of said input buffers to said memory area is selected to be different from a data rate at which image data is written to each of said input buffers. Image processing device. 6. The image memory has a plurality of output buffers including at least two output buffer units having a predetermined storage capacity, and in each of the output buffers, image data of a first output buffer unit is empty. Then, the reading of the image data from the second output buffer unit is started, and the image data read from the memory area is written to the first output buffer unit. When the data is empty, the first
4. The image processing apparatus according to claim 3, wherein reading of the image data from the output buffer unit is started, and the image data read from the memory area is written to the second output buffer unit. 7. The data rate at which image data is written from the memory area to each of the output buffers is selected to be different from the data rate at which image data is read from each of the output buffers. Image processing device. 8. A data path means, comprising: a first data path section for electrically connecting a data output terminal of the input section to a data input terminal of the digital signal processing section; A second data path unit for electrically connecting an output terminal to a data input terminal of the image memory; and electrically connecting a data output terminal of the digital signal processing unit and a data input terminal of the image memory. A third data path unit for electrically connecting a data output terminal of the image memory and a data input terminal of the digital signal processing unit;
A fifth data path unit for electrically connecting a data output terminal of the input unit and a data input terminal of the output unit, a data output terminal of the digital signal processing unit, and a data input terminal of the output unit; And a seventh data path section for electrically connecting a data output terminal of the image memory and a data input terminal of the output section. Item 2. The image processing device according to Item 1. 9. The image processing apparatus according to claim 8, wherein all of the first to seventh data path units are formed on the same semiconductor chip. 10. The control means includes: an input unit, a digital signal processing unit, an image memory, an output unit, and a data path unit. The image processing apparatus according to claim 1, further comprising: a program data holding unit that is distributed and arranged; and a program data distribution unit that fetches desired program data from outside and distributes the program data to the program data holding unit in each unit. 11. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein the image data corresponding to one video signal is taken into the input unit, and the image data is output from the input unit. Inputting image data to the digital signal processing unit and performing a first process; writing image data output from the digital signal processing unit after the first process to the image memory to temporarily store the image data; And an image processing method comprising: inputting image data read from the image memory to the digital signal processing unit again to perform a second process. 12. A step of writing image data output from the digital signal processing unit after the second processing to the image memory and temporarily storing the image data, and re-writing the image data read from the image memory. 12. The image processing method according to claim 11, further comprising a step of inputting the digital signal to a digital signal processing unit and performing a third process. 13. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein the image data corresponding to one video signal is input to the input unit, and the image data is output from the input unit. Writing image data in the image memory and temporarily storing the image data, and inputting the image data from the input unit and the image data read from the image memory in parallel to the digital signal processing unit, Performing a predetermined process with the image data. 14. A digital signal processing unit which reads image data from two output ports of the image memory with a time delay by a desired delay and inputs the image data in parallel to the digital signal processing unit. The image processing method according to claim 12, wherein the predetermined processing is performed between two pieces of image data from the input unit and image data from the input unit. 15. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein the image data corresponding to one video signal is displayed on only a part of pixels on each scanning line and / or on each field. An image processing method comprising: writing only some scanning lines to the image memory to temporarily store the image data; and reading image data in the order of the pixels and the scanning lines written from the image memory. 16. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein image data corresponding to one video signal is temporarily stored in the image memory. Intermittently reading image data from the image memory in pixel units or scanning line units; inputting the image data read from the image memory to the digital signal processing unit, and intermittently reading the image memory Interpolating image data for a pixel or a scanning line at a skipped position at times. 17. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein the input unit outputs first and second image data respectively corresponding to two video signals that are not synchronized with each other. And temporarily storing the first image data output from the input unit in the image memory, and the second image data output from the input unit in the digital signal processing unit. Simultaneously reading the first image data from the image memory in synchronization with the second image data and inputting the first image data to the digital signal processing unit; and inputting the first image data to the digital signal processing unit in synchronization with each other. Performing predetermined processing on the first and second image data. 18. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein the first and second image data respectively corresponding to two video signals that are not synchronized with each other are input to the input unit. Inputting the first image data output from the input unit to the digital signal processing unit and performing predetermined processing; and converting the first image data output from the digital signal processing unit to Inputting the second image data output from the input unit to the image memory at the same time as inputting the image data to the image memory; and synchronizing with a synchronization signal other than the synchronization signals related to the first and second image data. Reading first and second image data from the image memory. 19. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein the image data corresponding to one video signal is taken into the input unit, and the image data is output from the input unit. Inputting the first half of the image data to the digital signal processing unit during a first period; writing the image data output from the input unit to the image memory and reading out the image data after a predetermined delay time; Inputting the latter half of the image data read from the memory to the digital signal processing unit in a second period. 20. A step of writing the first half of the image data output from the digital signal processing unit to the image memory and reading it after a predetermined delay time, and the first half of the image data read from the image memory is Outputting to the outside from the output unit; outputting the second half of the image data from the digital signal processing unit; connecting the second half of the image data output from the digital signal processing unit to the first half of the image data 20. The image processing method according to claim 19, further comprising: outputting to the outside from the output unit. 21. A rear part of a first half of image data input to the digital signal processing unit during the first period,
Adding a first overlap portion overlapping the front end of the second half by a predetermined number of pixels; and the front end of the second half of image data input to the digital signal processing unit during the second period. Adding a second overlap portion that overlaps the rear end of the first half by a predetermined number of pixels to the unit; and outputting the image data to the outside from the output unit. Removing the overlapped part of the image. 22. An image processing method for processing image data by the image processing apparatus according to claim 1, wherein image data corresponding to one video signal is input to the input unit, and the input unit performs low-pass filtering processing. And an image processing method comprising: inputting image data output from the input unit to the digital signal processing unit or the image memory to perform a thinning process for compressing the image data.