JPH11355683A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correspond to plural display specifications not by providing a dedicated line in each request specification but by switching an instruction by providing a computer which performs arithmetic processing and an instruction sequencer which selects data to be inputted to it and controls an output in a pixel clock. SOLUTION: A memory controlling means 104 reads data to be shown in a line unit from a frame memory 102 to an output buffering means 105 according to an instruction of a system controlling part 100. A video processing unit 106 and an instruction sequencer 107 generate output data for one line by using the data. That is, an instruction execution controlling means 1072 synchronizes with a pixel clock and repeatedly reads instructions ranging 0 to 5 addresses from an instruction memory 1071. An instruction decoder means 1073 decodes a read instruction and controls a data selecting means 1061 and computers A1062 and B1063. An operation result is written to an output switching means 1065 and is outputted to an external monitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal for a set-top box or the like which receives a digital broadcast signal multiplexed with digital data such as a compressed video signal and program information, and decodes and outputs a selected video signal. The present invention relates to a display device.

[0002]

2. Description of the Related Art In recent years, with the development of digital technology, digital broadcasting services have been realized in which broadcasting video, audio, and data signals are integrally processed as digital signals, and broadcasting is performed using communication satellites and the like. is there. These services use MPEG2 (ISO / IEC-1381).
It is possible to provide broadcasts of tens to hundreds of channels by a compression multiplexing technique typified by, for example, (8).
Broadcasters use a variety of services to realize high-definition broadcasting and still image information services by taking advantage of the feature that all signals such as video, audio and data are handled as digital signals in digital broadcasting. Therefore, a video display device corresponding to these is required.

FIG. 6 shows an example of a conventional MPEG video decoder system, and its operation will be described below. In FIG. 6, reference numeral 100 denotes a system control unit for controlling the entire system;
Reference numeral 1 denotes a video decoding unit that performs MPEG decoding, and 102 denotes a frame memory that stores display data.
01 decodes video data and On Screen Display
(Hereinafter referred to as OSD) graphics data. 1
03 is a display timing generating means for generating a synchronization signal and the like, 104 is a memory control means for controlling writing and reading of the frame memory 102, and 105 is an output buffer means for temporarily storing display data read by the memory control means. 600 is a video processing unit that generates display data using the data of the output buffer means 105;
Reference numeral 601 denotes a control timing generation unit that controls the video processing unit.

FIG. 7 is a diagram showing a typical internal configuration of a video processing unit 600 in an MPEG video decoder system. Reference numerals 6001 and 6002 denote horizontal filter circuits for performing horizontal enlargement / reduction of video data, reference numeral 6003 denotes a vertical filter section for performing vertical enlargement / reduction from continuous two lines of data from the horizontal filters 6001 and 6002, and 6
004 indicates the video data from the vertical filter unit 6003 and O
This is a synthesis circuit for switching between SD data.

FIG. 8 shows a DVB (Digital VideoBroardcasti).
ng DOCUMENT A001-revision 1) Indicates the video output format to be realized by the digital broadcast receiver specified by the standard. In order to realize the horizontal / vertical enlargement processing shown in FIG. 8A, the horizontal filter circuits 6001, 6002 and the vertical filter circuit 6003 are provided with circuits corresponding to the following magnifications in advance.

Horizontal filter circuit: 3/4, 1, 9 /
8, 4/3, 3/2, 2, 8/3 Vertical filter circuit: 1, 2 FIG. 8B is a diagram showing pan scan processing, in which an input image having an aspect ratio of 16: 9 is converted to a 4: 3 image. When outputting to the monitor, the center part (Pan & Scan Window) of the screen is cut out and horizontally enlarged.

As described above, in the video display device of the digital broadcast receiver, horizontal and vertical enlargement processing of the video signal is an essential function. Hereinafter, the operation of the MPEG decoder system of FIG. 6 will be described. The system control unit 100 inputs a bit stream corresponding to the channel selected by the user to the video decoding unit 101.

[0008] The video decoding section 101 extracts the information of the input resolution shown in FIG. 8A stored in the bit stream, and transfers it to the system control section 100. Video decoding unit 101
Performs MPEG video decoding using the frame memory 102 as a reference frame buffer and a display frame buffer. The MPEG decoding process is not directly related to the object of the present invention, and a detailed description of the operation will be omitted.

The system control unit 100 controls the frame memory 102 to perform on-screen operation in parallel with the decoding control.
Display (OSD) data is drawn. This includes operation information such as menus and EPG (Electronic Program Guide).
This is the program guide data called. In the video display, the system control unit 100 controls the memory control unit 104 to store the decoded image data from the frame memory 102 and O
Read SD data in line units. The data read line by line is temporarily stored in the output buffer means 105.

The system control unit 100 includes a video decoding unit 1
01 according to the resolution information of the input image extracted from the image processing unit 01 and the aspect ratio of the output monitor designated by the user in advance.
02 and the enlargement ratio of the vertical filter circuit 8003 are set, and the enlargement processing shown in FIG. 8A is controlled. The enlarged decoded image is combined with the OSD data by the combining circuit 8004 and output to the outside.

As described above, the video processing apparatus in the conventional MPEG decoding system includes a dedicated circuit corresponding to a predetermined enlargement ratio, and a circuit for synthesizing OSD data.
The display output is generated according to the resolution information of the decoded image and the like. FIG. 9 is a block diagram of an MPEG decoder system for realizing still image display in addition to displaying a moving image and an OSD in order to support a still image information service. The image processing unit 800 includes two horizontal filter circuits 80.
01, 8002 and a vertical filter circuit 8003,
Each is controlled for moving image data and still image data, and a switching circuit 8005 for switching operation data and still image data is newly provided.

In operation, the system control unit 100 draws not only OSD data but also still image data in the frame memory 102. Still image data is transmitted using, for example, data broadcasting in digital satellite broadcasting,
Sent via telephone line. In each case, data is acquired by a user operation and displayed under the control of the system control unit 100. Still image data drawn in the frame memory 102 is converted into moving image data,
Output buffer means 10 for each line together with OSD data
5 is read. At this time, when performing the vertical filtering process on the moving image data, the moving image data is read out of data of two consecutive lines.

Using this data, the video processing unit shown in FIG. 9 independently executes a reduction process on moving image data and still image data, and combines this calculation result with the OSD data, as shown in FIG. Output screen can be obtained. As described above, the conventional video display device has been realized by providing a dedicated circuit as shown in FIGS. 7 and 9 corresponding to different display specifications for each business operator. These are usually incorporated as a part of the circuit of the MPEG video decoder LSI.

[0014]

As described above, in the conventional video display apparatus, a different dedicated circuit is required for each broadcaster, and in order to support a plurality of broadcasters, separate display requests are required for each display request. Circuits are required, which leads to an increase in the circuit scale, and if optimized for each business operator, it is necessary to develop a different type of LSI, resulting in an increase in development costs.

[0015]

In order to solve the above-mentioned problems, an image display apparatus according to the present invention comprises a computing unit which performs at least one computation within a pixel clock, and selection and output of data to be inputted to the computing unit. And an instruction sequencer that controls
By executing this instruction in synchronization with the display clock,
A video enlargement / reduction process and a synthesis process with the OSD are realized.

With this configuration, instead of providing a dedicated circuit for each required specification as in the conventional device, the arithmetic unit and the instruction sequencer are used as a common circuit, and a plurality of display specifications are supported by switching instructions. It is possible to do.

[0017]

A video display device according to claim 1 of the present invention comprises a frame memory for storing display data, a display timing generating means for generating display timing, and a frame memory for synchronizing with the display timing generating means. Memory control means for reading display data from a memory; output buffer means for temporarily storing display data read by the memory control means;
An arithmetic unit for performing display operations by performing the arithmetic operation twice, reading display data from the output buffer unit in synchronization with a pixel clock, and selecting data to be input to the arithmetic unit; A command sequencer for controlling the data selection means and the arithmetic unit in synchronization with timing of the means, wherein the instruction sequencer stores control information for controlling the calculation unit and the data selection means; Instruction execution control means for reading at least one or more instructions within a pixel clock; and instruction decoder means for decoding the read instructions and controlling data input to the arithmetic unit by the data selection means. It is characterized by having. Image display processing such as image enlargement / reduction and synthesis processing with the OSD can be described by an instruction of the instruction sequencer.

According to a second aspect of the present invention, in the video display device, the instruction memory according to the first aspect stores an execution instruction within at least one pixel clock. And a means for repeatedly reading the instruction memory in synchronization with the instruction and controlling the execution of the instruction for one line. This can be realized with a small instruction memory of one pixel.

According to a third aspect of the present invention, there is provided a video display device comprising an arithmetic result buffer means capable of temporarily storing the output of the arithmetic unit according to the first or second aspect and outputting the output to the data selection means. It is characterized by having. By temporarily accumulating the operation results, the operation results can be freely selected as the input of the operation unit even in the next cycle and thereafter, so that more types of operation processes can be controlled by instructions.

According to a fourth aspect of the present invention, there is provided a video display device comprising a write-back means for writing back the data output from the arithmetic unit according to the first to third aspects to an output buffer means, wherein the instruction sequencer also has a write-back means. It is characterized by controlling. The function of writing back the decoded image after the enlargement / reduction into the frame memory can also provide a screen for displaying a plurality of reduced images side by side.

According to a fifth aspect of the present invention, there is provided a video display device, wherein the instruction sequencer according to the first to fourth aspects includes means for switching the number of instructions to be read within a pixel clock according to a pixel clock frequency. It is assumed that.
By switching the number of execution instructions in the pixel clock in accordance with the decoded image, even in the case where 480 or 1080 interlaced scans and 480 or 720 sequential scans are mixed and broadcast, only by changing the number of execution instructions Video processing can be realized.

(Embodiment 1) Hereinafter, claims 1 to 3 of the present invention will be described.
An embodiment of the video display device will be described with reference to FIGS. In FIG. 1, a system control unit 100,
The video decoding unit 101, the frame memory 102, the display timing generation unit 103, the memory control unit 104, and the output buffer unit 105 have the same configuration as the conventional example.

The video processing unit 106 reads out display data from the output buffer means 105 in synchronization with the pixel clock and selects data to be input to an arithmetic unit described later. Calculator A that performs calculations and generates display data
1062, a computing unit B 1063, a register file 1064 for temporarily storing a computation result, and an output switching unit 106
And 5.

The data selecting means 1061 has a function of controlling the reading of data from the output buffer means 105 according to the horizontal magnification. This can be realized by, for example, having an 8-bit adder, incrementing a fixed value for each pixel clock, and using the carry of the adder as a trigger for reading the next pixel data. In this case, the horizontal enlargement ratio can be specified by a fixed value to be incremented, and the output of the 8-bit adder can be used as a calculation coefficient at the time of horizontal enlargement processing.

The arithmetic units A and B execute the following equations, respectively. Arithmetic unit A: (arithmetic result) = α × A + β × B + C Arithmetic unit B: (arithmetic result) = γ × D + (1−γ) × E The instruction sequencer 107 includes a display timing generation unit 10.
The data selector 1061 and the arithmetic units 1062 and 1063 are controlled in synchronization with the timing of No. 3 and include the following four components.

The instruction memory 1071 includes an arithmetic unit 1062,
The control information for controlling the input and output of the 1063 is stored. The instruction execution control means 1072 controls the reading of a plurality of instructions within a pixel clock. The instruction decoder means 1072 is read from the instruction memory 1071. It decodes the received instruction and controls the data selection means 105 to control the data input to the computing units 1062 and 1063.

The instruction is to select the coefficient values α and β and the input data A, B and C for the arithmetic unit A 1062 and to select the arithmetic unit B 10
Selection of the coefficient value γ and the input data D and E for 63, and the output destination of each arithmetic unit (information on where to write the result:
It is assumed that writing to the register file 1064 or output switching means 1065) is specified. The instruction memory 1071 stores six instructions, and the instruction execution control means 1072 repeats this in synchronization with the pixel clock to control the execution of one line of instructions.

The operation of the embodiment configured as described above will be described with reference to FIG. First, the system control unit 100 controls the display control in units of one line. Specifically, in accordance with an instruction from the system control unit 100, the memory control unit 104 reads data to be displayed from the frame memory 102 to the output buffer unit 105 line by line. Video processing unit 106 and instruction sequencer 107
Uses this data to generate one line of output data. Until the display data is read out to the output buffer means 105, the operation is the same as that of the conventional example. Below, the case where the input resolution shown in FIG. 8A is 352 × 240,
The description will be made on the assumption that the image is enlarged twice in the horizontal and vertical directions during display. In this case, it is assumed that the output buffer unit 105 holds data of two consecutive lines of the decoded image from the frame memory 102.

FIG. 2 shows an example in which the video processing of FIG. 7 of the conventional example is realized. The pixel clock is set to 13.5 MHz, and the operation clocks of the video processing unit and the instruction sequencer are increased by 6 times to 8 times.
It is 1 MHz. The instruction execution control means 1072 repeatedly reads instructions from addresses 0 to 5 from the instruction memory 1071 in synchronization with the pixel clock. Instruction decoder means 10
The decoding unit 73 decodes the read instruction and controls the data selection unit 1061, the arithmetic unit A 1062, and the arithmetic unit B 1063 as follows.

Arithmetic unit A: (1) Instruction 1: Data selecting means 1061 selects horizontal two-pixel data and coefficient value data of the first line of a decoded image (moving image), and executes a multiply-add process based on the data. . The calculation result is written in the register file 1064. (2) Instruction 2: The second instruction is performed by the data selection unit 1061.
Of the horizontal line and coefficient value data are selected, and a multiplication and addition process is performed using the selected data. The calculation result is passed through (feedback to the data selection means). (3) Instruction 3: The register file data written by the instruction 1 and the operation result of the instruction 2 (through) are selected by the data selection means 1061, and a multiply-add operation is executed. This means that the vertical operation based on the first line data and the second line data has been executed. Calculation coefficient value α,
β can be realized by providing the data selection means 1061 with a coefficient register and setting the line by the system control means 100. The calculation result is the register file 1064
To be written. (4) Instruction slots 4 to 6 do not particularly execute instructions.

Arithmetic unit B: (1) Instruction 1: The data of the register file 1064 written by the instruction 3 of the arithmetic unit A by the data selection unit 1061 and the register value as the background color (the data selection unit 10
61) and perform the calculation. The calculation coefficient value γ is
It is assumed that the data is generated from the effective display period signal of the decoded image in the data selection means 1061. The calculation result is through (feedback to the data selection means). Thereby, data in which the outside of the effective display area is filled with a specific background color is generated. (2) Instruction 2: The operation result of the instruction 1 and the OSD data are selected by the data selection unit 1061, and the combining processing is performed. The OSD data has a composite value (γ coefficient value) with the video data. The calculation result is output to the output switching unit 10.
65 and output to an external monitor. Describe the command (6 steps) for one pixel as described above,
As shown in FIG. 2, the instruction execution control means 1072 repeatedly executes the instruction in synchronization with the pixel clock, thereby generating one line of screen data. The enlargement processing for the decoded image is performed by the instruction 1 in the arithmetic unit A.
This can be dealt with by changing ~ 3. For example, in the case of horizontal enlargement processing, only instruction 1 is executed, and instructions 2 to 6 are set to NO.
This can be handled by setting P (No Operation).

On the other hand, FIG. 3 shows an example in which the image processing of FIG. 9 of the conventional example is realized in the image display device of FIG. In the following, a description will be given assuming that two types of screens, that is, a decoded image (moving image) and still image data, are each reduced by に in the horizontal and vertical directions. At the time of vertical 縮小 reduction, data is generated by performing interpolation processing using two consecutive lines. As in FIG. 2, the pixel clock is set to 13.5 MHz, and the operation clocks of the video processing unit and the instruction sequencer are increased by 6 times to 81.
MHz. The instruction controlled by the instruction sequencer 107 is controlled as follows.

Arithmetic unit A: (1) Instruction 1 to Instruction 3: Same as FIG. (3) Instruction 4 to Instruction 6: The execution contents are the same as those of Instructions 1 to 3, except that still image data is selected as operation data by the data selection means 1061. Arithmetic unit B: (1) Instruction 1: The data selection unit 1061 selects the register file 1064 written by instruction 3 of the arithmetic unit A and a register value to be a background color (held in the data selection unit 1061), and performs an operation. The calculation result is written into the register file 1064. (3) Instruction 2: The data selection means 1061 selects the register file 1064 written by the instruction 6 of the arithmetic unit A and the register value as the background color (held in the data selection means 1061), and executes the operation. The calculation result is passed through. (4) Instruction 3: The data selection means 1061 selects the register file 1064 written by the instruction 1 and the operation result of the instruction 2, and performs the operation. The calculation coefficient value γ is generated from the effective display period signal of the decoded image (moving image) by the data selection unit 1061 and is selected.
The calculation result is passed through. (5) Instruction 4: The operation result of the instruction 3 and the OSD data are selected by the data selection means 1061, and the operation is performed. The calculation result is written to the output switching means 1065 and output to the external monitor.

As described above, the same video display device shown in FIG. 1 executes the command shown in FIG. 3 to easily cope with the video processing shown in FIG. With recent advances in semiconductor technology, the operating frequency of circuits has been dramatically increased, and it has become easier to increase the operating clock of an arithmetic unit or the like relative to the pixel clock. For example, 81MHz
If it can be executed at a higher frequency, according to the configuration of the present invention, two still images or moving images can be easily displayed.

Further, in the embodiment of FIG. 1, the filter operation and the synthesis operation are executed separately by two operation units, and the present invention is not particularly limited to this configuration. For example, a single arithmetic unit may be realized, or a plurality of arithmetic units may be combined. The arithmetic unit also
The present invention is not limited to the multiplication and addition processing as described in the above embodiment, and may execute other arithmetic processing.

In the above embodiment, the instruction memory size is described as one pixel.
It is permissible to have a line. Also, the configuration using the register file has been described. However, if an instruction is specified to use the operation result every cycle, the present invention can be realized without having a register file. (Embodiment 2) Next, an embodiment of a video display apparatus according to a fourth aspect of the present invention will be described with reference to FIG.

The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. The write-back means 1066 controls to write back the output data from the arithmetic unit A 1062 and the arithmetic unit B 1063.
08 has a function of writing the data written back from the write-back unit 1066 to the frame memory 102 in addition to reading the display data from the frame memory 102.

The instruction of the instruction sequencer 107 selects the write-back means 1066 as a destination to which the operation result is written.
08 is written. In operation, the instruction decoder means 10
When the write-back means 1066 is selected from 73, the arithmetic unit A
The output data of the arithmetic unit 1062 or the arithmetic unit B 1063 is temporarily stored in the write-back unit 1066.

The write-back means 1066 transfers the stored data to the input / output buffer means 108 in a cycle other than the display reading. When the operation result data for one line is written, the system control unit 100 controls the write transfer to the frame memory 102 by the memory control unit 104. If the rewritten image is read out from the frame memory 102 as a still image and displayed, it is possible to display a plurality of reduced decoded images side by side. An interface screen can be easily provided.

(Embodiment 3) Next, an embodiment of an image display apparatus according to a fifth aspect of the present invention will be described with reference to FIG. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Some digital broadcasts provide broadcast services with different frame rates.
For example, 480 or 1080 interlaced scans, 4
It is a mixed broadcast of 80 or 720 sequential scans. In such a case, it is necessary to switch the clock for display depending on the decoded image.

In this embodiment, in such a case, a description will be given of a video display apparatus which handles the video processing unit 106 and the instruction sequencer 107 while keeping the operating frequency unchanged and switching only the number of execution instructions in the pixel clock. The number-of-executed-commands switching means 1074 switches the number of instructions to be read within a pixel clock.
Controlled by 0.

In operation, the system control unit 100
When the display clock is switched based on the resolution information of the decoded image, a predetermined number of instructions is set to the execution instruction number switching unit 1074. Instruction execution control means 1072
Reads repeatedly the number of instructions specified by the number-of-executed-commands switching means 1074.

With the above configuration, even if the display clock is switched, video processing can be executed without any problem.

[0044]

As described above, according to the video display device of the present invention, various display requirements can be easily changed by using a combination of common hardware and commands corresponding to the display requirements in response to different display requirements. Function can be realized. Also, the instruction memory can be realized with a size as small as one pixel, and the circuit scale can be realized with almost no difference from the conventional device.

As described above, there is an effect that the development cost can be reduced by producing a circuit (LSI) of a different type for each required specification, which has been a problem to be solved conventionally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a video display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of instruction execution in an instruction sequencer in the video display device shown in FIG.

FIG. 3 is a diagram showing another example of instruction execution in the instruction sequencer in the video display device shown in FIG. 1;

FIG. 4 is a block diagram showing a video display device according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a video display device according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a conventional video display device.

FIG. 7 is a detailed block diagram of a video processing unit in a conventional video display device.

8A is a diagram showing a video output specification in a digital broadcast receiver. FIG. 8B is a diagram showing a pan scan display process in the digital broadcast receiver.

FIG. 9 is a detailed block diagram of another video processing unit in a conventional video display device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 system control unit 101 video decoding means 102 frame memory 103 display timing generation means 104 memory control means 105 output buffer means 106 video processing unit 1061 data selection means 1062 arithmetic unit A 1063 arithmetic unit B 1064 register file 1065 output switching unit 1066 Return means 107 Instruction sequencer 1071 Instruction memory 1072 Instruction execution control means 1073 Instruction decoder means 1074 Execution instruction number switching means 108 I / O buffer means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/66 H04N 5/66 D

Claims (5)

[Claims] 1. A frame memory for storing display data, a display timing generator for generating display timing, a memory controller for reading display data from the frame memory in synchronization with the display timing generator, Output buffer means for temporarily storing display data read by the means, an arithmetic unit for performing display operation by performing at least one operation within a pixel clock, and synchronizing with the pixel clock from the output buffer means. Data display means for reading display data and selecting data to be input to the arithmetic unit, and an instruction sequencer for controlling the data selection means and the arithmetic unit in synchronization with the timing of the display timing generation means, The instruction sequencer controls the arithmetic unit and the data selection unit An instruction memory storing control information of the eye,
Instruction execution control means for reading at least one or more instructions in a pixel clock; and instruction decoder means for decoding the read instruction and controlling data input to the arithmetic unit by the data selection means. An image display device characterized by the above-mentioned. 2. The apparatus according to claim 1, wherein said instruction memory stores an execution instruction within at least one pixel clock, and said instruction execution means repeatedly reads said instruction memory in synchronization with the pixel clock. The image display device according to the above. 3. The video display according to claim 1, further comprising an operation result buffer unit capable of temporarily storing an output of the operation unit and outputting the output to the data selection unit. apparatus. 4. The apparatus according to claim 1, further comprising a write-back means for writing back the data output from said arithmetic unit to said output buffer means, wherein said instruction sequencer also controls said write-back means. An image display device according to the item. 5. The video display device according to claim 1, wherein said instruction sequencer comprises means for switching the number of instructions to be read within a pixel clock.