JPS61251970A - Image processor - Google Patents

Abstract

PURPOSE:To simplify the constitution of the peripheral circuit of frame memory by connecting memory capable of reading and writing parallel data in the frame memory at a high speed, for instance, an SAM, and switching the shift clock of the SAM. CONSTITUTION:A CLK of 24MHz is inputted to an access control circuit 6, and data is transferred between the SAM 4 and the frame memory (FM) 1 in synchronizing with 24MHz. An MPX 5 adds an address specifying simultaneously the indication address of one picture element in the FM and all picture elements of one line to the FM 1. The picture element data of one line is transferred in parallel between the SAM 4 and the FM 1, and the picture element data is inputted from a video digitizer through an MPX 10. Simultaneously the picture element data is outputted to an arithmetic circuit 12 through a register 11, and the circuit 12 writes the arithmetic processed result in the FM 1. Whenever an SCLK is applied from a clock switching circuit 13, the SAM 4 transfers the picture element data to the circuit 12 through the register 11, and simultaneously transfers it to a television monitor through a register 14.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing device that performs image calculation processing by controlling transfer of digitized image information as parallel data.

(Prior Art) An image captured by an imaging device contains a single image that is processed for various purposes such as mask processing and feature extraction.
It is necessary to perform various logical operations such as logical product operation and logical sum operation on each piece of pixel data for one frame.

FIG. 4 shows data input/output control with a frame memory 40 that stores digitized image information.
For example, the figure shows a transfer control unit in an image processing apparatus that performs arithmetic processing on image data supplied from a video digitizer and outputs the image to a TV monitor or the like.

(Problems to be Solved by the Invention) In the figure, reference numeral 41 denotes an arithmetic unit (Go-Processor) that performs various logical operations on image information, and performs arithmetic processing at a clock rate of, for example, 10MHz via a high-speed data bus. It is done. However, the sweep speed of video digitizers and TV monitors is usually slower than that, so video digitizers and To exchange data with the TV monitor, use FIFO
SAM4 memory 43.44 for converting data transfer speed (first-in first-out memory) etc.
It had to be installed on the input/output side of 2. In addition, the access control unit 45 performs high-speed memory access and the register 46
In order to exchange data with the arithmetic unit 41 via the multiplexer 47, the capacity of the memories 43 and 44 used becomes large, or an external buffer memory is required.

The present invention has been made to solve these problems, and an object of the present invention is to provide an image processing device in which the configuration of the peripheral circuit of the frame memory is simplified without impairing the high-speed calculation capability of the arithmetic unit. .

(Means for Solving the Problems) The present invention performs data input/output control with a frame memory that stores digitized image information, performs arithmetic processing on the supplied image, and outputs the image. In the image processing apparatus, the image processing apparatus includes: a storage section that writes and reads parallel data to and from the frame memory; a clock switching circuit that switches and supplies a plurality of synchronous clocks for data transfer control in the storage section; The image forming apparatus includes an input/output control circuit that inputs/outputs data at a necessary transfer rate between the storage section and the arithmetic processing section or between the image input/output section.

(Function) The image processing device of the present invention connects a storage unit, such as a serial access memory SAM, capable of reading and writing parallel data at high speed to a frame memory that stores digitized image information, and uses a shift clock of this SAM. By switching between the two, image information can be transferred without an external buffer memory.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of an apparatus according to an embodiment of the present invention, and is a block diagram of a main part of an image processing apparatus that extracts image information from a frame memory l in parallel and performs predetermined logical operations and the like to perform image arithmetic processing. .

The frame memory l is a frame memory with M rows and N columns that stores digitized image information as, for example, 128 (M) x 256 (N) pixel data,
a data input/output terminal connected to a system data bus 3 via a data transmitter/receiver 2; a data input/output terminal connected to a serial access memory (SAM) 4;
It has an address terminal and a chip select terminal connected to the output of the multiplexer 5, and a write enable terminal and a transfer terminal connected to the access control circuit 6. S.A.
M4 transmits and receives one row of pixel data to and from the frame memory 1 in parallel, and when one pixel has 8 bits, it is connected by 8×256 signal lines.

The access control circuit 6 has a 24 MHz clock CLK.
A processor 8 which instructs image processing and the like is connected via a control bus 7. Also,
The multiplexer 5 is connected to the processor 8 via an address bus 9, and is connected to the specified address of one pixel in the frame memory 1 and to an image data micro-digitizer (not shown) or an arithmetic unit (for example, an arithmetic circuit 12 to be described later).
) to the frame memory 1, and an address that simultaneously specifies all pixels for one row.

The SAM 4, which has enough stages to store pixel data for one row of the frame memory 1, has one row of pixel data between the frame memory 1 and
Parallel transfer of pixel data for rows is performed, and pixel data from the video digitizer is input via the multiplexer 10, and is also transferred via the register 11 to the arithmetic circuit (C
(+-processor) 12 to output pixel data. This arithmetic circuit 12 includes a multiplexer 1
0, the result of the arithmetic processing can be written into the frame memory 1 again.

The clock switching circuit 13 has two clocks, lOMHz and 6MFlz.
The frequency of the shift clock 5CLK that controls the SAM 4 is switched by a regular clock being supplied, and each time this 5CLK is added, the contents are sequentially shifted to the right by one pixel data. In this way, the pixel data of the SAM 4 is transferred to the arithmetic circuit 12 via the register 11, and is also transferred via the register 14 to an image output device such as a TV monitor. That is, these registers 11 and 14 constitute the output control circuit of the SAM 4, and control the transfer rate of pixel data synchronized with the IOMHz and 6MH2 clocks, respectively.

FIG. 2 shows a specific circuit configuration of the clock switching circuit 13.
) 21.22 and two clip-flops 23.24
Consisting of

Each of the three input terminals of the AND gate 21 has 6M
A Hz clock, 6 MHz selection signal and gate control signal are provided. In addition, the three input terminals of the AND gate 22 are connected to a 10MHz clock and a 10MHz clock, respectively.
z selection and gate control signals are provided. The outputs of these 21 and 22 are supplied to the SAM4 via the OR gate 20, and when the SAM4 is used to exchange data with a video digitizer or TV monitor, a flip-flop 23 is set. The AND gate 21 is opened at the output, and the SAM 4 is operated with a 6 MHz clock, and when inputting/outputting data with the arithmetic circuit 12, the SAM 4 is operated at 10 MHz.

Note that the access control circuit 6 of the frame memory 1 has 24
It is operated at MHz, and data transfer between the SAM 4 and the frame memory 1 is performed in synchronization with 24MH2.

FIG. 3(a) shows the SAM clock from the switching circuit 13 when 6 MHz is selected. By preparing a gate control signal as shown in the figure, it is also possible to generate a 3 MHz SAM clock. At this time, the selection signal is "l
” is fixed.

In addition, FIG. 3(b) shows the selector path 1 when lOMHz is selected.
The SAM clock from 3 is shown. By preparing a gate control signal as shown in the figure, it is also possible to generate a SAM clock with teeth omitted at a ratio of 1:3 from a 1OMHz clock. At this time, the selection signal is fixed at l''.

Although the above embodiment describes the case where the serial access memory SAM4 is used to transfer data between the frame memory 1 and the frame memory 1, the same applies when other memory access circuits are used. By switching the control synchronization clock, image information can be transferred without an external buffer memory.

(Effects of the Invention) As detailed above, according to the present invention, it is possible to provide an image processing device in which the configuration of the peripheral circuit of the frame memory is simplified without impairing the high-speed calculation capability of the arithmetic device. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration of a clock switching circuit of the same embodiment, and FIGS. 3(a) and (b) are diagrams showing the same embodiment. FIG. 4, a diagram showing example operation timing, is a block diagram of a conventional device. 1...Frame memory, 4...Serial accelerator memory, 12...Arithmetic unit, 13...Clock switching circuit, 11.14...Register.

Claims (2)

[Claims] (1) In an image processing device that performs data input/output control with a frame memory that stores digitized image information, performs arithmetic processing on the supplied image, and outputs the image, A storage unit that writes and reads parallel data to and from the memory, a clock switching circuit that switches and supplies a plurality of synchronized clocks for data transfer control in the storage unit, and a clock switching circuit that switches and supplies a plurality of synchronized clocks for data transfer control in the storage unit, and a clock switching circuit between the storage unit and the arithmetic processing unit or An image processing device comprising: an input/output control circuit that inputs/outputs data by converting it to a necessary transfer rate between the input/output unit and the input/output unit. (2) The image processing device according to claim 1, wherein the storage unit is a serial access memory that writes and reads one row of image data in the frame memory as parallel data. .