JPH01114965A - Command transfer system to processor array and its circuit - Google Patents

Abstract

PURPOSE:To allow a host computer to generate a control command by providing respective processors with corresponding command buffers in order to absorb the difference between an operation clock on the array processor side and command transfer speed on the host computer side. CONSTITUTION:A processor 2 inputs and processes an input signal supplied to a data input terminal 8 based on a synchronizing signal supplied from a synchronizing signal input terminal. The processed result of the processor 2 goes to a data input to a processor 3 as it is. On the other hand, a command transfer circuit 5 delays the synchronizing signal inputted from the terminal 22 by processing delay based upon the processor 2 and supplies the delayed signal to the succeeding command transfer circuit 6 and the processor 3. Thereby, the processor 3 can fetch and process the processed result of the processor 2 based on the synchronizing signal supplied from the circuit 5 independently of the delay processing of the processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method and circuit for transferring commands to a processor array, and particularly to a method and circuit for transferring a processor command to a digital signal processor array, such as a video signal.

(Prior art) In order to perform high-speed arithmetic processing on a large amount of data, such as when processing video signals in real time, it is necessary to arrange a large number of arithmetic circuits in series or parallel for real-time processing. It is conceivable that the computing power can be obtained.

As a processor for realizing such processing, a processor architecture for the purpose of real-time processing of video signals is published in the Proceedings of the National Conference of the Telecommunications Division of the Institute of Electronics and Communication Engineers in 1988, Vol. 2, Section 5.

According to the published content, the processor consists of multiple unit processors connected in parallel to an input bus and an output bus, and each unit processor processes a predetermined partial area within the output screen to perform real-time processing. It is something that will be realized. Each unit processor inputs a moving image signal, performs arithmetic processing, and outputs a processing result at a predetermined timing, with duplication allowed between the unit processors, with reference to the synchronization signal of the input signal. Therefore, each unit processor can operate independently from each other without inter-processor communication.

However, in a processor in which unit processors are connected in parallel in this manner, processing overhead may occur if several independent processes are sequentially performed on areas that have been imported redundantly. this is.

This is because the calculation results of other processors cannot be referenced.

This is done by performing the same processing on one overlapping area within a plurality of unit processors.

Such overhead can be avoided by connecting processors in multiple stages and introducing pipeline processing. Therefore, a multiprocessor architecture that enables the connection of input buses and output buses to be switched between processors and provides an optimal multi-stage configuration according to the application was published in the Proceedings of the 1986 IEICE Telecommunications Division National Conference. It is proposed in Volume 1, Section 208.

(Problem to be Solved by the Invention) However, when transferring commands such as control parameters from an external host computer to a play processor that connects multiple processors and performs real-time processing, the following is required. It is necessary to solve the problems described below.

First, the host computer usually uses a general-purpose processor, but the array processor side operates with a faster lock independent of the host in order to maximize the performance of the arithmetic circuit. Therefore, it is often difficult to transfer commands to each of a large number of processors due to changes in the operation content while the array processor is operating due to limitations in the transfer capacity of the host computer.

Furthermore, in the array processor that performs multi-stage processing as described above, unlike the case where all processors process the same input in parallel, each processor processes the data at different timings by the processing delay required for processing at each stage. It's working. Therefore, if the processing content in each processing stage is changed simultaneously by transferring commands from the host computer twice, a synchronization difference between the processors will occur.

For example, consider a case where each processor processes a video signal while thinning out frames. At this time, if you change the thinning rate while operating in real time for multiple processors performing multi-stage processing, the frames to be processed may differ in each stage of pipeline/processing. .

In particular, without communication between processors as described above,
In a play processor in which each processor operates based only on a synchronization signal of an input signal, once such a synchronization error occurs, it is impossible to resynchronize the processors.

Therefore, an object of the present invention is to transfer control commands from a host processor that operates asynchronously to the synchronization signal to a processor array that connects a plurality of processors that operate in real time in series and performs pipeline processing. The present invention aims to present a command transfer method that does not cause synchronization between processors due to processing delays in each pipeline stage, and at the same time to provide a circuit configuration for realizing the command transfer method.

(Means for Solving the Problem) The first invention realizes pipeline processing by connecting a plurality of processors in series that take in an input signal within the period of a synchronization signal, process it, and output the processing result. In this method, a control command is transferred from a host computer to each processor in a processor array, and the control command to be transferred is stored from the host computer in a storage means corresponding to each of the plurality of processors, and then is transferred from the storage means. The present invention is characterized in that transfer to each processor is started from the input side of the play processor in accordance with the connection order of the processors.

The present invention of fa2 involves connecting a plurality of processors in series that take in input signals within the period of a synchronization signal, process them, and output the processing results, and send control commands from a host computer to a processor array that realizes pipeline processing. It is an interface circuit provided for each processor to transfer the input synchronization signal from the outside, and a delay circuit that delays the input synchronization signal supplied from the outside by the amount of processing delay in the corresponding processor and outputs it to the outside, and a delay circuit that delays the input synchronization signal supplied from the outside by the amount of processing delay in the corresponding processor and outputs it to the outside. Command to be executed?
Based on the input synchronization signal (based on the packer memory to store the data and instructions from the host computer), a control signal is generated that instructs the start of command transmission from the buffer memory to the corresponding processor and also notifies the start of command transmission. It is characterized in that it consists of a control section that outputs to the outside.

The third invention provides a control command from a host computer to a processor array that realizes pipeline processing by connecting a plurality of processors in series that take in input signals within the period of a synchronization signal, process them, and output processing results. This is an interface circuit installed in each processor to transfer the input synchronization signal, which delays the input synchronization signal by the amount of processing delay in the corresponding processor and outputs it to the outside, and a buffer memory for storing commands to be sent to the corresponding processor; and a control unit that, under control from the host computer, instructs to start sending commands from the buffer 1 memory to the corresponding processor in synchronization with an input control signal supplied from the outside; It is characterized by comprising a second delay circuit that delays the command sending start signal generated by the control unit by a value specified by the host computer and outputs the delayed signal to the outside.

(Operation) In the command transfer method according to the present invention, a command buffer is provided for each processor in order to absorb the difference between the operating clock on the array processor side and the command transfer speed on the host computer side. Therefore, the host computer can generate control commands regardless of the operating speed and operating state of the transfer destination processor.

Once written to the buffer in this way.

Transfer to each processor can be performed independently from each buffer in synchronization with the operations on the processor side.

Even if each processor is composed of multiple unit processors as described in the prior art section, as long as the number of unit processors corresponding to one command buffer is commensurate with the transfer capacity from the command buffer. , commands can be transferred from one command buffer to multiple unit processors within a limited time.

Next, in the command transfer method according to the present invention, in order to eliminate the synchronization error pointed out as a problem in the conventional technology, the time at which the command is transferred from the command buffer to each corresponding processor is determined according to the processing delay at each stage of multi-stage processing. Adopt a method that delays the

At this time, in multi-stage processing by serially connecting processors,
Since processing delays inevitably accumulate from the input side to the output side of the connection, synchronization errors can be eliminated by delaying command transfer to the aR processor in accordance with the processing delays.

In order to realize such command transfer, the command transfer circuit according to the present invention is controlled by the host computer to enable writing from the host computer, a state of waiting for transfer to the corresponding processor, and a state of transfer to the processor. It has three states.

In the first state, ie, a state in which the host computer can write, the host computer can always write and store commands in its command buffer. In the second state, that is, in the transfer waiting state, it waits until it receives a control signal from the previous stage command transfer circuit indicating that it can be sent. In the state of waiting for transfer, when receiving a control signal from the preceding stage command transfer circuit informing that the command can be sent, it shifts to the third state, that is, the state of sending commands to the corresponding processor in synchronization with the input synchronization signal. do. When command transmission is started in synchronization with the input synchronization signal, a control signal is generated to notify the next-stage command transfer circuit that the command can be transmitted.

In this way, by storing the commands to be transferred from the host computer in each command buffer and setting them in a transferable state, the commands can be synchronized with the next input synchronization signal, and the transfer from the input side can be performed. Achieves orderly command transfer.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the first invention.

In the figure, 1 is a host computer, 2. 3. 4 is a processor, 5.6. 7 is a command transfer circuit provided corresponding to each of the processors 3, 4, and 5; 8 is a data input terminal; 9 is a data output terminal; 22 is a synchronization signal input terminal;
21 is a control signal generator.

The processor 2.3.4 has several programs built-in in advance and transfers commands from the host computer 1 to the command transfer circuits 5 and 6.
．． Based on commands sent via 7, processing contents are selected and processing parameters are changed.

The processor 2 receives and processes the input signal supplied to the data input terminal 8 based on the synchronization signal supplied from the synchronization signal input terminal 22. The processing results of the processor 2 become data input to the processor 3 as they are. On the other hand, the command transfer circuit 5 supplies the synchronization signal input from the synchronization signal input terminal 22 to the next-stage command transfer circuit 6 and the processor LK after being delayed by the processing delay by the processor 2. Therefore, the processor f3 can take in and process the processing results of the processor 2 based on the synchronization signal supplied from the command transfer circuit 5, regardless of the processing delay in the processor t2. Similarly, the processor 4 can also take in and process the processing results of the processor 3 based on the synchronization signal delayed by the command transfer circuit 6.
As described above, pipeline processing is realized by serially connected processors by delaying the synchronization signal in accordance with the processing delay caused at each stage of pipeline processing and passing it on to the next stage.

The host computer 1 connects the command transfer circuit 5.
6. Write the command to be transferred to the frame/dopa sofa in 7. At this time, the command transfer circuits 5, 6. 7 is in write mode from the host computer 1, and command transfer circuits 5, 6.7 to the corresponding processors 2.
No commands are transferred to 3.4. After storing all the commands to be transferred in the command transfer circuits 5, 6.7 in this manner, the host computer 1 puts the command/word transfer circuits 5, 6.7 into a transfer waiting state via the bus.

Thereafter, the host computer 1 instructs the control signal generator 21 to generate a control signal.
A control signal is generated from the command transfer circuit 5 to inform the command transfer circuit 5 that the command can be sent.

The command transfer circuit 5 is already in a transfer waiting state from the host computer 11C, and the control signal generator 21
When it is notified that the command can be sent from the processor 2, it starts transferring the command to the processor 2 in synchronization with the synchronization signal supplied to the input synchronization signal terminal 22. The command transfer circuit 5, at the same time as starting command transfer, issues a control signal to the command transfer circuit 6 to inform it that the command can be sent.

The command transfer circuit 6 is already in a transfer waiting state by the host computer 1 and is informed by the command transfer circuit 5 that the command can be sent, so that the command transfer circuit 5 only delays processing by the processor 2. Command transfer to the processor 3 is started in synchronization with the delayed synchronization signal. Therefore, the command is transferred to the processor 3 using the same synchronization signal as the command is transferred to the processor 2. Like the command transfer circuit 5, the command transfer circuit 6 starts command transfer and simultaneously issues a control signal to notify the next-stage command transfer circuit 7 that the command can be sent.

Similarly to the command transfer circuit 6, the command transfer circuit 7 also has the following functions:
Command transfer to the processor 4 is started by a control signal and a synchronization signal issued by the command transfer circuit at the previous stage to inform that the command can be sent.

With the above method, a control signal and a synchronization signal indicating that a command can be sent are passed between the serially connected command transfer circuits 5, 6, and 7 along the signal flow, thereby creating a multi-stage connection. This enables a command transfer method that does not cause synchronization deviations due to processing delays between the processors.

FIG. 2 shows an embodiment of a command transfer circuit according to the second invention.

In the figure, 14 is a buffer memory, and 15 is for delaying the synchronization signal supplied to the synchronization signal output terminal 10.

A delay circuit 16 outputs to the synchronization signal output terminal 11, and 16 is a control section, the details of which are shown in FIG.

Further, one command transfer circuit is connected to a host computer via a terminal 19, and commands are sent to a corresponding processor via a terminal 20. 12 is a control signal input terminal;
13 is a control signal output terminal.

The buffer memory 14 is a first-in, first-out storage circuit into which commands are written from the host computer 1 via a terminal 19 and sequentially outputs the stored commands to a terminal 20 based on a control signal from the control unit 16.

Command output is started by the rise of the control signal from the control unit 16, and is sequentially read out until all stored commands are transferred to the processor. At this time, reading is performed using the clock on the processor side.

The delay circuit 15 delays the synchronization signal supplied to the synchronization signal input terminal 10 by a value set from the host computer 1 via the terminal 19 and outputs the delayed synchronization signal to the synchronization signal output terminal 11 . The delay circuit 15 can delay the synchronization signal by the same amount as the amount of processing delay by the processor corresponding to the command transfer circuit, and send it to the next-stage command transfer circuit.

As shown in FIG. 4, the control unit 16 has a 1-bit register 30. Gate 31 and D type 2 lip 70 knob 3
Consists of 2.

The host computer 1 writes the value "On" to the register 30 via the terminal 19, supplies "O" to the reset terminal R of the 7-lip flop 32, and initializes the 7-lip flop 32 to @θ". This state is the first state, that is,
This corresponds to a state in which the host computer 1 can write to the buffer memory 14.

Next, when the host computer 1 finishes storing the commands to be transferred to all command transfer circuits, it sets the contents of the register 30 to 11'' and enters the second state, that is, the command can be sent from the previous command transfer circuit. The control signal is in a state of waiting for a control signal to notify the user of a certain situation.Here, when the value input to the control signal input terminal 12 is 1'', the command can be sent.

In this state, when the synchronization signal rises from 0 to 1, the D type clip 70 knob 32 changes the value of the gate 31,
That is, since the logical product 11'' of the register 30 and the input terminal 12 is taken in, the signal changes from 'mO' to '1'. This corresponds to the third state, that is, a state in which commands are sent to the corresponding processors in synchronization with the synchronization signal supplied to the synchronization signal input terminal 10. D type clip flop 3
2 changes from ``0'' to ``1''.

Via the output terminal 33, the buffer memory 14 in FIG. 2 is instructed to start sending commands. Simultaneous K.

Since the control signal output terminal 13 also becomes @1'', this means that a control signal is issued to notify the command transfer circuit connected to the primary stage that the command can be sent.

When this command transfer circuit is used in the array processor shown in FIG. 1, the control signal generator 21 shown in FIG.
It suffices to always output ``1'' regardless of the synchronization signal.

FIG. 3 shows an embodiment of a command transfer circuit according to the third aspect of the present invention.

In the figure, 14 is a buffer memory, 15 is a first delay circuit that delays the synchronization signal supplied to the synchronization signal input terminal 10 and outputs it to the synchronization signal output terminal 11, and 17 is a control section, the details of which are explained in the fifth section. As shown in the figure. 18 is a second delay circuit that delays the control signal generated by the control section 17. Further, one command transfer circuit is connected to a host computer via a terminal 19, and commands are sent to a corresponding processor via a terminal 20. 12 is a control signal input terminal, and 13 is a control signal output terminal.

The buffer memory 14 is a first-in, first-out storage circuit into which commands are written from the host computer l via a terminal 19 and sequentially outputs the stored commands to a terminal 20 in response to a control signal from the control unit 16. Command output is started by the rise of the control signal from the control unit 17, and is sequentially read out until all stored commands are transferred to the processor. At this time, reading is also performed using the clock on the processor side.

The delay circuit 15 delays the synchronization signal supplied to the synchronization signal input terminal 10 by a value set from the host computer 1 via the terminal 19 and outputs the delayed synchronization signal to the synchronization signal output terminal 11 . The delay circuit 15 can delay the synchronization signal by the same amount as the amount of processing delay by the processor corresponding to the command transfer circuit, and send it to the command transfer circuit at the primary stage.

The control section 17 is composed of a 1-bit register 40 and a D-type flip-flop 42, as shown in FIG. 1 host computer, terminal 19f: register 4 via
By writing the value @0'' to 0, the reset terminal RK''
0'' to initialize the D-type clip 70 knob 42 to 0.

This state corresponds to the first state, ie, the state rC in which the host computer 1 can write to the buffer memory 14.

Next, when the host computer 1 finishes storing the commands to be transferred to all command transfer circuits, it sets the contents of the register 40 to ``1'' and enters the second state, that is, the command is sent from the previous command transfer circuit. The state is set to wait for a control signal informing that it is possible. In this state, when the control signal supplied to the control signal input terminal 12 rises from 'θ'' to @1'', the D type clip 70 knob 42 takes in the value of the register 40, so it changes from @O'' to 11''. Changes to This means that the buffer memory 14 in FIG. 2 is instructed to start sending the command. At the same time, the value of the D type clip 70 tube 42 is outputted to the delay circuit 18 in FIG. 3 via the control signal output terminal 13.

Since the delay circuit 18 is set in advance by the host computer 1 to delay the synchronization signal by the same amount as the amount of processing delay by the corresponding processor, the control signal output terminal 13 in FIG. 3 is the same as the output terminal in FIG. 5. 44 from 'mO''to'''
After changing by 1''K, the value changes from ``0'' to @1 with a delay of the amount of processing delay by the corresponding processor. In this way, a control signal is issued to inform the command transfer circuit connected to the next stage that the command can be sent.

When this command transfer circuit is used in the array processor shown in FIG. 1, the control signal generator 21 shown in FIG.
can be obtained by using the same delay circuits as delay circuits 15 and 18 in FIG. Therefore, by setting the delay amount of the control signal generator 21, the synchronization signal of the input signal and the timing at which one command transfer is started can be arbitrarily set within one cycle of the input signal.

(Effects of the Invention) As described above, according to the present invention, there is no synchronization difference between processors due to the processing delay iK of each pipeline stage, and there is no synchronization difference between the processors from the host computer to the processor array performing pipeline processing. / file transfer is possible.

Furthermore, even if the processor becomes out of synchronization due to a malfunction within the system, it can be recovered by transferring a command from the host computer.

Further, in the command transfer method according to the present invention, since control signals are passed between adjacent processors, it is possible to provide a highly expandable multiprocessor system that does not depend on the number of processors.

[Brief explanation of the drawing]

Fig. 1 shows an enlarged view of the first invention, Fig. 2 shows an embodiment of the second invention, Fig. 3 shows an embodiment of the third invention, and Fig. 4 shows details of the main parts of Fig. 2. FIG. 5 is a diagram showing details of the main part of FIG. 3. 1...Host computer, 2,3.4...
Processor, 5.6.7...Command transfer circuit, 8...Data input terminal, 9...Data output terminal, 14...Buffer memo 1 1
5,18...Delay circuit, 16゜17...
...control unit, 10.22 ... synchronization signal input terminal, 11 ... synchronization signal output terminal, 12 ...
... Control signal input terminal, 13 ... Control signal output terminal, 21 ... Control signal generator, 30.4
0...Register, 31...Gate, 32.42...D type frig 7
0 tsubu. Agent Patent Attorney Uchihara Otokyo 1 Kokyo 2 Kokyo 3vi! J 4th shift

Claims (3)

[Claims] (1) Capture and process the input signal within the period of the synchronization signal,
Connect multiple processors in series to output processing results,
A method of transferring control commands from a host computer to each processor of a processor array that implements pipeline processing, wherein the control commands to be transferred are stored in storage means corresponding to each of the plurality of processors from the host computer, and then , from the storage means to each processor,
A command transfer method characterized in that transfer is started from the input side of a processor array in accordance with the connection order of processors. (2) Capture and process the input signal within the period of the synchronization signal,
Connect multiple processors in series to output processing results,
An interface circuit provided for each processor to transfer control commands from a host computer to a processor array that implements pipeline processing, and is used to transfer input synchronization signals supplied from the outside to processing delays in the corresponding processor. a delay circuit that delays the command by a certain amount and outputs it to the outside; a buffer memory that stores commands transferred from the host computer;
A command transfer characterized by comprising a control unit that instructs to start sending a command from the buffer memory to a corresponding processor in synchronization with the input synchronization signal, and generates and outputs a control signal to the outside to notify the start of sending the command. circuit. (3) Capture and process the input signal within the period of the synchronization signal,
Connect multiple processors in series to output processing results,
An interface circuit provided in each processor to transfer control commands from a host computer to a processor array that implements pipeline processing, which delays input synchronization signals by the amount of processing delay in the corresponding processor and outputs them to the outside. a first delay circuit for storing commands transferred from the host computer; a buffer memory for storing commands transferred from the host computer; and a first delay circuit for starting sending commands from the buffer memory to the corresponding processor under control from the host computer.
a control unit that gives an instruction in synchronization with an input control signal supplied from the outside; and a second delay circuit that delays the command sending start signal generated by the control unit by a value specified by the host computer and outputs the delayed command to the outside. A command transfer circuit comprising: