JPH10105375A - Asynchronous fifo buffer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the asynchronous FIFO buffer device with high access efficiency by synchronizing asynchronous information by a simple control method, and grasping the quantity of data in the asynchronous FIFO buffer and guaranteeing secure continuous access. SOLUTION: This buffer device is equipped with a 1st readable asynchronous FIFO buffer 20 and a 2nd asynchronous FIFO buffer 24 where one of the number of write data and the number of read data can be written and read. A write control circuit 21 writes the number of write data of the 1st asynchronous FIFO buffer 20 to the 2nd asynchronous FIFO buffer 24 by a counter 23 and an AND gate 25. A read control circuit 22 reads the written number of data and reads data corresponding to the number of data out of the 1st asynchronous FIFO buffer 20 together at a time. Even when access circuits share a read-side data bus, the overhead for bus acquisition can be reduced and the data transfer can be performed with efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronously input / output FIFO buffer device, and more particularly to a data input / output control method for a FIFO buffer.

[0002]

2. Description of the Related Art Conventionally, two clocks are operated with different clocks.
When performing data transfer between two devices, data is handled in each device in synchronization with a clock in each device. Therefore, for data sent from a device having a different clock, the data must be synchronized with its own clock. Normally, an asynchronous FIFO buffer is used to synchronize data handled at the asynchronous timing. This asynchronous FIFO buffer is
The timing of writing to the FO buffer and the timing of reading from the FIFO buffer are completely independent, and transfer data can be easily synchronized with the clock in the device.

For example, in a hard disk device connected to a SCSI bus, when data transmitted from the SCSI bus is received, the data is transferred from the SCSI bus asynchronously with the operation in the hard disk device. By arranging the data, the transmitted data can be easily taken into the device in synchronization with the operation clock in the hard disk device. For example, JP-A-3-1
Japanese Patent Application Publication No. 02450 describes that data is efficiently transferred using an asynchronous FIFO buffer.

FIG. 3 shows a basic configuration of the asynchronous FIFO buffer. This FIFO buffer has n bits x 8
A FIFO register 1 composed of registers at each stage, a write pointer 2 and a read pointer 3 for selecting one of the registers, and a status signal for indicating whether the FIFO register is empty or data exists. The status generating circuit 4 generates the status. The write pointer 2 and the read pointer 3 have the same basic configuration.
Each time data is written to O, one in the FIFO register
Point to the register of the book. The update of the write pointer 2 is updated only by the write control signal,
It is not affected by the read control side. Similarly, the update of the read pointer 3 is updated only by the read control signal,
Not affected by the light control side.

FIG. 4 shows the internal configuration of the asynchronous FIFO buffer of FIG. Write pointer 2, Read pointer 3
Is composed of a 1-bit × 8-stage cyclic shift register. When these shift registers are initialized, only one bit is set to "1" to indicate the same FIFO register, and all other bits are set to "0". In writing to the FIFO register 1, one data is written to the FIFO register indicated by the write pointer 2 by the write control signal. Each time the writing is completed, the shift register in the write pointer 2 is shifted by one bit, and the next FIFO register 1 is selected.

In the case of reading data from the FIFO register 1, data of the FIFO register 1 selected by the read pointer 3 is output by a read control signal.
At the end of reading, the shift register in the read pointer 3 is shifted by one bit, and the next FIFO
The O register is selected. These write and read operations do not need to be performed in synchronization with each other.
Writing to and reading from the register can be performed independently.

In the status generation circuit 4, if the statuses of the two pointers match after the read operation based on the output signal of each pointer, the status is empty.
Conversely, when the two pointers match after the write operation, the full signal 16 is activated because it indicates that the y signal 17 is occupied. These signals are cleared when the states of the two pointers no longer match.

[0008]

As described above, the role of the asynchronous FIFO buffer is to smoothly transfer data between systems operating with two different clocks, and the conventional asynchronous FIFO buffer has a disadvantage in that respect. Plays a sufficient role because writing to the FIFO and reading from the FIFO can be performed without affecting each other. However, it is difficult to know in real time how much data exists in the FIFO because writing and reading are asynchronous. Taking a conventional asynchronous FIFO buffer as an example, whether or not data exists in the FIFO can be determined by whether or not the contents of the read pointer and the write pointer are different. However, how much data is stored must be determined by the difference between the two pointers. If the two operate at the same operation clock to determine the difference, it is easy to compare the contents of the pointers and the time required to determine the difference is short. Must be extracted after synchronizing the contents of either pointer with the operating clock of the other pointer. If the operating speeds of the two pointers are significantly different, the time required to compare the pointers will increase.

Normally, in a system using an asynchronous FIFO buffer, one of the data buses on the read side or the write side is often shared with another device accessing the same data bus. For example, S
In the case of a computer connected to the CSI bus, one of the asynchronous FIFO buffers used for transmitting and receiving data on the SCSI bus is connected to the data bus of the computer, and this data bus is usually shared by the CPU and the DMA controller. I have. At this time, in order to use the data bus efficiently, the procedure for acquiring the bus access right must be reduced, and once the data bus has been acquired, the data must be transferred continuously. For that purpose, it is necessary to grasp the number of data in the FIFO buffer and access the FIFO buffer after reaching a certain predetermined level. However, as described above, it is difficult for the asynchronous FIFO buffer to grasp the amount of data in the FIFO buffer, and it takes time to determine whether the data has reached a predetermined level. Therefore, the judgment time until the start of the transfer is saved. Alternatively, the access to the asynchronous FIFO buffer is performed for each access to determine whether or not there is a space for writing, and to determine whether or not there is data for reading, and each time requires an overhead for acquiring an access right. I have.

An object of the present invention is to provide an asynchronous FIFO buffer device which synchronizes asynchronous information by a simple control method, grasps the amount of data in an asynchronous FIFO buffer, guarantees reliable continuous access, and has a high access efficiency. It is in.

[0011]

According to the present invention, there is provided a first asynchronous FIFO buffer in which data can be written and read asynchronously, and a second asynchronous FIFO buffer in which one of the number of write data and the number of read data can be written and read. A first asynchronous FIFO
The writing or reading operation of data in the buffer is performed based on the number of data read from the second asynchronous FIFO buffer. As a preferred first mode of the present invention, the number of data to be written to the first asynchronous FIFO buffer is written to the second asynchronous FIFO buffer, and the data of the written number of data is collectively read from the first asynchronous FIFO buffer. Configuration. In a preferred second embodiment of the present invention,
The number of data read from the first asynchronous FIFO buffer is written in the second asynchronous FIFO buffer, and the data of the written number of data is collectively collected in the first asynchronous FIFO buffer.
It is configured to write in the O buffer.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a first embodiment of the present invention. The FIFO buffer of this embodiment is an n-bit × m-stage (n, m is an integer of 1 or more) asynchronous FIFO buffer, here, an 8-stage asynchronous FIFO with m = 8
This is an example in which data is input / output to / from the O buffer 20. In addition to the asynchronous FIFO buffer 20, n ′ bits × m ′ stages (n ′ and m ′ are integers of 1 or more), where m ′ = 2 The two-stage asynchronous FIFO buffer 24 is provided. Data according to the write control signal 12 generated by the write control circuit 21 is written to the 8-stage asynchronous FIFO buffer through the input data bus 10. The read control signal 13 generated by the read control circuit 22 causes
The data in the stage asynchronous FIFO buffer 20 is read,
Output to the output data bus 11. A counter 23 and an AND gate 25 are connected to the write control circuit 21, and the output of the data bus 32 of the counter 23 can be written to the two-stage asynchronous FIFO buffer 24 based on the output of the AND gate 25. It is said. Further, the read control circuit 22 includes the two-stage asynchronous FIFO
The data input to the O buffer 24 can be read.

In this configuration, when data is written to the eight-stage asynchronous FIFO buffer 20, the write control circuit 21 outputs the status signal 16 (the eight-stage asynchronous FIFO buffer is occupied) output from the eight-stage asynchronous FIFO buffer 20. The write control signal 12 is generated in response to the write control signal 12, and data is written to the 8-stage asynchronous FIFO buffer 20. The counter 23 performs a counter operation using the write control signal 12 as a clock, and activates the control signal 33 when a predetermined number is reached. AN
The D gate 25 receives the control signal 33 and the write control signal 1
6 and outputs the signal 34 to the two-stage asynchronous FIFO.
This is a write control signal for the O buffer 24. At this time, 2
The value written to the stage asynchronous FIFO buffer 24 is the value output from the counter 23, and this value indicates the number of data written to the 8-stage asynchronous FIFO buffer 20 so far.

When writing to the two-stage asynchronous FIFO buffer 24 is completed, the counter 23 is cleared, and when data is written to a predetermined number of eight-stage asynchronous FIFO buffers 20, the control signal 33 becomes active again. And the same operation is repeated. For example, an 8-stage asynchronous F
Assuming that the above operation is performed every time data is written to the I / O buffer 20 four times, the value “4” is written to the two-stage asynchronous FIFO buffer 24 at the time of the fourth data writing.

On the other hand, when reading data from the eight-stage asynchronous FIFO buffer 20, the read control circuit 22 outputs the status signal 31 (two-stage asynchronous FIFO buffer 2) output from the two-stage asynchronous FIFO buffer 24.
4 is a signal indicating whether or not 4 is empty)
When recognizing that there is data in the FIFO buffer 24, the head data of the two-stage asynchronous FIFO buffer 24 is read. The two-stage asynchronous FIFO buffer 24 outputs the first data to the data bus 35 by the read control signal 30, and the data is input to the read control circuit 22.
This data indicates that the number of data indicated by the data has been written to the eight-stage asynchronous FIFO buffer 20. Therefore, the read control circuit 22 stores the data of that number in the eight-stage asynchronous FIFO buffer 20. The read control signal 13 is continuously output so as to read from the data, and the data is read.

As described above, when a predetermined number of data is written from the write side of the eight-stage asynchronous FIFO buffer 20, information data indicating the number of data is written to the two-stage asynchronous FIFO buffer 24. Then, by reading the information data written in the two-stage asynchronous FIFO buffer 24 from the reading side, the data can be unconditionally extracted from the eight-stage asynchronous FIFO buffer 20 by the number of times indicated by the information data. This is when the data transfer rate on the read side is faster than the write side,
In addition, when the read-side data bus is shared with a plurality of access circuits, data transfer can be efficiently performed. That is, when the data bus on the read side is acquired, the number of data that can be transferred continuously is guaranteed, so that the overhead for acquiring the bus can be reduced.

FIG. 2 is a configuration diagram of a second embodiment of the present invention. Here, parts equivalent to those in the first embodiment in FIG. 1 are denoted by the same reference numerals. In the second embodiment, the counter 23 counts the number of reads in the read control circuit 22, and writes the value 32 to the two-stage asynchronous FIFO buffer 24 by the signal 34 of the AND gate 25. The number of reads written to the two-stage asynchronous FIFO buffer 24 is determined by the write control circuit 21.
At the same time.

In this configuration, the write control circuit 21 writes data to the 8-stage asynchronous FIFO buffer 20 as in the conventional case. On the other hand, in the read control circuit 22, data can be read from the eight-stage asynchronous FIFO buffer 20 by the status signal 17 (signal indicating whether the eight-stage asynchronous FIFO buffer 20 is empty) output from the eight-stage asynchronous FIFO buffer 20. The data is read out by the read control signal 13 while judging whether or not the data is read. Then, the number of times of data reading is counted by the counter 23, and the number of times of reading is written to the two-stage asynchronous FIFO buffer 24 by the signal 34 of the logical product of the control signal 33 from the AND gate 25 and the read control signal 13.

The two-stage asynchronous FIFO buffer 24
Outputs the first data to the data bus 35 by the read control signal 30, and the data is input to the write control circuit 21. This data is stored in the 8-stage asynchronous FIFO buffer 2
Since 0 indicates that there is a vacancy of the number indicated by the data, the write control circuit 21 reads out the data of the number from the 8-stage asynchronous FIFO buffer 20 and the vacancy occurs. To recognize that the number of data can be written. Therefore, the write control circuit 21 can continuously write the next data by a predetermined number.

As described above, when a predetermined number of data is read from the write side of the eight-stage asynchronous FIFO buffer 20, information data indicating the number of data is written to the two-stage asynchronous FIFO buffer 24. Then, by reading the information data written in the two-stage asynchronous FIFO buffer 24 from the writing side, it becomes possible to write the data to the eight-stage asynchronous FIFO buffer 20 unconditionally the number of times indicated by the information data. This is because when the data transfer speed on the write side is higher than that on the read side, and when the data bus on the write side is shared with a plurality of access circuits, data transfer can be performed efficiently. . That is, when a write-side data bus is acquired, the number of data buses that can be transferred continuously is guaranteed, so that it is possible to reduce the overhead for acquiring the bus.

In the above embodiments, the number of stages of the first and second asynchronous FIFO buffers is m = 8, m '=
Although the case of 2 has been described, it goes without saying that an asynchronous FIFO buffer having the most suitable number of stages can be configured depending on the system configuration.

[0022]

As described above, the present invention comprises the first asynchronous FIFO buffer that can be read, and the second asynchronous FIFO buffer that can write and read either the number of write data or the number of read data. Since the operation of writing or reading data to or from the first asynchronous FIFO buffer is performed based on the number of data read from the second asynchronous FIFO buffer, writing to the first asynchronous FIFO buffer is performed by the second asynchronous FIFO buffer. When the data number is written, the data of the written data number can be read out from the first asynchronous FIFO buffer collectively.
Alternatively, the first asynchronous FIFO is stored in the second asynchronous FIFO buffer.
When the number of data to be read from the I / O buffer is written, the data of the number of the written data can be written to the first asynchronous FIFO buffer at a time. In this case, there is an effect that overhead for acquiring a bus can be reduced and data transfer can be performed efficiently. In addition, since the write amount and the read amount are transmitted between the write side and the read side via the second asynchronous FIFO buffer, control of extracting the information on the receiving side becomes very easy, and complicated timing is obtained. The effect that control and the circuit for it become unnecessary is also acquired.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional general asynchronous FIFO buffer.

FIG. 4 is a configuration diagram of a conventional asynchronous FIFO buffer register.

[Explanation of symbols]

20 8-stage asynchronous FIFO buffer (first asynchronous FIFO buffer)
FO buffer) 21 Write control circuit 22 Read control circuit 23 Counter 24 Two-stage asynchronous FIFO buffer (second asynchronous FI buffer)
FO buffer) 25 AND gate 30 Read control signal 31 Status signal 32 Data bus 33 Control signal 34 Write control signal 35 Data bus

Claims (5)

[Claims] A first asynchronous FIFO buffer capable of asynchronously writing and reading data; and a second asynchronous FIFO buffer capable of writing and reading either one of the number of write data and the number of read data, The operation of writing or reading data to or from the first asynchronous FIFO buffer is performed by the second asynchronous FIFO buffer.
An asynchronous FIFO buffer device which performs the determination based on the number of data read from a buffer. 2. The number of data to be written to the first asynchronous FIFO buffer is written to the second asynchronous FIFO buffer.
2. The asynchronous FIFO buffer device according to claim 1, wherein the data is read from the asynchronous FIFO buffer. 3. The asynchronous FIFO according to claim 1, wherein the number of data read from the first asynchronous FIFO buffer is written to the second asynchronous FIFO buffer, and the data of the written number of data is collectively written to the first asynchronous FIFO buffer. Buffer device. 4. An n-bit × m-stage (n, m is an integer of 1 or more) first asynchronous FIFO buffer;
Second asynchronous FI of m ′ stage (n ′, m ′ is an integer of 1 or more)
An FO buffer; a write control circuit that controls writing of data to the first asynchronous FIFO buffer; and a read control circuit that controls reading of data from the first asynchronous FIFO buffer. Means for writing the number of data written to the first asynchronous FIFO buffer to the second asynchronous FIFO buffer is provided, wherein the read control circuit reads the number of data written to the second asynchronous FIFO buffer;
An asynchronous FIFO buffer device having a function of collectively reading the data of the read data number from the first asynchronous FIFO buffer. 5. An n-bit × m-stage (n, m is an integer of 1 or more) first asynchronous FIFO buffer, and n′-bit ×
Second asynchronous FI of m ′ stage (n ′, m ′ is an integer of 1 or more)
An FO buffer; a write control circuit that controls writing of data to the first asynchronous FIFO buffer; and a read control circuit that controls reading of data from the first asynchronous FIFO buffer. Means is provided for writing the number of data read from the first asynchronous FIFO buffer to the second asynchronous FIFO buffer. The write control circuit reads the number of data written to the second asynchronous FIFO buffer, and calculates the number of data read. An asynchronous FIFO buffer device having a function of collectively writing data to a first asynchronous FIFO buffer.