JPH05334423A - Image processor - Google Patents

Abstract

PURPOSE:To effectively continuously and rapidly execute the input and processing of an image and the output of a processed result by a pipeline system without increasing the size of hardware in an image processor. CONSTITUTION:Image data to be processed which are formed from a camera 1 through an A/D converter 20 are successively and cyclically stored in frame memories 5 to 7 in each frame and in each vertical scanning period (1V). Image buses 8 to 10 are connected to the memories 5 to 7 by 1 to 1, the image data of the frame memories 5 to 7 are successively transferred to I/O buffers 11 to 13 in each 1V. An image processor 14 successively switches the buffers 11 to 13 in each 1V through a switch 24, processes the image data outputted from the selected buffer and outputs the processed result to a data bus 16 e.g. to output it to the external through a control CPU 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for inputting image data from an ITV camera or the like, performing image processing by an image processing processor, and outputting the result to the outside.
In particular, the present invention relates to an image processing apparatus having a pipeline processing function for continuously executing image processing at high speed.

In the following figures, the same reference numerals indicate the same or corresponding parts.

[0003]

2. Description of the Related Art FIG. 3 shows an example of the configuration of a conventional normal image processing apparatus. In the figure, 1 is a T using a CCD element or the like.
The V camera 2 is an image input / output board for A / D converting the image signal of the camera 1 and inputting it to a frame memory (not shown), or D / A converting the image data of the frame memory and outputting it to the monitor TV 30. Reference numeral 3 is a board provided with a processor for performing image processing, 4 is a board provided with a control CPU for performing bus control, and BS is a system bus for connecting the image input / output board 2, the image processing processor board 3, and the control CPU board 4. And the image bus.

By the way, conventionally, in the image processing apparatus,
The following methods have been applied to execute image processing at high speed. The hardware of the functions of the image processing processor 3, the application of a high-speed image processing processor (LSI) as the image processing processor 3, and the parallelization of the image processing functions.

As this method, as shown in FIG. 4, image processing processor boards having the same function are provided as 3-1 and 3-2.
3-3 are prepared in a plural number, and the image processor of each board is sequentially made to process different image data by one vertical scanning period (abbreviated as 1V), which is cyclically repeated.

[0006]

However, in the above-mentioned method, the contents of the image processing have to be almost fixed, resulting in sacrificing the versatility / programmability of the processing. In addition, the above method is a large-scale LSI
This often drives the technology, resulting in increased development costs and often not always applicable to all applications.

Further, the above method has a drawback that the scale is increased in terms of circuit and cost. Therefore, the present invention provides an image processing device capable of improving the processing speed without increasing the circuit or the configuration scale of the image processing device and without developing a dedicated LSI or dedicated hardware. It is an issue.

[0008]

In order to solve the above-mentioned problems, an image processing apparatus according to claim 1 has an ITV camera (1,
In an image processing apparatus for inputting image data to be processed from the A / D converter 20) or the like, processing the image data, and outputting the processing result to the outside, a plurality of frame memories (5 to 7)
And means for sequentially and cyclically storing the image data to be processed in the frame memory, one frame at a time for each vertical scanning period (switcher 22 or the like).
And an image bus (8) provided for each frame memory.
(10 to 10) and the like, the image data for one frame is input cyclically and cyclically from each of the frame memories in each cycle through the image bus corresponding to the frame memory to perform the processing described above. Image processing means (switching device 24, image processing processor 14, etc.).

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the image processing means outputs the processing result to the outside by a bus different from the image bus (data bus 16). Etc.). According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, the image data for one frame stored in the frame memory is sequentially arranged from the frame memories in each cycle. And means for cyclically extracting and displaying on the monitor (switch 23, D / A converter 21, monitor TV 30, etc.)
Means for transferring the image data for each frame processed through the image processing means to the frame memory through the image bus cyclically and cyclically in the cycle, and displaying it on the monitor display means. Output buffer 1
1 to 13, control CPU 17, etc.).

[0010]

In the image processing apparatus, generally, image input processing (including output processing for simultaneously displaying the input images), image processing (processing for extracting area, length, characteristic points, etc. from the input image), processing results The output process of, and the three processes of are continuously performed. In addition, to speed up the image processing means (1) speeding up each of these series of processing, and (2)
It is necessary to be able to continuously operate without waste during the processing operation of.

In the present invention, in order to enable the processing flow up to to be performed continuously and at high speed without increasing the circuit scale, the speeding up is realized by means of making the flow of image data parallel. It is a thing. That is, when data is transferred between the image input means, the image processing means, and the processing result output means, a plurality of image buses through which image data flows are provided, and further, the image input means, the image processing means, the image bus, etc. By providing a data bus for external output of control and processing results separately from the image bus described above, it is possible to continuously perform data flow between each means of image input / processing / output of processing results. To do.

That is, each time the image data is input, the input means temporarily buffers it in the frame memory and then transfers it to the processing means. The processing means processes the input data and then makes it possible to transfer the result to the output means. This is realized by providing a plurality of image buses for the input system and a data bus for the output system separately from the input.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of the image processing apparatus of the present invention, and FIG. 2 is an explanatory diagram of the pipeline operation of image processing in FIG. In FIG.
This image processing apparatus includes an image input / output board 2 for inputting an image from a CCD camera 1 and displaying an image on a monitor TV 30, an image processing processor board 3 for executing image processing,
A control CPU board 4 for controlling each of the boards 2 and 3 and 8 to 10 and 16 to be described below and externally outputting the image processing result, and three systems of image buses 8, 9, and 10 as a bidirectional bus for image data, And a data bus 16 of one system used for transfer of control data from the control CPU board 4 and external output of image processing results from the image processing processor board 3. In the following, for convenience, the image buses 8, 9 and 10 are also referred to as image buses A, B and C, respectively,
The data bus 16 is also called a data bus D.

In the image input / output board 2, 20 is an A / D converter for converting an analog grayscale image signal output from the CCD camera 1 into a digital signal, and 5, 6 and 7 are image buses 8, 9 and respectively. 10 is a frame memory provided corresponding to 10, and this frame memory is composed of a dual port RAM capable of writing and reading simultaneously.

Reference numeral 22 is a switcher for cyclically switching the grayscale image signal output from the A / D converter 20 for each vertical scanning period (1 V) to the frame memories 5 to 7, and 23 is each frame memory. The image data of 5 to 7 are cyclically switched in order of 1V and taken out, and D /
A switch for giving to the A converter 21 is a D / A converter for D / A converting the image data given by the switch 23 and displaying it on the monitor TV 30.

In the image processor board 3, 14 is an image processor, and 11, 12, and 13 are input / output buffers provided corresponding to the image buses 8, 9, and 10, respectively, which read and write. It has a so-called double buffer structure that can simultaneously perform. 24
Is a switcher that cyclically switches the input / output buffers 11 to 13 by 1 V in order and connects to the image processor 14, and 15 outputs the processing result of the image processor 14 to the data bus 16 or from the control CPU board 4. It is an input / output buffer for inputting control data of.

In the control processor board 4, 1
7 is the control CPU, 19 is the control CPU 17, and the image bus 8 to
A bus interface for controlling transfer permission of the data bus 16 and the data bus 16, and an output interface 18 for outputting the image processing result input by the control CPU 17 from the image processing processor board 3 via the data bus 16 to the outside. ..

As described above, the image input / output board 2 is provided with three systems of frame memories 5 to 7 for storing image data corresponding to the image buses 8 to 10. Further, the image processing processor board 3 also has the above-described three systems of image buses 8 to
10 are sequentially input to the image processing processor 14 via the input / output buffers 11 to 13, respectively, and by connecting the processor 14 to the data bus 16,
The processing result can be output to the outside via the control CPU board 4. The control CPU board 4 has a function of controlling the image buses 8 to 10 and the data bus 16, and also has a function of outputting the processing result transferred from the data bus 16 to the outside.

The image data input from the ITV camera 1 is sequentially input to the frame memories 5 to 7 for each frame unit (that is, for each 1V). That is, the first image frame goes into the frame memory 5, the next image frame goes into the frame memory 6, and the next image frame goes into the frame memory 7. Further, the next image frame repeats the operation of entering the frame memory 5 again.

The image data first input to the frame memory 5 is displayed on the monitor TV 30 via the path of the internal bus → switch 23 → D / A converter 21 on the one hand, and on the other hand after this display, the frame memory 5 is displayed. From the image processing processor board 3 via the image bus 8
1, and the image processing is performed by the image processor 14. During the 1V period, the image data stored in the frame memory 6 of the image input / output board 2 is transferred to the input / output buffer 12 of the image processor board 3, and is stored in the frame memory 7 of the image input / output board during the next 1V period. The operation in which the image data being transferred is transferred to the input / output buffer 13 of the image processor board is repeated. On the image processor 14 side, when the processing of the input / output buffer 11 is completed, the processing result is output by the input / output buffer 15 and then the processing of the input / output buffer 12 is performed. The operation of shifting to the processing is sequentially repeated. The processing result is the input / output buffer 15
Are sequentially transferred to the control CPU board by the data bus 16, and the processing result is output to the outside by the output interface 18.

The image input / output boat 2 and the image processor board 3 are connected to the image buses 8 to 10 and the data bus 1.
6 together with the bus interface 1 of the control CPU board 4
The input / output timing is controlled by 9. That is, the control CPU 17 controls the permission to use the bus, and the image input / output board 2 and the image processing processor board 3 cannot output data to the bus unless the permission to use each bus is obtained. This makes it possible to prevent data collision on the bus and process image data in a pipeline manner.

FIG. 2 is a timing chart showing the operations of image data transfer, image processing and result output of FIG.
Next, FIG. 2 will be described with reference to FIG. In this example, it is assumed that the image input for one frame, the image processing, and the output of the processing result are completed within one vertical scanning effective period (1V). Further, in the following, the processing contents for each vertical scanning period of 1V to 6V of FIG.

(1) First V: (Processing i) The image (1) is input from the camera 1 through the A / D converter 20 to the frame memory 5 by the switch 22. As described above, simultaneously with this input, the image (1) is displayed on the monitor TV 30 via the internal bus 31, the switch 23, and the D / A converter 21. Although not described again, the display operation performed simultaneously with the input of this image is the same for the following images (2) to (5).

(2) Second V: (Processing i) The image (2) is input from the camera 1 to the frame memory 6 through the A / D converter 20. (Process ii) The image (1) is transferred to the input / output buffer 11 via the image bus A, and the image (1) is processed by the processor 14. As a result, the result image (1a) is generated and stored in the same input / output buffer 11.

The (process i) and the (process ii) are simultaneously performed in parallel. (3) Third V: (Processing i) The image (3) is input to the frame memory 7 from the camera 1 through the A / D converter 20 and the switch 22. (Process ii) The image (2) is transferred from the frame memory 6 to the input / output buffer 12 via the image bus B, and the image (2) is processed by the processor 14. As a result, the result image (2a) is generated and stored in the same input / output buffer 12.

(Processing iii) The result image (1a) is the image bus A.
Is transferred from the input / output buffer 11 to the frame memory 5, and the resultant image (1a) is displayed on the monitor TV 30 via the switch 23 and the D / A converter 21. Note that (Process i), (Process ii), and (Process iii) are simultaneously performed in parallel. (4) Fourth V: (Processing i) The image (4) is input from the camera 1 through the A / D converter 20 to the frame memory 5 by the switcher 22.

(Process ii) The image (3) is transferred from the frame memory 7 to the input / output buffer 13 via the image bus C,
And the image (3) is processed by the processor 14.
As a result, the result image (3a) is generated and stored in the same input / output buffer 13. (Processing iii) The resulting image (2a) is transferred from the buffer 12 to the frame memory 6 by the image bus B, and the switch 23
The resultant image (2a) is displayed as an image on the monitor TV 30 via the D / A converter 21.

[Process i], Process ii and Process
iii) is performed in parallel at the same time. (5) 5th V: (Processing i) The image (5) is input from the camera 1 through the A / D converter 20 to the frame memory 6 by the switch 22. (Process ii) The image (4) is transferred from the frame memory 5 to the buffer 11 via the image bus A, and the image (4) is processed by the processor 14. As a result, the result image (4a) is generated and stored in the buffer 11.

(Processing iii) The resulting image (3a) is the image bus C.
Is transferred from the buffer 13 to the frame memory 7 by
The resulting image (3a) is displayed as an image on the monitor TV 30 via the switch 23 and the D / A converter 21. Note that (Process i), (Process ii), and (Process iii) are simultaneously performed in parallel. (6) Sixth V: (Processing i) The image (6) is input to the frame memory 7 from the camera 1 through the A / D converter 20 and the switch 22.

(Process ii) The image (5) is transferred from the frame memory 6 to the buffer 12 via the image bus B, and the image (5) is processed by the processor 14. As a result, the result image (5a) is generated and stored in the buffer 12. (Processing iii) The resulting image (4a) is transferred from the buffer 11 to the frame memory 5 by the image bus A, and the switching unit 23
The resultant image (4a) is displayed as an image on the monitor TV 30 via the D / A converter 21.

[Process i], Process ii and Process
iii) is performed in parallel at the same time. (7) The same process is repeated for the 7th and subsequent voltages.

[0032]

According to the present invention, the image data to be processed, which is input from the camera 1 or the like, is sequentially and cyclically stored in a plurality of frame memories 5 to 7, one frame at a time for each vertical scanning period, The image processor 14 includes an image bus 8 to 1 provided for each of the frame memories 5 to 7.
Image data for one frame is sequentially and cyclically input from each of the frame memories at every cycle via 0, and the processing result is obtained.
Since the data is output to the outside via the data bus 16 different from that of No. 10 to 10, the transfer of the image, the image processing, and the result output can be continuously and rapidly performed without waste in a pipeline type without increasing the hardware scale. Can be executed.

[Brief description of drawings]

FIG. 1 is a system configuration diagram as an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a diagram showing a typical system configuration example of a conventional image processing apparatus.

FIG. 4 is a diagram showing a system configuration example of a conventional image processing apparatus that performs high-speed processing.

[Explanation of symbols]

1 CCD camera 2 image input / output board 3 image processing processor board 4 control CPU board 5 frame memory 6 frame memory 7 frame memory 8 image bus A 9 image bus B 10 image bus C 11 image processing processor board internal bus input / output buffer 12 images Bus input / output buffer in processor board 13 Bus input / output buffer in image processor board 14 Image processor 15 Bus input / output buffer in image processor board 16 Data bus D 17 Control CPU 18 External output interface in control CPU board 19 Control CPU In-board bus interface 20 A / D converter 21 D / A converter 22 Switching device 23 Switching device 24 Switching device 30 Monitor TV 31 Image input / output board internal bus 32 Image input / output board internal Scan 33 image input and output board internal bus

Claims (3)

[Claims] 1. An image processing apparatus for inputting and processing image data to be processed from an ITV camera or the like, and outputting the processing result to the outside, wherein a plurality of frame memories and one vertical scan of the image data to be processed are provided. 1 for each cycle
A unit for sequentially and cyclically storing frames in the frame memory, an image bus provided for each frame memory, and the frame memories for each cycle sequentially and cyclically from each of the frame memories. And an image processing unit that receives one frame of image data via the image bus corresponding to the above and performs the above processing. 2. The image processing apparatus according to claim 1,
An image processing apparatus, wherein the image processing means outputs the processing result to the outside via a bus different from the image bus. 3. The image processing apparatus according to claim 1, wherein the image data for one frame stored in the frame memory is cyclically taken out from each of the frame memories in each cycle. Means for displaying on a monitor, and image data for each frame processed through the image processing means is cyclically and cyclically transferred to the frame memory via the image bus for each cycle and is displayed on the monitor display means. An image processing apparatus comprising: means for displaying.