JP5151177B2 - Pixel number converter - Google Patents

Description

  The present invention relates to a pixel number conversion device, and more particularly to a pixel number conversion device that converts and outputs the number of pixels of an input image signal by a configuration in which two pixel number conversion processing circuits are connected in cascade.

  In recording and playback devices, when recording high-definition image signals such as high-definition signals converted to standard-resolution image signals and recording, and the resolution of the reproduced image signal is converted and output as another resolution image signal, etc. When performing pixel number conversion processing (scaling processing) at the time of reproduction, conventionally, a dedicated pixel number conversion device (scaling circuit or scaler) is provided at the time of recording and reproduction, and the pixel number conversion processing is independently performed. Or a method of realizing a pixel number conversion process by sharing a single pixel number conversion device (scaling circuit or scaler) during recording and reproduction.

  Here, in the pixel number conversion, for example, zero interpolation is performed on the image data before conversion so that the sampling frequency of the input image data before conversion becomes a desired sampling frequency after conversion, and after the zero interpolation Using the low-pass filter, the image data after conversion of the desired number of pixels is obtained. Therefore, the characteristics of the above-described low-pass filter are determined by the sampling frequency (number of pixels) before and after the conversion. When the conversion ratio corresponds to a plurality of conversion ratios, a low-pass filter having a plurality of characteristics is necessary, and the circuit scale is large. A large scale and complicated control adapted to the number of pixels before and after conversion are necessary.

  Therefore, in order to solve the above problem, an average value of the arbitrary natural number of input image data in the horizontal direction and the vertical direction is calculated, the average value image data is interpolated in the horizontal direction and the vertical direction, and the interpolation is performed. A pixel number conversion device that reduces the circuit scale by using a filter having characteristics that utilize the fact that the sensitivity of the human eye differs between the luminance signal and the color difference signal for processing has been conventionally proposed (for example, Patent Document 1).

JP 2001-13947 A

  However, when a dedicated pixel number conversion device is provided for recording and reproduction, two pixel number conversion devices are required, and a dedicated memory is required for each, which increases the circuit scale. There are challenges.

  In addition, when one pixel number conversion device is used for both recording and reproduction, it is necessary to read image data from the memory and write the converted image data back to the memory after converting the number of pixels. There is a problem that the frequency increases.

  Further, in the conventional pixel number conversion device described in Patent Document 1, although the circuit scale of the pixel number conversion device itself can be reduced, a pixel number conversion device is required for both recording and reproduction, so the effect of reducing the circuit scale is Not so big.

  Therefore, the present inventor, in Japanese Patent Application No. 2005-240612, suppresses the increase in the circuit scale and the number of memories by eliminating the need for storage means such as dedicated memories for input and output. Therefore, a pixel number conversion device capable of performing various pixel number conversions by reducing the frequency of access to the memory has been proposed.

  However, this pixel number conversion device has a configuration in which two pixel number conversion units are connected in cascade to convert the number of pixels of an image signal input in synchronization with an output image signal and output the pixel number conversion unit. When outputting later image data to the outside, each image data read in advance from the memory is stored in a buffer so that the image data can be output immediately in response to a request from the output timing controller. Although it is necessary to supply a synchronization signal with a shifted timing to the pixel number conversion unit, the amount by which the timing of the synchronization signal is shifted must be changed depending on the image format such as the number of scanning lines and the number of pixels of the image data before and after conversion. There is a problem that control is complicated.

  The present invention has been made in view of the above points, and even with a configuration in which two pixel number conversion units are connected in cascade, image data is directly read out from a memory and output even when operated in synchronization with an output signal. It is an object of the present invention to provide a pixel number conversion device capable of performing the same number of pixel conversions.

In order to achieve the above object, the present invention provides a horizontal line of a first image signal that is an input image signal input from the outside, or a second image signal that is an image signal read from storage means in the apparatus. Two pixel number conversion units, a vertical pixel number conversion unit that converts the number of pixels in the vertical direction corresponding to the number, and a horizontal pixel number conversion unit that converts the number of pixels in the horizontal direction of the first or second image signal. A pixel number conversion device that is connected in cascade and outputs an image signal in which the number of pixels in the vertical direction and the number of pixels in the horizontal direction are converted by the two pixel number conversion units to the outside through the image output unit,
Each of the two pixel number conversion units performs an operation synchronized with the input side, which performs pixel number conversion on the first image signal input in synchronization with the synchronization signal input from the outside and then stores it in the storage means A first operation mode, which is a mode, and an output side that outputs the image to the image output unit after converting the number of pixels of the second image signal read from the storage means in synchronization with the synchronization signal from the image output unit The number of pixels is converted for the second operation mode which is a synchronized operation mode and the second image signal read from the storage means in synchronization with the synchronization signal input from the outside or the synchronization signal input from the image output unit. When operating in the second operation mode, the operation is performed in any one operation mode selected from the third operation mode, which is an operation mode independently operated and stored in the storage means. Are each external Start the pixel number conversion operation based on the available signal indicating that it can be read, and then terminate the pixel number conversion operation and generate an output enable signal when the converted image signal can be output. When two cascaded pixel number conversion units operate in the second operation mode, the two connected pixel number conversion units are connected to the preceding stage. The pixel number conversion unit starts the pixel number conversion operation based on the usable signal supplied from the storage unit, and then outputs the converted image signal when the pixel number conversion operation is completed and the converted image signal can be output. It is characterized by having a means which supplies a possible signal as a usable signal to the other pixel number conversion part connected to the back | latter stage.

According to the present invention, the rear stage side other operation start timing of the pixel number conversion section can the same as the operation start timing of one number of pixel conversion section of the preceding stage, the timing to each pixel number converter and storage means Even if complicated control such as supplying a shifted synchronization signal is not performed, the other pixel number conversion unit on the rear stage side is always an image signal in which one pixel number conversion unit on the front stage side has finished the first pixel number conversion. The second pixel number conversion can be performed by taking in the image signal after the first pixel number conversion after the output state is enabled, depending on the processing order and processing time of the two pixel number conversion units It is possible to construct a flexible system that does not.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an embodiment of a pixel number conversion apparatus according to the present invention. When this embodiment is applied to a video camera, an image signal obtained by photoelectric conversion with a solid-state imaging device such as a CCD (Charge Coupled Devise) or a CMOS sensor (this is a still image signal or a moving image signal). Both are possible) are input to the image input unit 1 of FIG. When the present embodiment is applied to a broadcast recording device similar to a VTR, an image signal selected and received by a television tuner is input to the image input unit 1 in FIG. The image input unit 1 generates a signal indicating the valid period of the input image signal, an odd / even field discrimination signal (field index), a vertical synchronization signal, and a horizontal synchronization signal.

  In FIG. 1, an image signal (usually a moving image signal) extracted from the image input unit 1 is supplied to a vertical pixel number conversion unit (V scaler) 3 via a signal selection unit 2 to be used as a pixel in the vertical direction. After the number (the number of scanning lines) is converted, it is supplied to the horizontal pixel number conversion unit (H scaler) 4 via the signal selection unit 2, where the number of pixels in the horizontal direction is converted.

  As a result, an image signal in which the number of pixels has been converted in both the vertical direction and the horizontal direction is extracted from the horizontal pixel number conversion unit 4, and an output buffer (hereinafter referred to as “Osram”) to the memory 8 via the signal selection unit 2. The data is once stored in 6 and then supplied to and written in a large capacity memory 8 such as a dynamic random access memory (DRAM) at a predetermined timing. When recording, the image signal after the pixel number conversion written in the memory 8 is supplied to the recording / reproducing apparatus 9 and recorded on the recording medium.

  Unlike the above case, the image signal extracted from the image input unit 1 is temporarily stored in the Osram 6 via the signal selection unit 2, and then directly written in the memory 8 at a predetermined timing, and further recorded. In the case of performing the above, the image signal written in the memory 8 and not subjected to pixel number conversion may be supplied to the recording / reproducing apparatus 9 and recorded on the recording medium.

  An image signal reproduced from the recording / reproducing apparatus 9 or the like and written to the memory 8 or an image signal written to the memory 8 is read from the memory 8 and input to the memory 8 (hereinafter referred to as “Isram”). 7 is temporarily stored and then read out at a predetermined timing and supplied to the vertical pixel number conversion unit 3 via the signal selection unit 2 to convert the number of pixels in the vertical direction. Then, the data is supplied to the horizontal pixel number conversion unit 4 where the number of pixels in the horizontal direction is converted. As a result, an image signal with the number of pixels converted in both the vertical direction and the horizontal direction is extracted from the horizontal pixel number conversion unit 4 and output from the image output unit 5 via the signal selection unit 2 again.

  Further, unlike the above case, the image signal reproduced from the recording / reproducing apparatus 9 or the like and written to the memory 8 or the image signal written to the memory 8 is read from the memory 8 and is subjected to Islam 7 and signal selection. Through the unit 2, neither the vertical pixel number conversion unit 3 nor the horizontal pixel number conversion unit 4 may pass through and may be output from the image output unit 5. The image signal output from the image output unit 5 is output and displayed on a television monitor (not shown) or the like.

  The image output unit 5 generates a synchronization signal for connecting to a television monitor or the like and a timing signal for reading the image signal from the Isram 7. The recording / reproducing apparatus 9 is an apparatus for recording and reproducing an image signal on a recording medium such as a tape, a disk, or a semiconductor memory, but may include an image compression circuit such as MPEG (Moving Picture Experts Group). . Osram 6 and Isram 7 are usually buffer memories that are required for a large-capacity memory 8 that operates with a clock that is asynchronous with an input signal or an output signal, and that other blocks not shown in FIG. The input image signal (image data) is temporarily stored until a predetermined timing at which the user can access is reached.

  Next, the configuration and operation of each part constituting the pixel number conversion apparatus of the present invention will be described in more detail. FIG. 2 shows a circuit system diagram of an embodiment of the vertical pixel number conversion unit 3 of FIG. 1 which forms a main part of the pixel number conversion device of the present invention. In FIG. 2, the vertical pixel number conversion unit 3 includes a plurality (five in FIG. 2) of line memories 30, a selector 31 for selecting an output signal of the line memory 30, an interpolation filter 32, and a central processing unit (CPU). 33, a write / read control circuit 34, a write controller 35, a read controller 36, and a coefficient RAM 37.

  The coefficient RAM 37 is composed of four random access memories (RAMs) provided in a one-to-one correspondence with the four multipliers provided in the interpolation filter 32, and is provided in the interpolation filter 32. The multiplication coefficient is switched and output to the corresponding multiplier. In addition, the interpolation filter 32 includes, for example, four multipliers and an adder that adds the multiplication results of the multipliers. The four lines of image data supplied from the selector 31 and the coefficient RAM 37 The supplied multiplication coefficients are separately multiplied by four multipliers, and the obtained four multiplication results are added, whereby the image data output from the selector 31 is subjected to predetermined interpolation processing and output. .

  The CPU 33 sets the value of the ratio between the number of effective scanning lines of the input image signal before conversion and the number of effective scanning lines of the image signal after conversion to the write / read control circuit 34 that is reset to 0 by the vertical synchronization signal Vsync. In addition to the setting, coefficients (write address and write data) to be multiplied by each line are written in advance in the four RAMs constituting the coefficient RAM 37.

  The vertical pixel number conversion unit 3 having the above configuration has three modes: (i) a mode that operates in synchronization with the input side, (ii) a mode that operates in synchronization with the output side, and (iii) a mode that operates independently. Operate in mode. Hereinafter, operations in these modes will be described in order.

(I) Mode that operates in synchronization with the input side FIG. 3 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. As shown in FIG. 3, the mode operating in synchronization with the input side is a case where the number of vertical scanning lines of the image signal input from the image input unit 1 is converted and written to the memory 8 (mainly input). This is used when the number of scanning lines of the image signal is converted and recorded.

  This operation mode will be described with reference to the circuit diagram of FIG. 2, the block diagram of FIG. 3, and the timing chart of FIG. In FIG. 3, the image signal schematically shown in FIG. 4A is input from the image input unit 1 to the vertical pixel number conversion unit 3 via the signal selection unit 2. Then, the write / read control circuit 34 in FIG. 2 resets the internal V counter to 0 by the vertical synchronization signal Vsync schematically shown in FIG. 4B included in the input image signal or input separately. Subsequently, the writing / reading control circuit 34 changes the above-mentioned V counter every time the horizontal synchronizing signal Hsync schematically shown in FIG. Count up as shown schematically in D).

  Subsequently, when the value of the V counter reaches a predetermined value n, the writing / reading control circuit 34 waits for the value of the H counter (not shown) to become a predetermined value, and as shown in FIG. An enable signal Idata enable is generated and supplied to the write controller 35 in the vertical pixel number converter 3 in FIG. The vertical pixel number conversion unit 3 is reset in advance by the vertical synchronization signal Vsync, and in accordance with the data enable signal Idata enable, the writing of the first line memory lmem0 among the line memories 30 having five write controllers 35 is performed. After the enable we is activated and the input image signal is written to lmem0 by a predetermined number of pixels, the write enable we of lmem0 is disabled.

  Next, the write controller 35 waits for the data enable signal Idata enable to be input from the image input unit 1 and activates the write enable we of the second line memory lmem1 among the five line memories 30. After writing a predetermined number of pixels of the input image signal in lmem1, the write enable we of lmem1 is disabled. Thereafter, the write controller 35 repeats the above operation every time the data enable signal Idata enable is input from the image input unit 1, and cyclically predetermined as lmem2, lmem3, lmem4, lmem0, lmem1, lmem2,. Write the number of pixels. FIG. 4F schematically shows the write enable we for each line memory.

  In this way, writing for one line to the line memory 30 (line memories lmem0 to 3) is completed, and the data is input from the image input unit 1 to the read controller 36 of the vertical pixel number conversion unit 3. 2 waits for the data enable signal Odata enable to become active, the read controller 36 shown in FIG. 2 reads the image data of each line written in the line memories lmem0 to 3 of the line memory 30 from the line memories lmem0 to 3. The data is read and supplied to the interpolation filter 32 through the selector 31. The conversion of the number of vertical pixels is performed by adjusting the line number selected and output by the selector 31 and setting the ratio between the writing speed and the reading speed with respect to the line memory 30.

  The interpolation filter 32 separately multiplies the image data for four lines from the line memories lmem0 to 3 supplied from the selector 31 and the multiplication coefficient supplied from the coefficient RAM 37 set by the CPU 33 with four multipliers, By adding the obtained four multiplication results, a predetermined interpolation process is performed on the image data output from the selector 31, and the result is output as an image signal of a newly generated line. The image signal generated with the conversion of the number of vertical pixels in this way is output from the vertical pixel number conversion unit 3 and sequentially written in the memory 8 via the Osram 6, as shown in FIG.

(ii) Mode Operated in Synchronism with Output Side FIG. 5 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. As shown in FIG. 5, in the mode that operates in synchronization with the output side, the image signal read from the memory 8 is supplied to the vertical pixel number conversion unit 3 via the Isram 7 and the signal selection unit 2, and the number of vertical pixels This mode is used when the conversion unit 3 converts the number of vertical pixels of the input image signal and outputs it to a monitor display or the like.

  This operation mode will be described with reference to the circuit diagram of FIG. 2, the block diagram of FIG. 5, and the timing chart of FIG. In FIG. 5, first, the vertical pixel number conversion unit 3 can read image data from the memory 8 when the vertical synchronization signal Vsync is input from the image output unit 5 as schematically shown in FIG. (Wait for the Islam enable signal supplied from the Isram 7 controller not shown to the write controller 35 in FIG. 2 to be enabled as schematically shown at a high level in FIG. 6F.) .

  Subsequently, when the Isram enable signal is enabled, the write controller 35 shown in FIG. 2 of the vertical pixel number conversion unit 3 outputs an Isram control signal, which is read from the memory 8 of FIG. 5 and stored in the Isram 7. The existing image data is read from Isram7. At the same time, the write controller 35 activates the write enable lmem we of the first line memory lmem0 in the line memory 30 of FIG. 2 and writes the image data from the Isram 7 to the lmem0 by a predetermined number of pixels. . Thereafter, the write enable lmem we of lmem0 is disabled.

  Next, the write controller 35 waits for the Isram enable signal from the image output unit 5 to be enabled, and activates the write enable lmemwe of the second line memory lmem1 out of the five line memories 30, After a predetermined number of pixels are written in the input image signal in lmem1, the write enable lmem we of lmem1 is disabled. Thereafter, the writing controller 35 repeats the above operation every time an enabled Islam enable signal is input from the image output unit 5, and cyclically such as lmem2, lmem3, lmem4, lmem0, lmem1, lmem2,. Write a predetermined number of pixels. FIG. 6G schematically shows the write enable lmem we to each line memory.

  In this way, writing for one line is completed for each of the line memories lmem0 to 3 of the five line memories 30, and the image output unit 5 sends to the read controller 36 of the vertical pixel number conversion unit 3. Wait for the input data enable signal Odata enable to become active. Here, the write / read control circuit 34 in FIG. 2 resets the internal V counter to 0 by the vertical synchronization signal Vsync schematically shown in FIG. Each time the horizontal synchronizing signal Hsync schematically shown in C) is inputted, the V counter is counted up as schematically shown in FIG. 6D, and the value of the V counter is set to a predetermined value n. Then, after waiting for the value of the H counter (not shown) to become a predetermined value, as shown in FIG. 6 (E), the data enable signal Odata enable is generated and the readout in the vertical pixel number conversion unit 3 in FIG. It supplies to the controller 36.

  When the data enable signal Odata enable becomes active, the read controller 36 shown in FIG. 2 reads the image data of each line written in the line memories lmem0 to 3 of the line memory 30 from the line memories lmem0 to 3 and selects them. The signal is supplied to the interpolation filter 32 through 31. The conversion of the number of vertical pixels is performed by adjusting the line number selected and output by the selector 31 and setting the ratio between the writing speed and the reading speed with respect to the line memory 30.

  The interpolation filter 32 separately multiplies the image data for four lines from the line memories lmem0 to 3 supplied from the selector 31 and the multiplication coefficient supplied from the coefficient RAM 37 set by the CPU 33 with four multipliers, By adding the obtained four multiplication results, a predetermined interpolation process is performed on the image data output from the selector 31, and the result is output as an image signal of a newly generated line.

  Further, the line memory lmem storing the image signal of the line that is no longer used performs the above-described write operation to write the image signal of the next line. The line image signal generated with the conversion of the number of vertical pixels in this way is output from the vertical pixel number conversion unit 3 as shown in FIG. 5, and as schematically shown in FIG. The images are sequentially output to the outside via the image output unit 5.

(Iii) Mode of operation alone FIG. 7 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. In this independent operation mode, as shown in FIG. 7, the vertical pixel number conversion unit 3 reads the number of vertical pixels (scanning line) of the image signal read from the large-capacity memory 8 via the Isram 7 and the signal selection unit 2. This is used when the number is converted and then written back to the memory 8 via the signal selector 2 and Osram 6.

  This operation mode will be described with reference to the circuit diagram of FIG. 2, the block diagram of FIG. 7, and the timing chart of FIG. When the vertical synchronization signal Vsync shown in FIG. 8A or the CPU scaling start command is input from the image input unit 1 or the image output unit 5 in FIG. 7 to the vertical pixel number conversion unit 3, It waits for an Isram available signal indicating whether reading is possible to be enabled (readable) as shown at a high level in FIG. 8B.

  When the Isram enable signal is enabled, the write controller 35 in the vertical pixel number conversion unit 3 in FIG. 2 outputs an Isram control signal, which is read from the memory 8 in FIG. 7 and stored in the Isram 7. Is read from Isram7. At the same time, the write controller 35 activates the write enable we of the first line memory lmem0 in the line memory 30 of FIG. 2 and writes the image data from the Islam 7 to the lmem0 by a predetermined number of pixels. Thereafter, the write enable we of lmem0 is disabled.

  When the image data from Islam7 is written to lmem0 by a predetermined number of pixels, the write enable we of lmem1, lmem2, and lmem3 is sequentially activated, and the image data from Islam7 is sequentially input to lmem1, lmem2, and lmem3 by a predetermined number of pixels. Let it be written. Thereafter, when the image data has been written in each of the line memories lmem0 to 3 and the Osram enable signal is enabled as schematically shown at a high level in FIG. 8C, the read controller 36 in FIG. Reads out the image data from each of the line memories lmem 0 to 3 and supplies it to the interpolation filter 32 through the selector 31. The conversion of the number of vertical pixels is performed by adjusting the line number selected and output by the selector 31 and setting the ratio between the writing speed and the reading speed with respect to the line memory 30.

  Similar to the above-described modes, the interpolation filter 32 adds the four multiplication results obtained by multiplying the input image data by the coefficient set by the CPU 33 to generate image data of a new line, and outputs it to the Osram 6. To do. The Osram 6 writes input image data when the write enable we shown in FIG. 8E becomes active as schematically shown at a high level. Further, the line memory lmemo storing the image data of the line that is no longer used performs the above writing operation again to write the image data of the next line.

  The line image signal generated with the conversion of the number of vertical pixels in this way is output from the vertical pixel number conversion unit 3 and written in the memory 8 as shown in FIG.

  Next, the configuration and operation of the horizontal pixel number conversion unit 4 will be described. FIG. 9 shows a circuit system diagram of an embodiment of the horizontal pixel number conversion unit 4 of FIG. 1 which forms another main part of the pixel number conversion apparatus of the present invention. In FIG. 9, the horizontal pixel number conversion unit 4 includes a plurality (eight in FIG. 2) of D-type flip-flops (DFF0 to DFF7) 40, a selector 41 that selects an output signal of the DFF 40, an interpolation filter 42, a center The processing unit (CPU) 43, a write / read control circuit 44, a write controller 45, a read controller 46, and a coefficient RAM 47 are included.

  The DFF 40 has a configuration in which eight DFF0 to DFF7 (that is, DFFs for eight pixels) are provided in parallel, and output image data of five DFFs among them is selected by a selector 41 as described later. When the horizontal pixel number conversion is performed, new pixel data is normally generated from the original data for several pixels. Therefore, before the horizontal pixel number conversion is performed before the data is written in the large-capacity memory 8, the DFF 40 used for the calculation is used. I need it. Here, as described above, the calculation is performed using the DFF for 8 pixels and using 5 pixels among them.

  The coefficient RAM 47 is composed of five random access memories (RAM) provided in a one-to-one correspondence with the five multipliers provided in the interpolation filter 42, and is output from the read controller 46. Based on the read address, the multiplication coefficient is switched and output to a corresponding multiplier provided in the interpolation filter 42. The interpolation filter 42 includes an adder that separately multiplies the image data for five pixels supplied from the selector 41 and the multiplication coefficient supplied from the coefficient RAM 47 and adds the obtained five multiplication results. Has been.

  The horizontal pixel number conversion unit 4 having the above configuration includes three modes: (iv) a mode operating in synchronization with the input side, (v) a mode operating in synchronization with the output side, and (vi) a mode operating independently. Operate in mode. Hereinafter, operations in these modes will be described in order.

(iv) Mode that operates in synchronization with the input side FIG. 10 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. As shown in FIG. 10, the mode operating in synchronization with the input side is obtained by converting the horizontal pixel number of the image signal input from the image input unit 1 by the horizontal pixel number conversion unit 4 and then switching the signal selection unit 2 and the Osram 6. This is used when writing to the memory 8 via the network (mainly when the number of horizontal pixels of the input image signal is converted and recorded).

  This operation mode will be described with reference to the circuit diagram of FIG. 9, the block diagram of FIG. 10, and the timing chart of FIG. In FIG. 10, the image signal schematically shown in FIG. 11A is input from the image input unit 1 to the horizontal pixel number conversion unit 4 via the signal selection unit 2. The horizontal pixel number conversion unit 4 includes a V counter (not shown) inside the writing / reading control circuit 44 based on a vertical synchronization signal Vsync schematically shown in FIG. Is reset to 0. Subsequently, the write / read control circuit 44 sets the V counter to the value shown in FIG. 11 () each time the horizontal synchronization signal Hsync schematically shown in FIG. 11 (C) included in the input image signal or inputted separately is input. Count up as shown schematically in D).

  Subsequently, when the value of the V counter reaches a predetermined value n, the write / read control circuit 44 waits for the value of the H counter (not shown) to reach a predetermined value, and displays a data enable (Idata enable) signal. 11 (E). The horizontal pixel number conversion unit 4 is reset in advance by the vertical synchronization signal Vsync, and the write controller 45 receives the write enable signal den of DFF0 to DFF7 in accordance with a data enable (Idata enable) signal input from the controller of Islam 7 (not shown). It is generated as schematically shown in FIG. 11 (F), and each pixel data of the image signal shown in FIG. 11 (A) inputted from the image input unit 1 is written in order of DFF0 to DFF7 one by one. .

  The horizontal pixel number conversion unit 4 finishes writing pixel data to DFF0 to DFF4 in FIG. 2 and is input to the read controller 46 of the horizontal pixel number conversion unit 4 to enable data from an Osram 6 controller (not shown). Waiting for the signal Odata enable to become active, the read controller 36 shown in FIG. 2 supplies pixel data read from five DFFs of the eight DFF0 to DFF7 to the interpolation filter 42 through the selector 41. . The number of horizontal pixels is converted by adjusting the pixel number read by the selector 41 and adjusting the ratio between the writing speed and the reading speed of the pixel to the DFF 40.

  The interpolation filter 42 separately multiplies the pixel data for five pixels supplied from the selector 41 and the multiplication coefficient supplied from the coefficient RAM 47 set by the CPU 43 with five multipliers, and obtains the five multiplication results obtained. Is added to the pixel data output from the selector 41 to perform a predetermined interpolation process and output as an image signal of a newly generated pixel. The image signal generated with the conversion of the number of horizontal pixels in this way is output from the horizontal pixel number conversion unit 4 and sequentially written in the memory 8 via the Osram 6, as shown in FIG.

(v) Mode Operated in Synchronism with Output Side FIG. 12 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. In the mode operating in synchronization with the output side, as shown in FIG. 12, the image signal read from the memory 8 is supplied to the horizontal pixel number conversion unit 4 via the Isram 7 and the signal selection unit 2, and the number of horizontal pixels This mode is used when the conversion unit 4 converts the number of horizontal pixels of the input image signal and outputs it from the image output unit 5 to a monitor display or the like.

  This operation mode will be described with reference to the circuit diagram of FIG. 9, the block diagram of FIG. 12, and the timing chart of FIG. In FIG. 12, first, the horizontal pixel number conversion unit 4 can read image data from the memory 8 when the vertical synchronization signal Vsync is input from the image output unit 5 as schematically shown in FIG. (Wait until the Isram enable signal supplied from the Isram 7 controller (not shown) to the write controller 45 in FIG. 9 is enabled as schematically shown at a high level in FIG. 13F.) .

  Subsequently, when the Isram enable signal is enabled, the write controller 45 shown in FIG. 9 of the horizontal pixel number conversion unit 4 outputs an Isram control signal, which is read from the memory 8 of FIG. 12 and stored in the Isram 7. The existing image data is read from Isram7. At the same time, the write controller 45 sequentially activates the write enable signals den of the eight DFF0 to DFF7 constituting the DFF 40 of FIG. 9 as shown in FIG. Write to DFF0 to DFF7.

  Next, after the writing of the pixel data to DFF0 to DFF4 is completed, the read controller 46 of FIG. 9 waits for the data enable signal Odata enable from the image output unit 5 to become active, and is written to DFF0 to DFF4. Each pixel data of the five pixels is read and supplied to the interpolation filter 42 through the selector 41. In the same manner as in the operation mode (iv), the interpolation filter 42 multiplies the input five pixel data by coefficients set by the CPU 43, and then adds the multiplication results to obtain a new value. Pixel data is generated and output. In addition, the write operation is performed to write the next pixel data in the DFF in which the pixel data that is no longer used is stored. The image data output from the interpolation filter 42 is output to the outside via the signal selection unit 2 and the image output unit 5 of FIG.

(Vi) Mode of operation alone FIG. 14 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. In this independent operation mode, as shown in FIG. 14, the horizontal pixel number conversion unit 4 converts the horizontal pixel number of the image signal read from the large capacity memory 8 via the Isram 7 and the signal selection unit 2. This is used when writing to the memory 8 again via the signal selector 2 and Osram 6.

  This independent operation mode will be described with reference to the circuit diagram of FIG. 9, the block diagram of FIG. 14, and the timing chart of FIG. When the horizontal synchronization signal Vsync shown in FIG. 15A or the CPU scaling start command is input from the image input unit 1 or the image output unit 5 in FIG. It waits until an Isram enable signal generated by an Isram controller (not shown) indicating whether reading is possible is enabled as schematically shown at a high level in FIG.

  When the Isram enable signal is enabled, the write controller 45 in the horizontal pixel number conversion unit 4 in FIG. 9 outputs an Isram control signal, which is read from the memory 8 in FIG. 14 and stored in the Isram 7. Is read from Isram7. At the same time, the write controller 45 sequentially activates the write enable signals den of the eight DFF0 to DFF7 constituting the DFF 40 of FIG. 9 as schematically shown in FIG. Pixel data is written in DFF0 to DFF7.

  Next, after completing the writing of the pixel data to DFF0 to DFF4, the readout controller 46 in FIG. 9 schematically shows the Osram available signal generated by the Osram controller (not shown) at a high level in FIG. If it is enabled, the pixel data of the five pixels written in DFF0 to DFF4 are read by activating the read enable Osram we shown in FIG. Supply. The number of horizontal pixels is converted by adjusting the pixel number selected by the selector 41 and adjusting the ratio between the pixel writing speed and the reading speed of the DFF 40.

  In the same manner as in the operation mode (iv), the interpolation filter 42 multiplies the input five pixel data by coefficients set by the CPU 43, and then adds the multiplication results to obtain a new value. Pixel data is generated and output. In addition, the write operation is performed to write the next pixel data in the DFF in which the pixel data that is no longer used is stored. The image data after the horizontal pixel number conversion output from the interpolation filter 42 in the horizontal pixel number conversion unit 4 is temporarily stored in the Osram 6 via the signal selection unit 2 in FIG. 14 and then output at a predetermined timing. Are written in the memory 8.

  Next, when the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 that operate in any of the above three operation modes are connected in cascade, and each is operated in a mode that operates in synchronization with the output side. Will be described. FIG. 16 is a block diagram of an embodiment of the pixel number conversion apparatus of the present invention showing a signal path in this mode. In the figure, the same components as those in FIG. The mode that operates in synchronism with the output side is, for example, that an image signal recorded at a standard resolution (SD) by the recording / reproducing apparatus 9 is received by the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4, respectively. This is used when converting the number of pixels into a high definition (HD) image signal and outputting it to the outside.

  In a mode that operates in synchronization with the output side (output synchronization mode), it is necessary to output image data that has undergone pixel number conversion in accordance with the synchronization signal generated by the image output unit 5 of FIG. Therefore, necessary image data must be prepared in the vertical pixel number converting unit 3 and the horizontal pixel number converting unit 4 at the time when the image output unit 5 first generates a read signal.

  In addition, as shown in FIG. 16, when the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 are connected in cascade, the vertical pixel number conversion unit 3 is operated first, and the horizontal pixel number conversion unit 4 It is necessary to prepare in advance so that the image data can be immediately output from the vertical pixel number conversion unit 3 in accordance with the request from. Also, the horizontal pixel number conversion unit 4 needs to be prepared in advance so that image data can be output before an output request from the image output unit 5 is input. That is, start of operation → vertical pixel number conversion unit 3 starts operation in output synchronous mode → vertical pixel number conversion unit 3 outputs ready → horizontal pixel number conversion unit 4 starts operation in output synchronous mode → horizontal pixel number conversion unit 4 output It is necessary to control the timing so that the order of preparation completion → output of the image output unit 5 starts.

  Therefore, normally, the operation is performed as follows by a method of making a difference in the start timing of each block. The operation in this case will be described with reference to the timing chart of FIG. 17. First, in the vertical pixel number conversion unit 3 of FIG. 16, the vertical synchronization signal Vsync is schematically shown in FIG. As shown in FIG. 17 (F), an Islam enable signal generated by an Isram controller (not shown) is schematically shown at a high level. When enabled, the write controller 35 shown in FIG. 2 of the vertical pixel number conversion unit 3 outputs an Isram control signal, reads the image data read from the memory 8 of FIG. 16 and accumulated in the Isram 7 from the Isram 7, Write enable lmem w for sequentially writing the five line memories constituting the line memory 30 of FIG. e is activated as schematically shown at a high level in FIG. 17G, and a predetermined number of pixels are written.

  Thereafter, when the image data has been written in each of the line memories 30 in the vertical pixel number conversion unit 3, the vertical pixel number conversion unit 3 waits for the input of the enable signal Odata enable from the horizontal pixel number conversion unit 4. Note that the vertical pixel number conversion unit 3 in FIG. 16 changes the above-described V counter every time the horizontal synchronization signal Hsync schematically shown in FIG. 17C input from the pixel output unit 5 is input. ) Is counted up as shown schematically.

  On the other hand, when a signal obtained by delaying the vertical synchronization signal Vsync shown in FIG. 17H is supplied from the pixel output unit 5 to the horizontal pixel number conversion unit 4 as an operation start command signal, the horizontal pixel number conversion unit 4 outputs the signal. The operation is started in the synchronous mode, and the Isram enable signal is enabled as schematically shown at a high level in FIG. 17 (I), and the vertical pixel number conversion unit 3 is enabled as shown in FIG. 17 (E). In addition to supplying the signal Odata enable, the write enable signals den of the eight DFF0 to DFF7 constituting the DFF 40 in the horizontal pixel number converter 4 in FIG. 9 are sequentially activated as shown in FIG. The pixel data read from the pixel number conversion unit 3 is written in DFF0 to DFF7. When writing to DFF0 to DFF4 is completed, the horizontal pixel number conversion unit 4 waits for the enable signal Odata enable input from the image output unit 5 to become active.

  Thereafter, when the enable signal Odata enable input from the image output unit 5 becomes active, the horizontal pixel number conversion unit 4 in FIG. 16 reads out pixel data from the internal DFF 40, and as described with reference to FIGS. An image signal is generated and output to the image output unit 5. FIG. 17A shows a new image signal output to the image output unit 5 at this time. Further, the pixel data is read from the vertical pixel number conversion unit 3 and written in the DFF in the horizontal pixel number conversion unit 4 in which pixel data that is no longer used is stored.

  In this method, in order for the horizontal pixel number conversion unit 4 in the subsequent stage to start operation, the vertical pixel number conversion unit 3 in the previous stage needs to be in a state in which a signal can be output. Since there is no way to know that the vertical pixel number conversion unit 3 is ready to output a signal, a signal obtained by delaying the vertical synchronization signal Vsync for starting the vertical pixel number conversion unit 3 by a predetermined time is generated. It is necessary to start the operation by supplying it to the horizontal pixel number converter 4. This predetermined delay time takes into consideration the transmission time of the signal from the memory 8 via the Isram 7 and the signal selection unit 2 to the vertical pixel number conversion unit 3, the image data storage time in the vertical pixel number conversion unit 3, and the like. Need to be set.

  Therefore, in the present embodiment, in order to solve the above-described problem, among the two pixel number conversion units connected in cascade, the preceding pixel number conversion unit (vertical pixel number conversion unit 3 in FIG. 16) can output a signal. Is supplied to the subsequent pixel number conversion unit (horizontal pixel number conversion unit 4 in FIG. 16) as an Isram usable signal indicating whether or not Isram 7 can be read. The two connected pixel number conversion units 3 and 4 have the same operation start timing. The operation of this embodiment will be described with reference to the block diagram of FIG. 16 and the timing chart of FIG.

  The vertical pixel number conversion unit 3 in FIG. 16 is an output enable signal indicating that the converted image can be output (a signal indicating a state in which image data is stored in an image signal storage line memory incorporated in the vertical pixel number conversion unit 3. The signal generated by the read controller 36 in FIG. 2 is output. Further, the horizontal pixel number conversion unit 4 in FIG. 16 also has a similar output enable signal (a signal indicating a state in which image data is stored in an image signal storage DFF built in the signal, which is read by the read controller 46 in FIG. Generated signal). In FIG. 16, since the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 are connected in this order, the preceding vertical pixel number conversion unit is used as an Isram usable signal supplied to the subsequent horizontal pixel number conversion unit 4. The output enable signal generated in step 3 is supplied.

  First, when the vertical synchronizing signal Vsync is input from the image output unit 5 as schematically shown in FIG. 18B, the vertical pixel number converting unit 3 in FIG. 16 operates in the output synchronous mode as a trigger. When the Isram enable signal generated by the Isram controller (not shown) is enabled as schematically shown at a high level in FIG. 18F, the write controller 35 shown in FIG. Outputs an Isram control signal, reads the image data read from the memory 8 in FIG. 16 and stored in the Isram 7 from the Isram 7, and sequentially writes the five line memories constituting the line memory 30 in FIG. The write enable lmem we is activated as shown schematically at a high level in FIG. A predetermined number of pixels are cyclically written as emo0, lmemo1, lmem2, lmem3, lmem4, lmem0, lmem1, lmem2,.

  After that, when the image data has been written in each of the line memories 30 in the vertical pixel number conversion unit 3, the vertical pixel number conversion unit 3 can immediately output the converted image, as shown in FIG. The output enable signal shown in FIG. 2 is generated by the read controller 36 in FIG. The signal selection unit 2 selects the output enable signal instead of the Isram use enable signal generated by the Isram controller, and supplies the selected signal to the horizontal pixel number conversion unit 4 as the Isram enable signal. Note that the vertical pixel number conversion unit 3 in FIG. 16 changes the above-described V counter every time the horizontal synchronization signal Hsync schematically shown in FIG. 18C input from the pixel output unit 5 is input. ) Is counted up as shown schematically.

  When the above-mentioned Isram usable signal (output enable signal) is supplied to the horizontal pixel number conversion unit 4 in FIG. 16, each writing of the eight DFF0 to DFF7 constituting the DFF 40 in the horizontal pixel number conversion unit 4 in FIG. 9 is performed. The enable signal den is sequentially activated as shown in FIG. 18J, and the pixel data read from the vertical pixel number conversion unit 3 is written into DFF0 to DFF7. When writing to DFF0 to DFF4 is completed, the horizontal pixel number conversion unit 4 waits for the enable signal Odata enable input from the image output unit 5 to become active.

  Thereafter, when the enable signal Odata enable input from the image output unit 5 becomes active, the horizontal pixel number conversion unit 4 in FIG. 16 reads out pixel data from the internal DFF 40, and as described with reference to FIGS. An image signal is generated and output to the image output unit 5. FIG. 18A shows a new image signal output to the image output unit 5 at this time. Further, the pixel data is read from the vertical pixel number conversion unit 3 and written in the DFF in the horizontal pixel number conversion unit 4 in which pixel data that is no longer used is stored.

  Thus, in the present embodiment, the subsequent horizontal pixel number conversion unit 4 reads and writes the image data from the previous vertical pixel number conversion unit 3 in exactly the same way as when image data is directly read from the Isram 7. Therefore, the operation start timing of the horizontal pixel number conversion unit 4 can be made the same as the operation start timing of the vertical pixel number conversion unit 3 (the horizontal pixel number conversion unit 4 is narrowly defined by the input of an Isram usable signal). The operation is started, but the Isram usable signal is an output enable signal obtained by the end of the image data writing operation of the vertical pixel number conversion unit 3, so the operation start timing of the horizontal pixel number conversion unit 4 is the vertical pixel number conversion. It can be said that it is the same as the operation start timing of the unit 3.) Accordingly, it is not necessary to generate a delayed operation start timing signal as in the normal method described with reference to FIG. 17, and the occurrence of malfunction can be prevented.

  In addition, the above description is a case where the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 that are cascade-connected in two stages are both operated in a mode that operates in synchronization with the output side (output synchronization mode). In this case, the desired effect of the present invention can be obtained. In addition to this, (1) a mode in which both the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 operate in synchronization with the input side ( Operation in the input synchronization mode), (2) operation in which the vertical pixel number conversion unit 3 operates alone, and the horizontal pixel number conversion unit 4 operates in input synchronization mode, and (3) vertical pixel number conversion unit 3 Can be set to the output synchronous mode, and the horizontal pixel number conversion unit 4 can be operated alone.

  In the above operation (1), the image signal input from the image input unit 1 is converted into the number of vertical pixels and the number of horizontal pixels by the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4, respectively. Is written to. In the above operations (2) and (3), the horizontal pixel number conversion is performed after the image data accumulated in the Isram 7 is read out by the vertical pixel number conversion unit 3 and converted in the vertical pixel number. The number of horizontal pixels is supplied to the unit 4 and converted and written to the Osram 6. In the operation of (2) or (3) above, one of the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 is a master, and the pixel number conversion unit in the mode of operating independently becomes the master. The other pixel number conversion unit operates based on an output enable signal indicating that the converted image can be output immediately or an input enable signal indicating that the image can be input immediately. Thus, the operation start timings of the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 can be made the same.

  The present invention is not limited to the above embodiment. For example, the connection order of the vertical pixel number conversion unit 3 and the horizontal pixel number conversion unit 4 that are cascade-connected in two stages is the same as that of the above embodiment. May be reversed. Moreover, the computer program which implement | achieves operation | movement of the vertical pixel number conversion part 3 and the horizontal pixel number conversion part 4 with a computer is also included. In this case, the program may be recorded on a recording medium and taken into a computer, may be delivered to a computer via a communication network, or may be taken in beforehand by dedicated hardware of the computer. Also good.

It is a block diagram which shows the whole structure of one Embodiment of the pixel number converter of this invention. FIG. 2 is a circuit diagram of an embodiment of the vertical pixel number conversion unit of FIG. 1 forming a main part of the pixel number conversion device of the present invention. It is a block diagram which shows the signal path | route at the time of the mode in which the vertical pixel number conversion part in the pixel number conversion apparatus of this invention operate | moves synchronizing with an input side. 5 is a timing chart for explaining operations in a mode in which a vertical pixel number conversion unit operates in synchronization with an input side. It is a block diagram which shows the signal path | route at the time of the mode in which the vertical pixel number conversion part in the pixel number conversion apparatus of this invention operate | moves synchronizing with an output side. 5 is a timing chart for explaining operations in a mode in which a vertical pixel number conversion unit operates in synchronization with an output side. It is a block diagram which shows the signal path | route at the time of the mode in which the vertical pixel number conversion part in the pixel number conversion apparatus of this invention operate | moves independently. It is a timing chart for operation | movement explanation at the time of the mode in which a vertical pixel number conversion part operate | moves in synchronization independently. FIG. 3 is a circuit diagram of an embodiment of the horizontal pixel number conversion unit of FIG. 1 that forms another main part of the pixel number conversion device of the present invention. It is a block diagram which shows the signal path | route at the time of the mode in which the horizontal pixel number conversion part in the pixel number conversion apparatus of this invention operate | moves synchronizing with an input side. It is a timing chart for operation | movement explanation at the time of the mode in which a horizontal pixel number conversion part operate | moves synchronizing with an input side. It is a block diagram which shows the signal path | route at the time of the mode in which the horizontal pixel number conversion part in the pixel number conversion apparatus of this invention operate | moves synchronizing with an output side. 5 is a timing chart for explaining operations in a mode in which a horizontal pixel number conversion unit operates in synchronization with the output side. It is a block diagram which shows the signal path | route at the time of the mode in which the horizontal pixel number conversion part in the pixel number conversion apparatus of this invention operate | moves independently. It is a timing chart for operation | movement explanation at the time of the mode in which a vertical pixel number conversion part operate | moves in synchronization independently. It is a block diagram showing a signal path in a mode in which a vertical pixel number conversion unit and a horizontal pixel number conversion unit in a pixel number conversion device of the present invention are connected in cascade and operate in synchronization with the output side. It is a timing chart explaining an example of the operation | movement in FIG. It is a timing chart explaining the operation | movement of one Embodiment of this invention in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image input part 2 Signal selection part 3 Vertical pixel number conversion part (V scaler)
4 Horizontal pixel number converter (H scaler)
5 Image output unit 6 Output buffer for memory (Osram)
7 Input buffer for memory (Isram)
8 Memory 9 Recording / reproducing device 30, 30, lmem0-lmem4 Line memory 31, 41 Selector 32, 42 Interpolation filter 33, 43 Central processing unit (CPU)
34, 44 Write / read control circuit 35, 45 Write controller 36, 46 Read controller 37, 47 Coefficient RAM
40, DFF0 to DFF7 D-type flip-flop (DFF)

Claims (1)

Vertical conversion that converts the number of pixels in the vertical direction corresponding to the number of horizontal lines of the first image signal that is an input image signal input from the outside or the second image signal that is an image signal read from the storage means in the apparatus. Two pixel number conversion units are connected in cascade, a pixel number conversion unit and a horizontal pixel number conversion unit that converts the number of pixels in the horizontal direction of the first or second image signal. A pixel number conversion device for outputting an image signal obtained by converting the number of pixels in the vertical direction and the number of pixels in the horizontal direction to the outside through the image output unit,
Each of the two pixel number conversion units performs pixel number conversion on the first image signal input in synchronization with the synchronization signal input from the outside, and then stores it in the storage unit. A first operation mode that is a synchronized operation mode and the image output after the pixel number conversion is performed on the second image signal read from the storage means in synchronization with the synchronization signal from the image output unit A second operation mode which is an operation mode synchronized with an output side to be output to the unit, and the second read out from the storage means in synchronization with a synchronization signal input from the outside or a synchronization signal input from the image output unit. The operation is performed in any one of the operation modes arbitrarily selected from the third operation mode, which is the operation mode independently operating after converting the number of pixels to the image signal of 2 Shi The supplied from each operation when the outside in the second mode of operation, to start the pixel number conversion operation on the basis of the usable signal indicating a readable, then exit the pixel number conversion converted image signal When it becomes possible to output, it has means to generate and output an output enable signal,
When both the two pixel number conversion units connected in cascade operate in the second operation mode, one of the two pixel number conversion units connected in cascade is connected to the preceding stage. The unit starts the pixel number conversion operation based on the usable signal supplied from the storage means, and then ends the pixel number conversion operation and can output the converted image signal when it can be output. A pixel number conversion apparatus comprising means for supplying a signal as the usable signal to the other pixel number conversion unit connected to the subsequent stage.

Images