JP2004110046A - Display device for performing video scaling - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display a video with the resolution converted into that of the display device irrespective of the resolution of the video. <P>SOLUTION: The resolution of a video signal is determined from the frequency by checking the frequency of a synchronous signal of the video signal. Then, the resolution of the video signal is converted so as to coincide with that of the display device by magnifying/contracting the video to be displayed by the video signal to display it on a display device. <P>COPYRIGHT: (C)2004,JPO

Description

<< The present invention relates to a display device for scaling and displaying an input video.

There is a case where an image created by a computer is desired to be displayed on another display device such as a liquid crystal projector. In such a case, it is necessary for the computer to create a video signal corresponding to the resolution of the display device. In this specification, “resolution” means the number of dots (pixels) in the horizontal direction and the number of lines (scanning lines) in the vertical direction of an image. The number of dots in the horizontal direction is called “horizontal resolution”, and the number of lines in the vertical direction is called “vertical resolution”.

解像度 The resolution and the number of gradations of images that can be generated by a computer are limited by the capacity of a video RAM (VRAM) in the computer. In other words, there is a relationship that the number of gradations decreases when displaying with a large resolution (that is, a large screen size), and the resolution decreases with increasing the number of gradations. Therefore, when the screen size of the display device is large, the resolution of the video signal generated by the computer may not be able to match the resolution of the display device. Such a problem is the same when displaying an image other than a computer (for example, an image on a television) on a display device other than the television.

The present invention has been made to solve the above-described problems in the conventional technology, and has as its object to convert an input video to a resolution of a display device and display the video, regardless of the resolution of the video.

In order to solve at least a part of the above-described problems, a first display device according to the present invention includes a light source, a light modulator, a resolution determining unit that determines a horizontal resolution and a vertical resolution of an input video signal, A scaling means for processing the video signal so that the horizontal resolution of the video signal matches the standard horizontal resolution of the light modulation unit, wherein the video based on the video signal processed by the scaling means Is displayed.

Since the resolution of the display device is known, the ratio of the horizontal resolution of the video signal to the horizontal resolution of the display device can be obtained by determining the horizontal resolution of the input video signal. Therefore, if the image is scaled up / down at this ratio, the image can be displayed with the horizontal resolution of the video signal matched with the horizontal resolution of the display device.

The scaling means may process the video signal such that a vertical resolution of the video signal matches a standard vertical resolution of the display device.

A second display device according to the present invention includes a light source, a light modulation unit, resolution determining means for determining a horizontal resolution and a vertical resolution of an input video signal, and a vertical resolution of the video signal is a standard of the light modulation unit. A scaling means for processing the video signal so as to match the vertical resolution, wherein the display device displays an image based on the video signal processed by the scaling means.

(4) With this display device, the vertical resolution of the video signal can be displayed in accordance with the vertical resolution of the display device.

The scaling means may process the video signal such that a horizontal resolution of the video signal matches a standard horizontal resolution of the display device.

The resolution determining unit detects a frequency of a horizontal synchronization signal and a frequency of a vertical synchronization signal of the video signal, and a frequency detection unit, based on at least the detected frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal, Means for determining the horizontal resolution and the vertical resolution of the video signal.

Further, the display device, a plurality of input units each capable of receiving an input video signal, a video signal selection unit that selects one input video signal from the input video signals received by the plurality of input units, And the selected one input video signal may be the video signal.

The display device is, for example, a projector.

As the video signal, a video signal generated by a computer, a video signal of a television, or the like can be applied.

Next, embodiments of the present invention will be described based on examples. FIG. 1 is a block diagram showing a configuration of a liquid crystal projector according to a first embodiment of the present invention. This liquid crystal projector is a device that projects an image generated by the personal computer 100 on a large-size screen (not shown), and includes a CPU 20, a main memory 22, an input panel 24 as input means, A D converter 32, a frame memory 34, a video scaler 36, an LCD driver 38, an LCD panel (liquid crystal display panel) 40, and a light source 42 are provided. Note that the frame memory 34 has three memory planes for storing RGB signals.

The CPU 20 has a function as a frequency determination unit 26 that determines the frequency of the synchronization signal SYNC given from the personal computer 100 and a function as a resolution determination unit 28 that determines the resolution corresponding to the frequency of the synchronization signal SYNC. These functions are realized by the CPU 20 executing a software program stored in the main memory 22.

The A / D converter 32 A / D converts the video signal VPC supplied from the personal computer 100 to generate a digital video signal DPC, and inputs the digital video signal DPC to the video scaler 36. A synchronization signal SYNC from the personal computer 100 is input to the video scaler 36 together with the digital video signal DPC. In this specification, “video signal” may mean a video signal in a narrow sense that does not include a synchronization signal, or may mean a video signal in a broad sense that includes a synchronization signal.

The video scaler 36 writes the input digital video signal DPC into the frame memory 34, reads the video signal from the frame memory 34, and supplies the read video signal to the LCD driver 38. At this time, the video scaler 36 adjusts the resolution of the video signal so as to match the standard resolution of the LCD panel 40 by enlarging / reducing the video. The LCD driver 38 displays an image provided from the video scaler 36 on the LCD panel 40. Then, the image displayed on the LCD panel 40 is projected on the screen by the light source 42.

FIG. 2 is an explanatory diagram showing functions of the video scaler 36. As shown on the left side of FIG. 2, images generated by a personal computer have various resolutions (640 dots × 400 lines, 640 dots × 480 lines, 800 dots × 600 lines, 1024 dots × 768 lines, 1600 dots × 1200 lines). On the other hand, the standard resolution of the LCD panel 40 is constant, and is 800 dots × 600 lines in the example of FIG. Therefore, the video scaler 36 generates a video signal having the standard resolution of the LCD panel 40 by enlarging or reducing the input video signal VPC. In this way, if the video signal VPC generated by the personal computer 100 is input to this liquid crystal projector, the video can be displayed on the entire screen of the LCD panel 40. That is, the resolution of the liquid crystal projector is independent of the resolution of the input video signal VPC. Therefore, it is possible to generate an image having a desired resolution and the number of gradations on the personal computer 100 side and display the image on the entire screen of the LCD panel 40.

FIG. 3 is a block diagram showing the internal configuration of the video scaler 36. The video scaler 36 includes a first color conversion unit 50, a write synchronization signal generation unit 52, an input FIFO buffer 54, a DRAM controller 56, an address controller 58, a CPU access controller 60, and an output Two FIFO buffers 61
, 62, a filter section 64, a second color conversion section 66, and a readout synchronization signal generation section 68. As shown in FIG. 3, in this embodiment, the frame memory 34 is constituted by a dynamic RAM. The DRAM controller 56 is a circuit that controls writing of the video signal to the frame memory 34 and reading of the video signal from the frame memory 34.

(1) The digital video signal DPC generated by the A / D converter 32 in FIG. 1 is provided to the first color conversion unit 50, and color conversion into RGB signals is performed as necessary. For example, when the input digital video signal DPC is a YCrCb signal, it is converted into an RGB signal by the color conversion unit 50.

The synchronization signal SYNC provided from the personal computer 100 includes the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1. The write synchronizing signal generator 52 generates the dot clock signal DCK1 by multiplying the frequency of the horizontal synchronizing signal HSYNC1 or the vertical synchronizing signal VSYNC1 by N0 by an internal PLL circuit (not shown). The dot clock signal DCK1 is a signal indicating the update timing of the dot position in the horizontal direction. The dot clock signal DCK1 is supplied to the address controller 58 together with the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1.

The video signal converted by the first color conversion unit 50 is temporarily stored in the FIFO buffer 54, and is written in the frame memory 34 by the DRAM controller 56. The FIFO buffer 54 is used for adjusting the write timing. The write operation to the frame memory 34 is performed in synchronization with the write synchronization signals {DCK1, HSYNC1, VSYNC1} provided from the write synchronization signal generation unit 52. That is, each dot position (horizontal address) is updated in synchronization with the dot clock signal DCK1, the scanning line position (vertical address) is updated in synchronization with the horizontal synchronization signal HSYNC1, and each frame (each field) is updated vertically. It is updated in synchronization with the synchronization signal VSYNC1. The DRAM controller 56 also controls the reading of the video signal stored in the frame memory 34 and the writing of the video signal to the FIFO buffers 61 and 62 alternately. The read operation from the frame memory 34 is performed in synchronization with the read synchronization signal {DCK2, HSYNC2, VSYNC2} generated by the read synchronization signal generation unit 68. The read synchronization signals {DCK2, HSYNC2, VSYNC2} are also provided to the LCD driver 38 and used as display synchronization signals on the LCD panel 40. The address controller 58 is a circuit that generates a write address and a read address and supplies the generated address and the read address to the DRAM controller 56, and includes a scaling unit 70 that enlarges or reduces an image.

One line of video signal read from the frame memory 34 is alternately written to the two FIFO buffers 61 and 62 for output. At this time, the video signal is read from the buffer in which writing has not been performed, and applied to the filter unit 64. The filter unit 64 is a circuit that performs gamma correction (input / output gradation conversion) and various filtering processes such as horizontal inversion and vertical inversion of an image. The video signal that has been subjected to the filtering process is subjected to color conversion as necessary in a color conversion section 66, and is converted into an output video signal DOUT. The output video signal DOUT is supplied to the LCD driver 38 (FIG. 1).

1 The CPU 20 in FIG. 1 can access each unit in the video scaler 36 via the CPU access controller 60 in FIG. When determining the frequency of the synchronization signal SYNC corresponding to the input video signal VPC, the CPU 20 receives a signal from the write synchronization signal generator 52 via the CPU access controller 60. First, the CPU 20 functions as the frequency determination unit 26 (FIG. 1), and measures the frequencies of the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1 input to the write synchronization signal generation unit 52, respectively. Next, it functions as the resolution determining unit 28, and determines the resolution of the input video signal VPC based on these frequencies.

FIG. 4 is a resolution determination table showing the relationship between resolution and frequency. In this resolution determination table, the relationship between various resolutions (the number of dots × the number of lines) and the frequencies of the horizontal synchronization signal and the vertical synchronization signal is registered. The resolution determination table is stored in the main memory 22. Since the frequency of the operation clock of the CPU 20 is several tens of MHz, the frequency of the horizontal synchronization signal is several tens of kHz, and the frequency of the vertical synchronization signal is several tens of Hz, the function of the frequency determination unit 26 is executed by software processing. Can be measured with sufficient accuracy. For example, if the CPU 20 counts up at a fixed cycle and calculates the count number between edges (for example, falling edges) of the horizontal synchronization signal HSYNC1, the frequency of the horizontal synchronization signal HSYNC1 can be calculated from the count number. it can. The same applies to the vertical synchronization signal VSYNC1. When the frequencies of the synchronization signals HSYNC1 and VSYNC1 are determined in this way, the resolution determination unit 28 determines the corresponding resolution by referring to the resolution determination table (FIG. 4).

By the way, as illustrated in FIG. 4, there are cases where there are several types of the frequency of the synchronization signal even with the same resolution. Therefore, it is preferable to register as many relations as possible between the resolution and the frequency used in many commercially available devices in the resolution determination table. However, there may be a case where a video signal of a frequency not registered in the resolution determination table is input. In this case, the CPU 20 displays on the LCD panel 40 (or the display unit of the input panel 24) that the frequency of the input video signal VPC has not been registered. Then, when the user sets the resolution (the number of dots × the number of lines) of the input video signal VPC using the input panel 24, the relationship between the frequency and the resolution is registered in the resolution determination table. In order to realize this processing, it is preferable to store the resolution determination table in a writable memory such as a RAM or a flash memory.

When determining the resolution of the input video signal VPC, the resolution may be determined not only based on the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal, but also based on their period widths HH and HV and the presence or absence of interlace. . FIG. 5 is an explanatory diagram for explaining the period widths HH and HV of the horizontal synchronization signal and the vertical synchronization signal. However, for convenience of illustration, FIG. 5 shows the waveform of the composite video signal. If the resolution of the input synchronization signal is determined not only based on the frequency of the synchronization signal but also based on the period widths HH and HV and the presence or absence of interlace, errors in determining the resolution can be reduced.

The horizontal resolution and the vertical resolution determined by the resolution determining unit 28 are given to the address controller 58 via the CPU access controller 60 (FIG. 3). The scaling unit 70 in the address controller 58 executes the enlargement / reduction of the image as described in FIG. 2 in order to convert these resolutions to the standard resolution of the LCD panel 40.

FIG. 6 is a block diagram showing the internal configuration of the scaling unit 70. The scaling unit 70 includes a PLL circuit 142, a frequency divider 144, a horizontal address forming unit 146, a vertical address forming unit 148, a three-state buffer unit 160, and an inverter 162. The data latch 164 shown in FIG. 6 is a circuit in the DRAM controller 56. The horizontal address forming unit 146 includes a latch miss elimination circuit 150, a first counter 152, and a first latch 154. The vertical address forming section 148 has a second counter 156 and a second latch 158.

The PLL circuit 142 generates a second dot clock signal DCKX having a frequency that is N times as high as that of the horizontal synchronization signal HSYNC2 for reading. The frequency divider 144 generates a line increment signal LINCX by dividing the read dot clock signal DCK2 by 1 / M. The set values N and M in the PLL circuit 142 and the frequency divider 144 are values for converting the resolution of the input video signal VPC to the resolution of the LCD panel 40, and are set by the CPU 20, respectively. The method for determining these set values N and M will be described later.

FIG. 7 is a timing chart showing the operation of the vertical address forming unit 148. The second counter 156 counts the number of pulses of the line increment signal LINCX after being reset by the vertical synchronizing signal VSYNC2 for reading (FIG. 7A). The count value HC (FIG. 7D) of the second counter 156 is latched in response to the rising edge of the horizontal synchronization signal HSYNC2, and is supplied to the three-state buffer 160 as a vertical address VADD. In the example of FIG. 7E, the value of the vertical address VADD is updated as 0, 1, 1, 2,....

FIG. 8 is an explanatory diagram showing how the image is enlarged. FIG. 8A shows video data stored in the frame memory 34, and FIG. 8B shows enlarged video data. Also, the numbers described in the respective frames in these figures are the values of the video data. In the timing chart of FIG. 7E, the image on the scanning line with VADD = 0 is read once, the image on the scanning line with VADD = 1 twice, the image on the scanning line with VADD = 2 twice, and so on. , The video data is read from the frame memory 34. Therefore, the read image is enlarged in the vertical direction as shown in FIG. The magnification MV2 in the vertical direction is given by the ratio of the frequency fHSYNC2 of the horizontal synchronization signal HSYNC2 to the frequency fLINCX of the line increment signal LINCX. Therefore, by adjusting the set value M of the frequency divider 144 (FIG. 7), it is possible to enlarge the image at an arbitrary magnification in the vertical direction. If the value of the magnification MV2 is set to 1 or less, the image can be reduced in the vertical direction.

FIG. 9 is a timing chart showing the operation of the horizontal address forming unit 146. The latch miss elimination circuit 150 (FIG. 6) responds to the first and second dot clock signals DCK2 and DCKX (FIGS. 9 (b) and 9 (d)) to generate a third dot clock signal DCKXX (FIG. 9 (e)). Generate

FIG. 10 is a block diagram showing an internal configuration of the latch miss elimination circuit 150. The latch miss elimination circuit 150 includes a delay unit 170, an EXNOR circuit 172, and a D-type flip-flop 174. The output signal DKFF of the EXNOR circuit 172 is a signal obtained by taking an exclusive OR of the first dot clock signal DCK2 and a signal obtained by delaying the dot clock signal DCK2 by a predetermined time and inverting the result. Therefore, as shown in FIG. 9C, the signal DKFF indicates the rising and falling timings of the first dot clock signal DCK2.

The output signal DKFF of the EXNOR circuit 172 is given to the clock input terminal of the flip-flop 174. A second dot clock signal DCKX is supplied to a D input terminal of the flip-flop 174. Accordingly, the third dot clock signal DCKXX output from the flip-flop 174 is, as shown in FIG. 9E, the second dot clock signal DCKX at the rising edge of the output signal DKFF of the EXNOR circuit 172. This signal indicates a level. The third dot clock signal DCKXX has the same frequency as the second dot clock signal DCKX. Further, since the output signal DKFF of the EXNOR circuit 172 rises with a delay of a predetermined delay time from the edge of the first dot clock signal DCK2, the timing of the level change of the third dot clock signal DCKXX also changes with the first dot. It is delayed by a predetermined delay time from the edge of the clock signal DCK2. The reason why such a third dot clock signal DCKXX is generated by the latch miss elimination circuit 150 is to prevent the value of the horizontal address latched by the first latch 154 from becoming unstable. Will be further described later.

The first counter 152 (FIG. 6) of the horizontal address forming unit 146 counts up the number of pulses of the third dot clock signal DCKXX generated by the latch miss elimination circuit 150 after being reset by the pulse of the horizontal synchronization signal HSYNC2. Then, the count value DC (FIG. 9F) is supplied to the first latch 154. By the way, since the third dot clock signal DCKXX has the same frequency as the second dot clock signal DCKX, the count value DC of the first counter 152 is substantially equal to the pulse of the second dot clock signal DCKX. Indicates a number. The first latch 154 latches the count value DC in synchronization with the first dot clock signal DCK2, and supplies the count value DC to the three-state buffer 160 as a horizontal address HADD (FIG. 9 (g)). That is, the horizontal address HADD is a value indicating the number of pulses of the second dot clock signal DCKX, and the value is updated according to the rising edge of the first dot clock signal DCK2. Therefore, by adjusting the frequency fDCK2 of the first dot clock signal DCK2 and the frequency fDCKX of the second dot clock signal DCKX, it is possible to set how to update the value of the horizontal address HADD. In the example of FIG. 9G, it can be seen that the value of the horizontal address HADD changes as 0, 0, 1.

FIGS. 8A and 8B show how the video is enlarged in accordance with the update of the horizontal address HADD in FIG. 9G. The timing chart shown in FIG. 9 corresponds to the timing of the horizontal address generation on the uppermost scanning line where the vertical address VADD is 0. As shown in FIG. 9G, the horizontal address HADD has been updated to 0, 0, 1. Therefore, on this scanning line, the video data of the pixel of the horizontal address HADD = 0 is read twice, and then the video data of the pixel of the HADD = 1 is once. The data is sequentially read from the memory 34.

(5) Thus, the horizontal address HADD depends on the relationship between the frequencies of the two dot clock signals DCK2 and DCKX. Therefore, by adjusting the frequency of the dot clock signals DCK2 and DCKX, the image can be enlarged / reduced in the horizontal direction. That is, the horizontal magnification MH2 of the video at the time of reading is given by the ratio of the frequency fDCK2 of the first dot clock signal DCK2 to the frequency fDCKX of the second dot clock signal DCKX, as shown in the lower part of FIG. Can be Therefore, by adjusting the set value N of the PLL circuit 142, it is possible to enlarge / reduce an image at an arbitrary magnification in the horizontal direction.

The reason why the signal DCKXX is generated by the latch miss elimination circuit 150 is as follows. As shown in FIG. 9F, the count value DC of the first counter 152 becomes the third dot clock signal DCKXX (FIG. 9) after the horizontal synchronization signal HSYNC2 (FIG. 9A) returns to the H level. It changes in synchronization with the rising edge of (e)). On the other hand, as described above, since the edge of the third dot clock signal DCKXX is delayed by a predetermined time from the edge of the first dot clock signal DCK2, the timing of the latch in the first latch 154 becomes the count value DC. Of the horizontal address HADD, and therefore, the value of the horizontal address HADD does not become unstable.

As described above, by adjusting the set value N of the PLL circuit 142 and the set value M of the frequency divider 144 shown in FIG. 6, the horizontal magnification MH2 and the vertical magnification MV2 are respectively set as shown in the lower part of FIG. It can be set independently. Therefore, the horizontal scaling factor MH2 is set equal to (the horizontal resolution of the LCD panel 40) / (the horizontal resolution of the input video signal VPC), and the vertical scaling factor MV2 is set to (the vertical resolution of the LCD panel 40) / (input video signal). If it is set equal to (vertical resolution of VPC), an image can be displayed on the entire screen of the LCD panel 40.

FIG. 11 is a block diagram showing a configuration of a down converter according to a second embodiment of the present invention. This downconverter adds a video signal selection unit 200 to the input unit of the liquid crystal projector shown in FIG. John 204, video player 206, and CD-RAM 208
).

The video signal selection unit 200 receives two types of television video signals STV1 and STV2 in addition to the video signal {VPC, SYNC} generated by the personal computer, and is a selector that selects one of them. is there. The television video signals STV1 and STV2 are composite video signals including synchronization signals. When selecting a composite video signal, a decoder (not shown) in the video signal selection unit 200 generates a component video signal VIN and a synchronization signal SYNC from the composite video signal.

The video encoder 202 generates a composite video signal from the digital video signal DOUT output from the video scaler 36 and the read synchronization signals (DCK2, HSYNC2, VSYNC2). This composite video signal is supplied to the television 204 and the video player 206. When writing an image on the CD-RAM 208 (writable compact disk device), the video encoder supplies the digital image signal DOUT and the readout synchronization signal to the CD-RAM 208 without generating a composite image signal. Since the video scaler 36 can change the video to a desired resolution, the video can be output at a desired resolution according to various output devices by setting the resolution by the user. The reason why the apparatus shown in FIG. 11 is called a “down converter” means that various input video signals can be converted into various output video signals.

The present invention is not limited to the above-described examples and embodiments, and can be carried out in various modes without departing from the gist of the present invention. For example, the following modifications are possible.

(1) The functions of the frequency determination unit 26 and the resolution determination unit 28 (FIG. 1) realized by the software processing in the above embodiment can be realized by a hardware circuit.

(2) In the above embodiment, the enlargement / reduction is performed when the video is read from the frame memory 34. However, the enlargement / reduction may be performed when the video is written to the frame memory 34. is there.

(3) As a method of performing enlargement / reduction, a method other than the frequency control described above can be applied. For example, it is also possible to change the address by multiplying the read address or the write address by a coefficient, and thereby enlarge or reduce the address. FIG. 12 is an explanatory diagram showing a method of enlarging / reducing an image by multiplying a read address by a coefficient K. FIG. 12A shows an image stored in the frame memory 34, and FIGS. 12B1 to 12B3 show images which are displayed after being enlarged or reduced. Di, j indicates image data written at the address (i, j) in the frame memory 34.

In FIG. 12, assuming that the memory resolution is Mx (dot) × My (line) and the display resolution is Nx (dot) × Ny (line), a coefficient K (Kx, Ky) for multiplying the address is represented by the following equation. Given by

Kx = Mx / Nx (1a)
Ky = My / Ny (1b)

The read address (XADD, YADD) for reading image data from the frame memory 34 is converted into a new read address (XADD ', YADD') by the following equation.

XADD '= INT (Kx × XADD) (2a)
YADD '= INT (Ky × YADD) (2b)

演算 子 Here, the operator INT () represents an operation that takes an integer part in parentheses.

FIG. 12B1 is an example of an image displayed when the coefficients Kx and Ky are larger than 1.0 (for example, when Kx = Ky = 2.0). When the original horizontal address XADD increases by 1, 0, 1, 2,..., The converted horizontal address XADD ′ becomes (2a
) According to 0, 2, 4. The same applies to the vertical address YADD. Since the image data is read from the frame memory 34 in accordance with the read addresses XADD 'and YADD', the image is reduced and displayed as shown in FIG. 12 (B1). At this time, the horizontal magnification and the vertical magnification are equal to 1 / Kx and 1 / Ky, respectively.

画像 As shown in FIG. 12 (B2), when the coefficients Kx and Ky are equal to 1.0, the image in the frame memory 34 is displayed at the same magnification.

FIG. 12B3 is an example of an image displayed when the coefficients Kx and Ky are smaller than 1.0 (for example, when Kx = Ky = 0.7). When the original horizontal address XADD increases by 1, 0, 1, 2, 3..., The converted vertical address XADD ′ becomes 0, 0
, 1, 2,... The same applies to the vertical address YADD. Since image data is read from the frame memory 34 in accordance with the read addresses XADD 'and YADD', the image is enlarged and displayed as shown in FIG. 12 (B3).

The values of Kx and Ky can be independently set to arbitrary values.

(4) If a high-speed read / write memory such as a synchronous DRAM is used as the frame memory 34, high-speed read / write of an image signal can be performed.

FIG. 1 is a block diagram showing a configuration of a liquid crystal projector according to a first embodiment of the present invention. FIG. 4 is an explanatory diagram showing functions of the video scaler 36. FIG. 2 is a block diagram showing an internal configuration of the video scaler 36. FIG. 4 is an explanatory diagram showing the contents of a resolution determination table. FIG. 3 is an explanatory diagram showing a waveform of a composite video signal. FIG. 3 is a block diagram showing an internal configuration of a scaling unit 70. 6 is a timing chart showing a vertical address forming operation. FIG. 4 is an explanatory diagram showing an enlarged image. 6 is a timing chart illustrating an operation of forming a horizontal address. FIG. 2 is a block diagram showing an internal configuration of a latch miss elimination circuit 150. FIG. 7 is a block diagram showing a configuration of a down converter according to a second embodiment of the present invention. FIG. 4 is an explanatory diagram showing a method of enlarging / reducing an image by multiplying a read address by a coefficient K;

Explanation of reference numerals

20 ... CPU
Reference Signs List 22 main memory 24 input panel 26 frequency determining unit 28 resolution determining unit 32 A / D converter 34 frame memory 36 video scaler 38 LCD driver 40 LCD panel 42 light source 50 color conversion unit 52 .. Write synchronization signal generator 54 FIFO buffer 56 DRAM controller 58 Address controller 60 CPU access controllers 61 and 62 FIFO buffer 64 Filter 66 Color converter 68 Read synchronization signal generator 70 Scaling unit Reference Signs List 100 personal computer 142 PLL circuit 144 frequency divider 146 horizontal address forming unit 148 vertical address forming unit 150 latch miss elimination circuit 152 counter 154 latch 156 counter 158 latch 162 a Converter 164 ... data latch 170 ... delay unit 172 ... EXNOR circuit 174 ... D-type flip-flop 200 ... video signal selection section 202 ... video encoder 204 ... television 206 ... video player 208 ... CD-RAM

Claims (7)

A light source,
An optical modulator;
Resolution determination means for determining the horizontal resolution and the vertical resolution of the input video signal,
Scaling means for processing the video signal so that the horizontal resolution of the video signal matches the standard horizontal resolution of the light modulator,
A display device comprising:
A display device for displaying an image based on the image signal processed by the scaling means. The display device according to claim 1, wherein the scaling means processes the video signal so that a vertical resolution of the video signal matches a standard vertical resolution of the display device. A light source,
An optical modulator;
Resolution determination means for determining the horizontal resolution and the vertical resolution of the input video signal,
Scaling means for processing the video signal so that the vertical resolution of the video signal matches the standard vertical resolution of the light modulator,
A display device comprising:
A display device for displaying an image based on the image signal processed by the scaling means. The display device according to claim 3, wherein the scaling means processes the video signal such that a horizontal resolution of the video signal matches a standard horizontal resolution of the display device. The display device according to claim 1, wherein:
The resolution determining means,
A frequency detection unit that detects the frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal of the video signal,
Means for determining a horizontal resolution and a vertical resolution of the video signal based on at least the detected frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal,
Display device. The display device according to claim 1, wherein:
A plurality of input units each capable of receiving an input video signal,
A video signal selector that selects one input video signal from the input video signals received by the plurality of input units,
The one selected input video signal is the video signal,
Display device. The display device according to any one of claims 1 to 6, wherein the display device is a projector.

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